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Searched refs:SH7750_STBCR2_MSTP5 (Results 1 – 1 of 1) sorted by relevance

/openbmc/qemu/hw/sh4/
H A Dsh7750_regs.h341 #define SH7750_STBCR2_MSTP5 0x01 /* Stopping the clock supply to the */ macro
343 #define SH7750_STBCR2_UBC_STP SH7750_STBCR2_MSTP5