Searched refs:SET_RD (Results 1 – 4 of 4) sorted by relevance
/openbmc/linux/arch/riscv/kvm/ |
H A D | vcpu_insn.c | 129 #define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val)) macro 241 SET_RD(insn, &vcpu->arch.guest_context, in kvm_riscv_vcpu_csr_return() 727 SET_RD(insn, &vcpu->arch.guest_context, in kvm_riscv_vcpu_mmio_return() 732 SET_RD(insn, &vcpu->arch.guest_context, in kvm_riscv_vcpu_mmio_return() 737 SET_RD(insn, &vcpu->arch.guest_context, in kvm_riscv_vcpu_mmio_return() 742 SET_RD(insn, &vcpu->arch.guest_context, in kvm_riscv_vcpu_mmio_return()
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/openbmc/qemu/target/riscv/ |
H A D | cpu_helper.c | 1441 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); in riscv_transformed_insn() 1449 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); in riscv_transformed_insn() 1457 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); in riscv_transformed_insn() 1463 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); in riscv_transformed_insn() 1509 xinsn = SET_RD(xinsn, GET_C_RD(insn)); in riscv_transformed_insn() 1517 xinsn = SET_RD(xinsn, GET_C_RD(insn)); in riscv_transformed_insn() 1525 xinsn = SET_RD(xinsn, GET_C_RD(insn)); in riscv_transformed_insn() 1531 xinsn = SET_RD(xinsn, GET_C_RD(insn)); in riscv_transformed_insn()
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H A D | instmap.h | 325 #define SET_RD(inst, val) deposit32(inst, 7, 5, val) macro
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/openbmc/linux/arch/riscv/kernel/ |
H A D | traps_misaligned.c | 143 #define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val)) macro 314 SET_RD(insn, regs, val.data_ulong << shift >> shift); in handle_misaligned_load()
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