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Searched refs:SET_RD (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/arch/riscv/kvm/
H A Dvcpu_insn.c129 #define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val)) macro
241 SET_RD(insn, &vcpu->arch.guest_context, in kvm_riscv_vcpu_csr_return()
727 SET_RD(insn, &vcpu->arch.guest_context, in kvm_riscv_vcpu_mmio_return()
732 SET_RD(insn, &vcpu->arch.guest_context, in kvm_riscv_vcpu_mmio_return()
737 SET_RD(insn, &vcpu->arch.guest_context, in kvm_riscv_vcpu_mmio_return()
742 SET_RD(insn, &vcpu->arch.guest_context, in kvm_riscv_vcpu_mmio_return()
/openbmc/linux/arch/riscv/kernel/
H A Dtraps_misaligned.c141 #define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val)) macro
280 SET_RD(insn, regs, val.data_ulong << shift >> shift); in handle_misaligned_load()
/openbmc/qemu/target/riscv/
H A Dcpu_helper.c1602 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); in riscv_transformed_insn()
1610 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); in riscv_transformed_insn()
1618 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); in riscv_transformed_insn()
1624 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); in riscv_transformed_insn()
1670 xinsn = SET_RD(xinsn, GET_C_RD(insn)); in riscv_transformed_insn()
1678 xinsn = SET_RD(xinsn, GET_C_RD(insn)); in riscv_transformed_insn()
1686 xinsn = SET_RD(xinsn, GET_C_RD(insn)); in riscv_transformed_insn()
1692 xinsn = SET_RD(xinsn, GET_C_RD(insn)); in riscv_transformed_insn()
H A Dinstmap.h325 #define SET_RD(inst, val) deposit32(inst, 7, 5, val) macro