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Searched refs:SET_IDREG (Results 1 – 8 of 8) sorted by relevance

/openbmc/qemu/target/arm/tcg/
H A Dcpu-v7m.c62 SET_IDREG(isar, ID_PFR0, 0x00000030); in cortex_m0_initfn()
63 SET_IDREG(isar, ID_PFR1, 0x00000200); in cortex_m0_initfn()
64 SET_IDREG(isar, ID_DFR0, 0x00100000); in cortex_m0_initfn()
65 SET_IDREG(isar, ID_AFR0, 0x00000000); in cortex_m0_initfn()
66 SET_IDREG(isar, ID_MMFR0, 0x00000030); in cortex_m0_initfn()
67 SET_IDREG(isar, ID_MMFR1, 0x00000000); in cortex_m0_initfn()
68 SET_IDREG(isar, ID_MMFR2, 0x00000000); in cortex_m0_initfn()
69 SET_IDREG(isar, ID_MMFR3, 0x00000000); in cortex_m0_initfn()
70 SET_IDREG(isar, ID_ISAR0, 0x01141110); in cortex_m0_initfn()
71 SET_IDREG(isar, ID_ISAR1, 0x02111000); in cortex_m0_initfn()
[all …]
H A Dcpu64.c52 SET_IDREG(isar, ID_PFR0, 0x00000131); in aarch64_a35_initfn()
53 SET_IDREG(isar, ID_PFR1, 0x00011011); in aarch64_a35_initfn()
54 SET_IDREG(isar, ID_DFR0, 0x03010066); in aarch64_a35_initfn()
55 SET_IDREG(isar, ID_AFR0, 0); in aarch64_a35_initfn()
56 SET_IDREG(isar, ID_MMFR0, 0x10201105); in aarch64_a35_initfn()
57 SET_IDREG(isar, ID_MMFR1, 0x40000000); in aarch64_a35_initfn()
58 SET_IDREG(isar, ID_MMFR2, 0x01260000); in aarch64_a35_initfn()
59 SET_IDREG(isar, ID_MMFR3, 0x02102211); in aarch64_a35_initfn()
60 SET_IDREG(isar, ID_ISAR0, 0x02101110); in aarch64_a35_initfn()
61 SET_IDREG(isa in aarch64_a35_initfn()
[all...]
H A Dcpu32.c36 SET_IDREG(isar, ID_ISAR5, t); in aa32_max_features()
46 SET_IDREG(isar, ID_ISAR6, t); in aa32_max_features()
66 SET_IDREG(isar, ID_MMFR4, t); in aa32_max_features()
74 SET_IDREG(isar, ID_PFR0, t); in aa32_max_features()
79 SET_IDREG(isar, ID_PFR2, t); in aa32_max_features()
85 SET_IDREG(isar, ID_DFR0, t); in aa32_max_features()
225 SET_IDREG(isar, ID_PFR0, 0x111); in arm1136_r2_initfn()
226 SET_IDREG(isar, ID_PFR1, 0x1); in arm1136_r2_initfn()
227 SET_IDREG(isar, ID_DFR0, 0x2); in arm1136_r2_initfn()
228 SET_IDREG(isa in arm1136_r2_initfn()
[all...]
/openbmc/qemu/target/arm/
H A Dcpu64.c138 SET_IDREG(&cpu->isar, ID_AA64ZFR0, 0); in arm_cpu_sve_finalize()
266 SET_IDREG(&cpu->isar, ID_AA64ZFR0, t); in arm_cpu_sve_finalize()
337 SET_IDREG(&cpu->isar, ID_AA64SMFR0, 0); in arm_cpu_sme_finalize()
582 SET_IDREG(isar, ID_AA64ISAR1, isar1); in arm_cpu_pauth_finalize()
583 SET_IDREG(isar, ID_AA64ISAR2, isar2); in arm_cpu_pauth_finalize()
635 SET_IDREG(&cpu->isar, ID_AA64MMFR0, t); in arm_cpu_lpa2_finalize()
662 SET_IDREG(isar, ID_PFR0, 0x00000131); in aarch64_a57_initfn()
663 SET_IDREG(isar, ID_PFR1, 0x00011011); in aarch64_a57_initfn()
664 SET_IDREG(isar, ID_DFR0, 0x03010066); in aarch64_a57_initfn()
665 SET_IDREG(isa in aarch64_a57_initfn()
[all...]
H A Dcpu.c1783 SET_IDREG(isar, ID_ISAR6, u); in arm_cpu_post_init()
1825 SET_IDREG(isar, ID_AA64ISAR0, t); in arm_cpu_post_init()
1831 SET_IDREG(isar, ID_AA64ISAR1, t); in arm_cpu_post_init()
1841 SET_IDREG(isar, ID_ISAR5, u); in arm_cpu_post_init()
1848 SET_IDREG(isar, ID_ISAR6, u); in arm_cpu_post_init()
1891 SET_IDREG(isar, ID_ISAR2, u); in arm_cpu_post_init()
1896 SET_IDREG(isar, ID_ISAR3, u); in arm_cpu_finalizefn()
H A Dkvm.c323 SET_IDREG(&ahcf->isar, ID_AA64PFR0, 0x00000011); /* EL1&0, AArch64 only */ in kvm_arm_get_host_cpu_features()
H A Dcpu.h896 #define SET_IDREG(ISAR, REG, VALUE) \
889 #define SET_IDREG( global() macro
/openbmc/qemu/target/arm/hvf/
H A Dhvf.c741 SET_IDREG(isar, ID_AA64MMFR0, id_aa64mmfr0); in hvf_put_registers()
805 SET_IDREG(&host_isar, ID_AA64PFR1, in hvf_put_registers()