Home
last modified time | relevance | path

Searched refs:SERIRQ_CNTL (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/x86/include/asm/
H A Dpch_common.h35 #define SERIRQ_CNTL 0x64 macro
/openbmc/u-boot/arch/x86/cpu/ivybridge/
H A Dlpc.c78 dm_pci_write_config8(pch, SERIRQ_CNTL, value); in pch_enable_serial_irqs()
80 dm_pci_write_config8(pch, SERIRQ_CNTL, value | (1 << 6)); in pch_enable_serial_irqs()
/openbmc/u-boot/arch/x86/include/asm/arch-ivybridge/
H A Dpch.h57 #define SERIRQ_CNTL 0x64 macro
/openbmc/u-boot/arch/x86/cpu/broadwell/
H A Dpch.c106 dm_pci_clrset_config8(dev, SERIRQ_CNTL, 0, 1 << 7 | 1 << 6); in pch_misc_init()