Searched refs:SERDES_CR_CTL (Results 1 – 2 of 2) sorted by relevance
| /openbmc/u-boot/board/highbank/ |
| H A D | ahci.c | 16 #define SERDES_CR_CTL 0x80a0 macro
60 while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY) in combo_phy_read()
63 __combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_START); in combo_phy_read()
64 while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY) in combo_phy_read()
74 while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY) in combo_phy_write()
78 __combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_WR_RDN | CR_START); in combo_phy_write()
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| /openbmc/linux/drivers/ata/ |
| H A D | sata_highbank.c | 29 #define SERDES_CR_CTL 0x80a0 macro
236 while (__combo_phy_reg_read(sata_port, SERDES_CR_CTL) & CR_BUSY) in combo_phy_wait_for_ready()
244 __combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_START); in combo_phy_read()
254 __combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_WR_RDN | CR_START); in combo_phy_write()
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