Searched refs:SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_SET (Results 1 – 2 of 2) sorted by relevance
996 sdx5_inst_rmw(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_SET(3), in sparx5_cmu_apply_cfg()
2132 #define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_SET(x)\ macro