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Searched refs:SDR_PHYGRP_SCCGRP_ADDRESS (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/drivers/ddr/altera/
H A Dsequencer.h83 #define SDR_PHYGRP_SCCGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x0) macro
H A Dsequencer.c22 (SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
260 writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2)); in scc_mgr_set()
477 const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | in scc_mgr_set_hhp_extras()
2324 const s32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | delay_off; in center_dq_windows()
2393 SDR_PHYGRP_SCCGRP_ADDRESS + SCC_MGR_DQS_IN_DELAY_OFFSET + in rw_mgr_mem_calibrate_vfifo_center()
2971 start_dqs = readl((SDR_PHYGRP_SCCGRP_ADDRESS | in rw_mgr_mem_calibrate_writes_center()
3262 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS | in mem_skip_calibrate()
3328 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS | in mem_calibrate()
3377 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS | in mem_calibrate()