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Searched refs:SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dwrap_sdram_config.c43 SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) |
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dsdram_gen5.h241 #define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18 macro