1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (c) 2016 Google, Inc 4 */ 5 #ifndef _ASM_ARCH_SDRAM_AST2500_H 6 #define _ASM_ARCH_SDRAM_AST2500_H 7 8 #define SDRAM_UNLOCK_KEY 0xfc600309 9 #define SDRAM_VIDEO_UNLOCK_KEY 0x2003000f 10 11 #define SDRAM_PCR_CKE_EN (1 << 0) 12 #define SDRAM_PCR_AUTOPWRDN_EN (1 << 1) 13 #define SDRAM_PCR_CKE_DELAY_SHIFT 4 14 #define SDRAM_PCR_CKE_DELAY_MASK 7 15 #define SDRAM_PCR_RESETN_DIS (1 << 7) 16 #define SDRAM_PCR_ODT_EN (1 << 8) 17 #define SDRAM_PCR_ODT_AUTO_ON (1 << 10) 18 #define SDRAM_PCR_ODT_EXT_EN (1 << 11) 19 #define SDRAM_PCR_TCKE_PW_SHIFT 12 20 #define SDRAM_PCR_TCKE_PW_MASK 7 21 #define SDRAM_PCR_RGAP_CTRL_EN (1 << 15) 22 #define SDRAM_PCR_MREQI_DIS (1 << 17) 23 24 /* Fixed priority DRAM Requests mask */ 25 #define SDRAM_REQ_VGA_HW_CURSOR (1 << 0) 26 #define SDRAM_REQ_VGA_TEXT_CG_FONT (1 << 1) 27 #define SDRAM_REQ_VGA_TEXT_ASCII (1 << 2) 28 #define SDRAM_REQ_VGA_CRT (1 << 3) 29 #define SDRAM_REQ_SOC_DC_CURSOR (1 << 4) 30 #define SDRAM_REQ_SOC_DC_OCD (1 << 5) 31 #define SDRAM_REQ_SOC_DC_CRT (1 << 6) 32 #define SDRAM_REQ_VIDEO_HIPRI_WRITE (1 << 7) 33 #define SDRAM_REQ_USB20_EHCI1 (1 << 8) 34 #define SDRAM_REQ_USB20_EHCI2 (1 << 9) 35 #define SDRAM_REQ_CPU (1 << 10) 36 #define SDRAM_REQ_AHB2 (1 << 11) 37 #define SDRAM_REQ_AHB (1 << 12) 38 #define SDRAM_REQ_MAC0 (1 << 13) 39 #define SDRAM_REQ_MAC1 (1 << 14) 40 #define SDRAM_REQ_PCIE (1 << 16) 41 #define SDRAM_REQ_XDMA (1 << 17) 42 #define SDRAM_REQ_ENCRYPTION (1 << 18) 43 #define SDRAM_REQ_VIDEO_FLAG (1 << 21) 44 #define SDRAM_REQ_VIDEO_LOW_PRI_WRITE (1 << 28) 45 #define SDRAM_REQ_2D_RW (1 << 29) 46 #define SDRAM_REQ_MEMCHECK (1 << 30) 47 48 #define SDRAM_ICR_RESET_ALL (1 << 31) 49 50 #define SDRAM_CONF_CAP_SHIFT 0 51 #define SDRAM_CONF_CAP_MASK 3 52 #define SDRAM_CONF_DDR4 (1 << 4) 53 #define SDRAM_CONF_SCRAMBLE (1 << 8) 54 #define SDRAM_CONF_ECC_EN (1 << 7) 55 #define SDRAM_CONF_SCRAMBLE_PAT2 (1 << 9) 56 #define SDRAM_CONF_CACHE_EN (1 << 10) 57 #define SDRAM_CONF_CACHE_ADDR_CTRL (1 << 11) 58 #define SDRAM_CONF_CACHE_INIT_EN (1 << 12) 59 #define SDRAM_CONF_DUALX8 (1 << 13) 60 #define SDRAM_CONF_CACHE_INIT_DONE (1 << 19) 61 62 #define SDRAM_CONF_CAP_128M 0 63 #define SDRAM_CONF_CAP_256M 1 64 #define SDRAM_CONF_CAP_512M 2 65 #define SDRAM_CONF_CAP_1024M 3 66 67 #define SDRAM_MISC_DDR4_TREFRESH (1 << 3) 68 69 #define SDRAM_PHYCTRL0_INIT (1 << 0) 70 #define SDRAM_PHYCTRL0_AUTO_UPDATE (1 << 1) 71 #define SDRAM_PHYCTRL0_NRST (1 << 2) 72 73 #define SDRAM_REFRESH_CYCLES_SHIFT 0 74 #define SDRAM_REFRESH_CYCLES_MASK 0xf 75 #define SDRAM_REFRESH_ZQCS_EN (1 << 7) 76 #define SDRAM_REFRESH_PERIOD_SHIFT 8 77 #define SDRAM_REFRESH_PERIOD_MASK 0xf 78 79 #define SDRAM_TEST_LEN_SHIFT 4 80 #define SDRAM_TEST_LEN_MASK 0xfffff 81 #define SDRAM_TEST_START_ADDR_SHIFT 24 82 #define SDRAM_TEST_START_ADDR_MASK 0x3f 83 84 #define SDRAM_TEST_EN (1 << 0) 85 #define SDRAM_TEST_MODE_SHIFT 1 86 #define SDRAM_TEST_MODE_MASK 3 87 #define SDRAM_TEST_MODE_WO 0 88 #define SDRAM_TEST_MODE_RB 1 89 #define SDRAM_TEST_MODE_RW 2 90 #define SDRAM_TEST_GEN_MODE_SHIFT 3 91 #define SDRAM_TEST_GEN_MODE_MASK 7 92 #define SDRAM_TEST_TWO_MODES (1 << 6) 93 #define SDRAM_TEST_ERRSTOP (1 << 7) 94 #define SDRAM_TEST_DONE (1 << 12) 95 #define SDRAM_TEST_FAIL (1 << 13) 96 97 #define SDRAM_AC_TRFC_SHIFT 0 98 #define SDRAM_AC_TRFC_MASK 0xff 99 100 #ifndef __ASSEMBLY__ 101 102 struct ast2500_sdrammc_regs { 103 u32 protection_key; /* offset 0x00 */ 104 u32 config; /* offset 0x04 */ 105 u32 gm_protection_key; /* offset 0x08 */ 106 u32 refresh_timing; /* offset 0x0C */ 107 u32 ac_timing[3]; /* offset 0x10 ~ 0x18 */ 108 u32 misc_control; /* offset 0x0C */ 109 u32 mr46_mode_setting; /* offset 0x20 */ 110 u32 mr5_mode_setting; /* offset 0x24 */ 111 u32 mode_setting_control; /* offset 0x28 */ 112 u32 mr02_mode_setting; /* offset 0x2C */ 113 u32 mr13_mode_setting; /* offset 0x30 */ 114 u32 power_control; /* offset 0x34 */ 115 u32 req_limit_mask; /* offset 0x38 */ 116 u32 pri_group_setting; /* offset 0x3C */ 117 u32 max_grant_len[4]; /* offset 0x40 ~ 0x4C */ 118 u32 intr_ctrl; /* offset 0x50 */ 119 u32 ecc_range_ctrl; /* offset 0x54 */ 120 u32 first_ecc_err_addr; /* offset 0x58 */ 121 u32 last_ecc_err_addr; /* offset 0x5C */ 122 u32 phy_ctrl[4]; /* offset 0x60 ~ 0x6C */ 123 u32 ecc_test_ctrl; /* offset 0x70 */ 124 u32 test_addr; /* offset 0x74 */ 125 u32 test_fail_dq_bit; /* offset 0x78 */ 126 u32 test_init_val; /* offset 0x7C */ 127 u32 phy_debug_ctrl; 128 u32 phy_debug_data; 129 u32 reserved1[30]; 130 u32 scu_passwd; 131 u32 reserved2[7]; 132 u32 scu_mpll; 133 u32 reserved3[19]; 134 u32 scu_hwstrap; 135 }; 136 137 #endif /* __ASSEMBLY__ */ 138 139 #endif /* _ASM_ARCH_SDRAM_AST2500_H */ 140