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Searched refs:SDRAM_CONF_CACHE_ADDR_CTRL (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-aspeed/
H A Dsdram_ast2500.h57 #define SDRAM_CONF_CACHE_ADDR_CTRL (1 << 11) macro
/openbmc/u-boot/drivers/ram/aspeed/
H A Dsdram_ast2500.c300 (SDRAM_CONF_ECC_EN | SDRAM_CONF_CACHE_ADDR_CTRL); in ast2500_sdrammc_ecc_enable()