1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __SDMA_V6_0_0_PKT_OPEN_H_ 24 #define __SDMA_V6_0_0_PKT_OPEN_H_ 25 26 #define SDMA_OP_NOP 0 27 #define SDMA_OP_COPY 1 28 #define SDMA_OP_WRITE 2 29 #define SDMA_OP_INDIRECT 4 30 #define SDMA_OP_FENCE 5 31 #define SDMA_OP_TRAP 6 32 #define SDMA_OP_SEM 7 33 #define SDMA_OP_POLL_REGMEM 8 34 #define SDMA_OP_COND_EXE 9 35 #define SDMA_OP_ATOMIC 10 36 #define SDMA_OP_CONST_FILL 11 37 #define SDMA_OP_PTEPDE 12 38 #define SDMA_OP_TIMESTAMP 13 39 #define SDMA_OP_SRBM_WRITE 14 40 #define SDMA_OP_PRE_EXE 15 41 #define SDMA_OP_GPUVM_INV 16 42 #define SDMA_OP_GCR_REQ 17 43 #define SDMA_OP_DUMMY_TRAP 32 44 #define SDMA_SUBOP_TIMESTAMP_SET 0 45 #define SDMA_SUBOP_TIMESTAMP_GET 1 46 #define SDMA_SUBOP_TIMESTAMP_GET_GLOBAL 2 47 #define SDMA_SUBOP_COPY_LINEAR 0 48 #define SDMA_SUBOP_COPY_LINEAR_SUB_WIND 4 49 #define SDMA_SUBOP_COPY_TILED 1 50 #define SDMA_SUBOP_COPY_TILED_SUB_WIND 5 51 #define SDMA_SUBOP_COPY_T2T_SUB_WIND 6 52 #define SDMA_SUBOP_COPY_SOA 3 53 #define SDMA_SUBOP_COPY_DIRTY_PAGE 7 54 #define SDMA_SUBOP_COPY_LINEAR_PHY 8 55 #define SDMA_SUBOP_COPY_LINEAR_SUB_WIND_LARGE 36 56 #define SDMA_SUBOP_COPY_LINEAR_BC 16 57 #define SDMA_SUBOP_COPY_TILED_BC 17 58 #define SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC 20 59 #define SDMA_SUBOP_COPY_TILED_SUB_WIND_BC 21 60 #define SDMA_SUBOP_COPY_T2T_SUB_WIND_BC 22 61 #define SDMA_SUBOP_WRITE_LINEAR 0 62 #define SDMA_SUBOP_WRITE_TILED 1 63 #define SDMA_SUBOP_WRITE_TILED_BC 17 64 #define SDMA_SUBOP_PTEPDE_GEN 0 65 #define SDMA_SUBOP_PTEPDE_COPY 1 66 #define SDMA_SUBOP_PTEPDE_RMW 2 67 #define SDMA_SUBOP_PTEPDE_COPY_BACKWARDS 3 68 #define SDMA_SUBOP_MEM_INCR 1 69 #define SDMA_SUBOP_DATA_FILL_MULTI 1 70 #define SDMA_SUBOP_POLL_REG_WRITE_MEM 1 71 #define SDMA_SUBOP_POLL_DBIT_WRITE_MEM 2 72 #define SDMA_SUBOP_POLL_MEM_VERIFY 3 73 #define SDMA_SUBOP_VM_INVALIDATION 4 74 #define HEADER_AGENT_DISPATCH 4 75 #define HEADER_BARRIER 5 76 #define SDMA_OP_AQL_COPY 0 77 #define SDMA_OP_AQL_BARRIER_OR 0 78 79 #define SDMA_GCR_RANGE_IS_PA (1 << 18) 80 #define SDMA_GCR_SEQ(x) (((x) & 0x3) << 16) 81 #define SDMA_GCR_GL2_WB (1 << 15) 82 #define SDMA_GCR_GL2_INV (1 << 14) 83 #define SDMA_GCR_GL2_DISCARD (1 << 13) 84 #define SDMA_GCR_GL2_RANGE(x) (((x) & 0x3) << 11) 85 #define SDMA_GCR_GL2_US (1 << 10) 86 #define SDMA_GCR_GL1_INV (1 << 9) 87 #define SDMA_GCR_GLV_INV (1 << 8) 88 #define SDMA_GCR_GLK_INV (1 << 7) 89 #define SDMA_GCR_GLK_WB (1 << 6) 90 #define SDMA_GCR_GLM_INV (1 << 5) 91 #define SDMA_GCR_GLM_WB (1 << 4) 92 #define SDMA_GCR_GL1_RANGE(x) (((x) & 0x3) << 2) 93 #define SDMA_GCR_GLI_INV(x) (((x) & 0x3) << 0) 94 /* 95 ** Definitions for SDMA_PKT_COPY_LINEAR packet 96 */ 97 98 /*define for HEADER word*/ 99 /*define for op field*/ 100 #define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0 101 #define SDMA_PKT_COPY_LINEAR_HEADER_op_mask 0x000000FF 102 #define SDMA_PKT_COPY_LINEAR_HEADER_op_shift 0 103 #define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift) 104 105 /*define for sub_op field*/ 106 #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 0 107 #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask 0x000000FF 108 #define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift 8 109 #define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift) 110 111 /*define for encrypt field*/ 112 #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset 0 113 #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask 0x00000001 114 #define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift 16 115 #define SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift) 116 117 /*define for tmz field*/ 118 #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset 0 119 #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask 0x00000001 120 #define SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift 18 121 #define SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift) 122 123 /*define for cpv field*/ 124 #define SDMA_PKT_COPY_LINEAR_HEADER_cpv_offset 0 125 #define SDMA_PKT_COPY_LINEAR_HEADER_cpv_mask 0x00000001 126 #define SDMA_PKT_COPY_LINEAR_HEADER_cpv_shift 19 127 #define SDMA_PKT_COPY_LINEAR_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_cpv_mask) << SDMA_PKT_COPY_LINEAR_HEADER_cpv_shift) 128 129 /*define for backwards field*/ 130 #define SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset 0 131 #define SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask 0x00000001 132 #define SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift 25 133 #define SDMA_PKT_COPY_LINEAR_HEADER_BACKWARDS(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask) << SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift) 134 135 /*define for broadcast field*/ 136 #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0 137 #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask 0x00000001 138 #define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift 27 139 #define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift) 140 141 /*define for COUNT word*/ 142 /*define for count field*/ 143 #define SDMA_PKT_COPY_LINEAR_COUNT_count_offset 1 144 #define SDMA_PKT_COPY_LINEAR_COUNT_count_mask 0x3FFFFFFF 145 #define SDMA_PKT_COPY_LINEAR_COUNT_count_shift 0 146 #define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift) 147 148 /*define for PARAMETER word*/ 149 /*define for dst_sw field*/ 150 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 2 151 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 152 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 153 #define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) 154 155 /*define for dst_cache_policy field*/ 156 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset 2 157 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask 0x00000007 158 #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift 18 159 #define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift) 160 161 /*define for src_sw field*/ 162 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 2 163 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 164 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 165 #define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) 166 167 /*define for src_cache_policy field*/ 168 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset 2 169 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask 0x00000007 170 #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift 26 171 #define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift) 172 173 /*define for SRC_ADDR_LO word*/ 174 /*define for src_addr_31_0 field*/ 175 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 176 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 177 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 178 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 179 180 /*define for SRC_ADDR_HI word*/ 181 /*define for src_addr_63_32 field*/ 182 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 183 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 184 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 185 #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 186 187 /*define for DST_ADDR_LO word*/ 188 /*define for dst_addr_31_0 field*/ 189 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 190 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 191 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 192 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) 193 194 /*define for DST_ADDR_HI word*/ 195 /*define for dst_addr_63_32 field*/ 196 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 197 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 198 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 199 #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) 200 201 202 /* 203 ** Definitions for SDMA_PKT_COPY_LINEAR_BC packet 204 */ 205 206 /*define for HEADER word*/ 207 /*define for op field*/ 208 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset 0 209 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask 0x000000FF 210 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift 0 211 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift) 212 213 /*define for sub_op field*/ 214 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset 0 215 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask 0x000000FF 216 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift 8 217 #define SDMA_PKT_COPY_LINEAR_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift) 218 219 /*define for COUNT word*/ 220 /*define for count field*/ 221 #define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset 1 222 #define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask 0x003FFFFF 223 #define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift 0 224 #define SDMA_PKT_COPY_LINEAR_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift) 225 226 /*define for PARAMETER word*/ 227 /*define for dst_sw field*/ 228 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset 2 229 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask 0x00000003 230 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift 16 231 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift) 232 233 /*define for dst_ha field*/ 234 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset 2 235 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask 0x00000001 236 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift 19 237 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift) 238 239 /*define for src_sw field*/ 240 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset 2 241 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask 0x00000003 242 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift 24 243 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift) 244 245 /*define for src_ha field*/ 246 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset 2 247 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask 0x00000001 248 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift 27 249 #define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift) 250 251 /*define for SRC_ADDR_LO word*/ 252 /*define for src_addr_31_0 field*/ 253 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset 3 254 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 255 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift 0 256 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift) 257 258 /*define for SRC_ADDR_HI word*/ 259 /*define for src_addr_63_32 field*/ 260 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset 4 261 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 262 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift 0 263 #define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift) 264 265 /*define for DST_ADDR_LO word*/ 266 /*define for dst_addr_31_0 field*/ 267 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset 5 268 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 269 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 270 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift) 271 272 /*define for DST_ADDR_HI word*/ 273 /*define for dst_addr_63_32 field*/ 274 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset 6 275 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 276 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 277 #define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift) 278 279 280 /* 281 ** Definitions for SDMA_PKT_COPY_DIRTY_PAGE packet 282 */ 283 284 /*define for HEADER word*/ 285 /*define for op field*/ 286 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset 0 287 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask 0x000000FF 288 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift 0 289 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift) 290 291 /*define for sub_op field*/ 292 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset 0 293 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask 0x000000FF 294 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift 8 295 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift) 296 297 /*define for tmz field*/ 298 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset 0 299 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask 0x00000001 300 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift 18 301 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift) 302 303 /*define for cpv field*/ 304 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_offset 0 305 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_mask 0x00000001 306 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_shift 19 307 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_shift) 308 309 /*define for all field*/ 310 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset 0 311 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask 0x00000001 312 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift 31 313 #define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift) 314 315 /*define for COUNT word*/ 316 /*define for count field*/ 317 #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset 1 318 #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask 0x003FFFFF 319 #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift 0 320 #define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask) << SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift) 321 322 /*define for PARAMETER word*/ 323 /*define for dst_mtype field*/ 324 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset 2 325 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask 0x00000007 326 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift 3 327 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_MTYPE(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift) 328 329 /*define for dst_l2_policy field*/ 330 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset 2 331 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask 0x00000003 332 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift 6 333 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_L2_POLICY(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift) 334 335 /*define for dst_llc field*/ 336 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_offset 2 337 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_mask 0x00000001 338 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_shift 8 339 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_LLC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_shift) 340 341 /*define for src_mtype field*/ 342 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset 2 343 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask 0x00000007 344 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift 11 345 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_MTYPE(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift) 346 347 /*define for src_l2_policy field*/ 348 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset 2 349 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask 0x00000003 350 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift 14 351 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_L2_POLICY(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift) 352 353 /*define for src_llc field*/ 354 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_offset 2 355 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_mask 0x00000001 356 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_shift 16 357 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_LLC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_shift) 358 359 /*define for dst_sw field*/ 360 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset 2 361 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask 0x00000003 362 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift 17 363 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift) 364 365 /*define for dst_gcc field*/ 366 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset 2 367 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask 0x00000001 368 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift 19 369 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift) 370 371 /*define for dst_sys field*/ 372 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset 2 373 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask 0x00000001 374 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift 20 375 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift) 376 377 /*define for dst_snoop field*/ 378 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset 2 379 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask 0x00000001 380 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift 22 381 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift) 382 383 /*define for dst_gpa field*/ 384 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset 2 385 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask 0x00000001 386 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift 23 387 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift) 388 389 /*define for src_sw field*/ 390 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset 2 391 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask 0x00000003 392 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift 24 393 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift) 394 395 /*define for src_sys field*/ 396 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset 2 397 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask 0x00000001 398 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift 28 399 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift) 400 401 /*define for src_snoop field*/ 402 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset 2 403 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask 0x00000001 404 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift 30 405 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift) 406 407 /*define for src_gpa field*/ 408 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset 2 409 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask 0x00000001 410 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift 31 411 #define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift) 412 413 /*define for SRC_ADDR_LO word*/ 414 /*define for src_addr_31_0 field*/ 415 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset 3 416 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 417 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift 0 418 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift) 419 420 /*define for SRC_ADDR_HI word*/ 421 /*define for src_addr_63_32 field*/ 422 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset 4 423 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 424 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift 0 425 #define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift) 426 427 /*define for DST_ADDR_LO word*/ 428 /*define for dst_addr_31_0 field*/ 429 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset 5 430 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 431 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift 0 432 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift) 433 434 /*define for DST_ADDR_HI word*/ 435 /*define for dst_addr_63_32 field*/ 436 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset 6 437 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 438 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift 0 439 #define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift) 440 441 442 /* 443 ** Definitions for SDMA_PKT_COPY_PHYSICAL_LINEAR packet 444 */ 445 446 /*define for HEADER word*/ 447 /*define for op field*/ 448 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset 0 449 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask 0x000000FF 450 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift 0 451 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift) 452 453 /*define for sub_op field*/ 454 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset 0 455 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask 0x000000FF 456 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift 8 457 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift) 458 459 /*define for tmz field*/ 460 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset 0 461 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask 0x00000001 462 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift 18 463 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift) 464 465 /*define for cpv field*/ 466 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_offset 0 467 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_mask 0x00000001 468 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_shift 19 469 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_shift) 470 471 /*define for COUNT word*/ 472 /*define for count field*/ 473 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset 1 474 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask 0x003FFFFF 475 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift 0 476 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift) 477 478 /*define for addr_pair_num field*/ 479 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_offset 1 480 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_mask 0x000000FF 481 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_shift 24 482 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_ADDR_PAIR_NUM(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_shift) 483 484 /*define for PARAMETER word*/ 485 /*define for dst_mtype field*/ 486 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset 2 487 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask 0x00000007 488 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift 3 489 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_MTYPE(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift) 490 491 /*define for dst_l2_policy field*/ 492 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset 2 493 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask 0x00000003 494 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift 6 495 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_L2_POLICY(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift) 496 497 /*define for dst_llc field*/ 498 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_offset 2 499 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_mask 0x00000001 500 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_shift 8 501 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LLC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_shift) 502 503 /*define for src_mtype field*/ 504 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset 2 505 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask 0x00000007 506 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift 11 507 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_MTYPE(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift) 508 509 /*define for src_l2_policy field*/ 510 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset 2 511 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask 0x00000003 512 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift 14 513 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_L2_POLICY(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift) 514 515 /*define for src_llc field*/ 516 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_offset 2 517 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_mask 0x00000001 518 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_shift 16 519 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_LLC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_shift) 520 521 /*define for dst_sw field*/ 522 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset 2 523 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask 0x00000003 524 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift 17 525 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift) 526 527 /*define for dst_gcc field*/ 528 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset 2 529 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask 0x00000001 530 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift 19 531 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift) 532 533 /*define for dst_sys field*/ 534 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset 2 535 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask 0x00000001 536 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift 20 537 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift) 538 539 /*define for dst_log field*/ 540 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset 2 541 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask 0x00000001 542 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift 21 543 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift) 544 545 /*define for dst_snoop field*/ 546 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset 2 547 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask 0x00000001 548 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift 22 549 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift) 550 551 /*define for dst_gpa field*/ 552 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset 2 553 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask 0x00000001 554 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift 23 555 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift) 556 557 /*define for src_sw field*/ 558 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset 2 559 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask 0x00000003 560 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift 24 561 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift) 562 563 /*define for src_gcc field*/ 564 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset 2 565 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask 0x00000001 566 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift 27 567 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift) 568 569 /*define for src_sys field*/ 570 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset 2 571 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask 0x00000001 572 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift 28 573 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift) 574 575 /*define for src_snoop field*/ 576 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset 2 577 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask 0x00000001 578 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift 30 579 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift) 580 581 /*define for src_gpa field*/ 582 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset 2 583 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask 0x00000001 584 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift 31 585 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift) 586 587 /*define for SRC_ADDR_LO word*/ 588 /*define for src_addr_31_0 field*/ 589 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 590 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 591 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 592 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 593 594 /*define for SRC_ADDR_HI word*/ 595 /*define for src_addr_63_32 field*/ 596 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 597 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 598 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 599 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 600 601 /*define for DST_ADDR_LO word*/ 602 /*define for dst_addr_31_0 field*/ 603 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 604 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 605 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 606 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) 607 608 /*define for DST_ADDR_HI word*/ 609 /*define for dst_addr_63_32 field*/ 610 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 611 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 612 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 613 #define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) 614 615 616 /* 617 ** Definitions for SDMA_PKT_COPY_BROADCAST_LINEAR packet 618 */ 619 620 /*define for HEADER word*/ 621 /*define for op field*/ 622 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0 623 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask 0x000000FF 624 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift 0 625 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift) 626 627 /*define for sub_op field*/ 628 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0 629 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask 0x000000FF 630 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift 8 631 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift) 632 633 /*define for encrypt field*/ 634 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset 0 635 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask 0x00000001 636 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift 16 637 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift) 638 639 /*define for tmz field*/ 640 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset 0 641 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask 0x00000001 642 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift 18 643 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift) 644 645 /*define for cpv field*/ 646 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_offset 0 647 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_mask 0x00000001 648 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_shift 19 649 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_shift) 650 651 /*define for broadcast field*/ 652 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0 653 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask 0x00000001 654 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift 27 655 #define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift) 656 657 /*define for COUNT word*/ 658 /*define for count field*/ 659 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset 1 660 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask 0x3FFFFFFF 661 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift 0 662 #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift) 663 664 /*define for PARAMETER word*/ 665 /*define for dst2_sw field*/ 666 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset 2 667 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask 0x00000003 668 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift 8 669 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift) 670 671 /*define for dst2_cache_policy field*/ 672 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_offset 2 673 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_mask 0x00000007 674 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_shift 10 675 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_shift) 676 677 /*define for dst1_sw field*/ 678 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset 2 679 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask 0x00000003 680 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift 16 681 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift) 682 683 /*define for dst1_cache_policy field*/ 684 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_offset 2 685 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_mask 0x00000007 686 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_shift 18 687 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_shift) 688 689 /*define for src_sw field*/ 690 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset 2 691 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask 0x00000003 692 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift 24 693 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift) 694 695 /*define for src_cache_policy field*/ 696 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_offset 2 697 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_mask 0x00000007 698 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_shift 26 699 #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_shift) 700 701 /*define for SRC_ADDR_LO word*/ 702 /*define for src_addr_31_0 field*/ 703 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 704 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 705 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 706 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 707 708 /*define for SRC_ADDR_HI word*/ 709 /*define for src_addr_63_32 field*/ 710 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 711 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 712 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 713 #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 714 715 /*define for DST1_ADDR_LO word*/ 716 /*define for dst1_addr_31_0 field*/ 717 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset 5 718 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask 0xFFFFFFFF 719 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift 0 720 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift) 721 722 /*define for DST1_ADDR_HI word*/ 723 /*define for dst1_addr_63_32 field*/ 724 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset 6 725 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask 0xFFFFFFFF 726 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift 0 727 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift) 728 729 /*define for DST2_ADDR_LO word*/ 730 /*define for dst2_addr_31_0 field*/ 731 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset 7 732 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask 0xFFFFFFFF 733 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift 0 734 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift) 735 736 /*define for DST2_ADDR_HI word*/ 737 /*define for dst2_addr_63_32 field*/ 738 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset 8 739 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask 0xFFFFFFFF 740 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift 0 741 #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift) 742 743 744 /* 745 ** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN packet 746 */ 747 748 /*define for HEADER word*/ 749 /*define for op field*/ 750 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0 751 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask 0x000000FF 752 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift 0 753 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift) 754 755 /*define for sub_op field*/ 756 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0 757 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask 0x000000FF 758 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift 8 759 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift) 760 761 /*define for tmz field*/ 762 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset 0 763 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask 0x00000001 764 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift 18 765 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift) 766 767 /*define for cpv field*/ 768 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_offset 0 769 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_mask 0x00000001 770 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_shift 19 771 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_shift) 772 773 /*define for elementsize field*/ 774 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0 775 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask 0x00000007 776 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift 29 777 #define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift) 778 779 /*define for SRC_ADDR_LO word*/ 780 /*define for src_addr_31_0 field*/ 781 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset 1 782 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 783 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift 0 784 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift) 785 786 /*define for SRC_ADDR_HI word*/ 787 /*define for src_addr_63_32 field*/ 788 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset 2 789 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 790 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift 0 791 #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift) 792 793 /*define for DW_3 word*/ 794 /*define for src_x field*/ 795 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset 3 796 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask 0x00003FFF 797 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift 0 798 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift) 799 800 /*define for src_y field*/ 801 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset 3 802 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask 0x00003FFF 803 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift 16 804 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift) 805 806 /*define for DW_4 word*/ 807 /*define for src_z field*/ 808 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset 4 809 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask 0x00001FFF 810 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift 0 811 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift) 812 813 /*define for src_pitch field*/ 814 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset 4 815 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask 0x0007FFFF 816 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift 13 817 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift) 818 819 /*define for DW_5 word*/ 820 /*define for src_slice_pitch field*/ 821 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset 5 822 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask 0x0FFFFFFF 823 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift 0 824 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift) 825 826 /*define for DST_ADDR_LO word*/ 827 /*define for dst_addr_31_0 field*/ 828 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset 6 829 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 830 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift 0 831 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift) 832 833 /*define for DST_ADDR_HI word*/ 834 /*define for dst_addr_63_32 field*/ 835 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset 7 836 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 837 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift 0 838 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift) 839 840 /*define for DW_8 word*/ 841 /*define for dst_x field*/ 842 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset 8 843 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask 0x00003FFF 844 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift 0 845 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift) 846 847 /*define for dst_y field*/ 848 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset 8 849 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask 0x00003FFF 850 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift 16 851 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift) 852 853 /*define for DW_9 word*/ 854 /*define for dst_z field*/ 855 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset 9 856 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask 0x00001FFF 857 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift 0 858 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift) 859 860 /*define for dst_pitch field*/ 861 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset 9 862 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask 0x0007FFFF 863 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift 13 864 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift) 865 866 /*define for DW_10 word*/ 867 /*define for dst_slice_pitch field*/ 868 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset 10 869 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask 0x0FFFFFFF 870 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift 0 871 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift) 872 873 /*define for DW_11 word*/ 874 /*define for rect_x field*/ 875 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset 11 876 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask 0x00003FFF 877 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift 0 878 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift) 879 880 /*define for rect_y field*/ 881 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset 11 882 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask 0x00003FFF 883 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift 16 884 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift) 885 886 /*define for DW_12 word*/ 887 /*define for rect_z field*/ 888 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset 12 889 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask 0x00001FFF 890 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift 0 891 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift) 892 893 /*define for dst_sw field*/ 894 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset 12 895 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask 0x00000003 896 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift 16 897 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift) 898 899 /*define for dst_cache_policy field*/ 900 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_offset 12 901 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_mask 0x00000007 902 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_shift 18 903 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_shift) 904 905 /*define for src_sw field*/ 906 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset 12 907 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask 0x00000003 908 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift 24 909 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift) 910 911 /*define for src_cache_policy field*/ 912 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_offset 12 913 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_mask 0x00000007 914 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_shift 26 915 #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_shift) 916 917 918 /* 919 ** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE packet 920 */ 921 922 /*define for HEADER word*/ 923 /*define for op field*/ 924 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_offset 0 925 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_mask 0x000000FF 926 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_shift 0 927 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_shift) 928 929 /*define for sub_op field*/ 930 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_offset 0 931 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_mask 0x000000FF 932 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_shift 8 933 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_shift) 934 935 /*define for tmz field*/ 936 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_offset 0 937 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_mask 0x00000001 938 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_shift 18 939 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_shift) 940 941 /*define for cpv field*/ 942 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_offset 0 943 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_mask 0x00000001 944 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_shift 19 945 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_shift) 946 947 /*define for SRC_ADDR_LO word*/ 948 /*define for src_addr_31_0 field*/ 949 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_offset 1 950 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 951 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_shift 0 952 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_shift) 953 954 /*define for SRC_ADDR_HI word*/ 955 /*define for src_addr_63_32 field*/ 956 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_offset 2 957 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 958 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_shift 0 959 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_shift) 960 961 /*define for DW_3 word*/ 962 /*define for src_x field*/ 963 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_offset 3 964 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_mask 0xFFFFFFFF 965 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_shift 0 966 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_shift) 967 968 /*define for DW_4 word*/ 969 /*define for src_y field*/ 970 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_offset 4 971 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_mask 0xFFFFFFFF 972 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_shift 0 973 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_shift) 974 975 /*define for DW_5 word*/ 976 /*define for src_z field*/ 977 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_offset 5 978 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_mask 0xFFFFFFFF 979 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_shift 0 980 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_shift) 981 982 /*define for DW_6 word*/ 983 /*define for src_pitch field*/ 984 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_offset 6 985 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_mask 0xFFFFFFFF 986 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_shift 0 987 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_shift) 988 989 /*define for DW_7 word*/ 990 /*define for src_slice_pitch_31_0 field*/ 991 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_offset 7 992 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_mask 0xFFFFFFFF 993 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_shift 0 994 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_SRC_SLICE_PITCH_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_shift) 995 996 /*define for DW_8 word*/ 997 /*define for src_slice_pitch_47_32 field*/ 998 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_offset 8 999 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_mask 0x0000FFFF 1000 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_shift 0 1001 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_SRC_SLICE_PITCH_47_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_shift) 1002 1003 /*define for DST_ADDR_LO word*/ 1004 /*define for dst_addr_31_0 field*/ 1005 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_offset 9 1006 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 1007 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_shift 0 1008 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_shift) 1009 1010 /*define for DST_ADDR_HI word*/ 1011 /*define for dst_addr_63_32 field*/ 1012 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_offset 10 1013 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 1014 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_shift 0 1015 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_shift) 1016 1017 /*define for DW_11 word*/ 1018 /*define for dst_x field*/ 1019 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_offset 11 1020 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_mask 0xFFFFFFFF 1021 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_shift 0 1022 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_shift) 1023 1024 /*define for DW_12 word*/ 1025 /*define for dst_y field*/ 1026 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_offset 12 1027 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_mask 0xFFFFFFFF 1028 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_shift 0 1029 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_shift) 1030 1031 /*define for DW_13 word*/ 1032 /*define for dst_z field*/ 1033 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_offset 13 1034 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_mask 0xFFFFFFFF 1035 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_shift 0 1036 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_shift) 1037 1038 /*define for DW_14 word*/ 1039 /*define for dst_pitch field*/ 1040 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_offset 14 1041 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_mask 0xFFFFFFFF 1042 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_shift 0 1043 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_shift) 1044 1045 /*define for DW_15 word*/ 1046 /*define for dst_slice_pitch_31_0 field*/ 1047 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_offset 15 1048 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_mask 0xFFFFFFFF 1049 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_shift 0 1050 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_DST_SLICE_PITCH_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_shift) 1051 1052 /*define for DW_16 word*/ 1053 /*define for dst_slice_pitch_47_32 field*/ 1054 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_offset 16 1055 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_mask 0x0000FFFF 1056 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_shift 0 1057 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_SLICE_PITCH_47_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_shift) 1058 1059 /*define for dst_sw field*/ 1060 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_offset 16 1061 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_mask 0x00000003 1062 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_shift 16 1063 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_shift) 1064 1065 /*define for dst_policy field*/ 1066 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_offset 16 1067 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_mask 0x00000007 1068 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_shift 18 1069 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_shift) 1070 1071 /*define for src_sw field*/ 1072 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_offset 16 1073 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_mask 0x00000003 1074 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_shift 24 1075 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_shift) 1076 1077 /*define for src_policy field*/ 1078 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_offset 16 1079 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_mask 0x00000007 1080 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_shift 26 1081 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_SRC_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_shift) 1082 1083 /*define for DW_17 word*/ 1084 /*define for rect_x field*/ 1085 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_offset 17 1086 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_mask 0xFFFFFFFF 1087 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_shift 0 1088 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_shift) 1089 1090 /*define for DW_18 word*/ 1091 /*define for rect_y field*/ 1092 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_offset 18 1093 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_mask 0xFFFFFFFF 1094 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_shift 0 1095 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_shift) 1096 1097 /*define for DW_19 word*/ 1098 /*define for rect_z field*/ 1099 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_offset 19 1100 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_mask 0xFFFFFFFF 1101 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_shift 0 1102 #define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_shift) 1103 1104 1105 /* 1106 ** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN_BC packet 1107 */ 1108 1109 /*define for HEADER word*/ 1110 /*define for op field*/ 1111 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset 0 1112 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask 0x000000FF 1113 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift 0 1114 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift) 1115 1116 /*define for sub_op field*/ 1117 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset 0 1118 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask 0x000000FF 1119 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift 8 1120 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift) 1121 1122 /*define for elementsize field*/ 1123 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset 0 1124 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask 0x00000007 1125 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift 29 1126 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift) 1127 1128 /*define for SRC_ADDR_LO word*/ 1129 /*define for src_addr_31_0 field*/ 1130 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset 1 1131 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 1132 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift 0 1133 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift) 1134 1135 /*define for SRC_ADDR_HI word*/ 1136 /*define for src_addr_63_32 field*/ 1137 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset 2 1138 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 1139 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift 0 1140 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift) 1141 1142 /*define for DW_3 word*/ 1143 /*define for src_x field*/ 1144 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset 3 1145 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask 0x00003FFF 1146 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift 0 1147 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift) 1148 1149 /*define for src_y field*/ 1150 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset 3 1151 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask 0x00003FFF 1152 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift 16 1153 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift) 1154 1155 /*define for DW_4 word*/ 1156 /*define for src_z field*/ 1157 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset 4 1158 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask 0x000007FF 1159 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift 0 1160 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift) 1161 1162 /*define for src_pitch field*/ 1163 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset 4 1164 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask 0x00003FFF 1165 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift 13 1166 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift) 1167 1168 /*define for DW_5 word*/ 1169 /*define for src_slice_pitch field*/ 1170 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset 5 1171 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask 0x0FFFFFFF 1172 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift 0 1173 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift) 1174 1175 /*define for DST_ADDR_LO word*/ 1176 /*define for dst_addr_31_0 field*/ 1177 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset 6 1178 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 1179 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 1180 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift) 1181 1182 /*define for DST_ADDR_HI word*/ 1183 /*define for dst_addr_63_32 field*/ 1184 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset 7 1185 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 1186 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 1187 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift) 1188 1189 /*define for DW_8 word*/ 1190 /*define for dst_x field*/ 1191 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset 8 1192 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask 0x00003FFF 1193 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift 0 1194 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift) 1195 1196 /*define for dst_y field*/ 1197 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset 8 1198 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask 0x00003FFF 1199 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift 16 1200 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift) 1201 1202 /*define for DW_9 word*/ 1203 /*define for dst_z field*/ 1204 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset 9 1205 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask 0x000007FF 1206 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift 0 1207 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift) 1208 1209 /*define for dst_pitch field*/ 1210 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset 9 1211 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask 0x00003FFF 1212 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift 13 1213 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift) 1214 1215 /*define for DW_10 word*/ 1216 /*define for dst_slice_pitch field*/ 1217 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset 10 1218 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask 0x0FFFFFFF 1219 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift 0 1220 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift) 1221 1222 /*define for DW_11 word*/ 1223 /*define for rect_x field*/ 1224 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset 11 1225 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask 0x00003FFF 1226 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift 0 1227 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift) 1228 1229 /*define for rect_y field*/ 1230 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset 11 1231 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask 0x00003FFF 1232 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift 16 1233 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift) 1234 1235 /*define for DW_12 word*/ 1236 /*define for rect_z field*/ 1237 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset 12 1238 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask 0x000007FF 1239 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift 0 1240 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift) 1241 1242 /*define for dst_sw field*/ 1243 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset 12 1244 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask 0x00000003 1245 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift 16 1246 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift) 1247 1248 /*define for dst_ha field*/ 1249 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset 12 1250 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask 0x00000001 1251 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift 19 1252 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift) 1253 1254 /*define for src_sw field*/ 1255 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset 12 1256 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask 0x00000003 1257 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift 24 1258 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift) 1259 1260 /*define for src_ha field*/ 1261 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset 12 1262 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask 0x00000001 1263 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift 27 1264 #define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift) 1265 1266 1267 /* 1268 ** Definitions for SDMA_PKT_COPY_TILED packet 1269 */ 1270 1271 /*define for HEADER word*/ 1272 /*define for op field*/ 1273 #define SDMA_PKT_COPY_TILED_HEADER_op_offset 0 1274 #define SDMA_PKT_COPY_TILED_HEADER_op_mask 0x000000FF 1275 #define SDMA_PKT_COPY_TILED_HEADER_op_shift 0 1276 #define SDMA_PKT_COPY_TILED_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift) 1277 1278 /*define for sub_op field*/ 1279 #define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 0 1280 #define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask 0x000000FF 1281 #define SDMA_PKT_COPY_TILED_HEADER_sub_op_shift 8 1282 #define SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift) 1283 1284 /*define for encrypt field*/ 1285 #define SDMA_PKT_COPY_TILED_HEADER_encrypt_offset 0 1286 #define SDMA_PKT_COPY_TILED_HEADER_encrypt_mask 0x00000001 1287 #define SDMA_PKT_COPY_TILED_HEADER_encrypt_shift 16 1288 #define SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_encrypt_mask) << SDMA_PKT_COPY_TILED_HEADER_encrypt_shift) 1289 1290 /*define for tmz field*/ 1291 #define SDMA_PKT_COPY_TILED_HEADER_tmz_offset 0 1292 #define SDMA_PKT_COPY_TILED_HEADER_tmz_mask 0x00000001 1293 #define SDMA_PKT_COPY_TILED_HEADER_tmz_shift 18 1294 #define SDMA_PKT_COPY_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_HEADER_tmz_shift) 1295 1296 /*define for cpv field*/ 1297 #define SDMA_PKT_COPY_TILED_HEADER_cpv_offset 0 1298 #define SDMA_PKT_COPY_TILED_HEADER_cpv_mask 0x00000001 1299 #define SDMA_PKT_COPY_TILED_HEADER_cpv_shift 19 1300 #define SDMA_PKT_COPY_TILED_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_cpv_mask) << SDMA_PKT_COPY_TILED_HEADER_cpv_shift) 1301 1302 /*define for detile field*/ 1303 #define SDMA_PKT_COPY_TILED_HEADER_detile_offset 0 1304 #define SDMA_PKT_COPY_TILED_HEADER_detile_mask 0x00000001 1305 #define SDMA_PKT_COPY_TILED_HEADER_detile_shift 31 1306 #define SDMA_PKT_COPY_TILED_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift) 1307 1308 /*define for TILED_ADDR_LO word*/ 1309 /*define for tiled_addr_31_0 field*/ 1310 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset 1 1311 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 1312 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift 0 1313 #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift) 1314 1315 /*define for TILED_ADDR_HI word*/ 1316 /*define for tiled_addr_63_32 field*/ 1317 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset 2 1318 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 1319 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift 0 1320 #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift) 1321 1322 /*define for DW_3 word*/ 1323 /*define for width field*/ 1324 #define SDMA_PKT_COPY_TILED_DW_3_width_offset 3 1325 #define SDMA_PKT_COPY_TILED_DW_3_width_mask 0x00003FFF 1326 #define SDMA_PKT_COPY_TILED_DW_3_width_shift 0 1327 #define SDMA_PKT_COPY_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_width_mask) << SDMA_PKT_COPY_TILED_DW_3_width_shift) 1328 1329 /*define for DW_4 word*/ 1330 /*define for height field*/ 1331 #define SDMA_PKT_COPY_TILED_DW_4_height_offset 4 1332 #define SDMA_PKT_COPY_TILED_DW_4_height_mask 0x00003FFF 1333 #define SDMA_PKT_COPY_TILED_DW_4_height_shift 0 1334 #define SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_height_mask) << SDMA_PKT_COPY_TILED_DW_4_height_shift) 1335 1336 /*define for depth field*/ 1337 #define SDMA_PKT_COPY_TILED_DW_4_depth_offset 4 1338 #define SDMA_PKT_COPY_TILED_DW_4_depth_mask 0x00001FFF 1339 #define SDMA_PKT_COPY_TILED_DW_4_depth_shift 16 1340 #define SDMA_PKT_COPY_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_DW_4_depth_shift) 1341 1342 /*define for DW_5 word*/ 1343 /*define for element_size field*/ 1344 #define SDMA_PKT_COPY_TILED_DW_5_element_size_offset 5 1345 #define SDMA_PKT_COPY_TILED_DW_5_element_size_mask 0x00000007 1346 #define SDMA_PKT_COPY_TILED_DW_5_element_size_shift 0 1347 #define SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift) 1348 1349 /*define for swizzle_mode field*/ 1350 #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset 5 1351 #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask 0x0000001F 1352 #define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift 3 1353 #define SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift) 1354 1355 /*define for dimension field*/ 1356 #define SDMA_PKT_COPY_TILED_DW_5_dimension_offset 5 1357 #define SDMA_PKT_COPY_TILED_DW_5_dimension_mask 0x00000003 1358 #define SDMA_PKT_COPY_TILED_DW_5_dimension_shift 9 1359 #define SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_dimension_mask) << SDMA_PKT_COPY_TILED_DW_5_dimension_shift) 1360 1361 /*define for mip_max field*/ 1362 #define SDMA_PKT_COPY_TILED_DW_5_mip_max_offset 5 1363 #define SDMA_PKT_COPY_TILED_DW_5_mip_max_mask 0x0000000F 1364 #define SDMA_PKT_COPY_TILED_DW_5_mip_max_shift 16 1365 #define SDMA_PKT_COPY_TILED_DW_5_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_mip_max_mask) << SDMA_PKT_COPY_TILED_DW_5_mip_max_shift) 1366 1367 /*define for DW_6 word*/ 1368 /*define for x field*/ 1369 #define SDMA_PKT_COPY_TILED_DW_6_x_offset 6 1370 #define SDMA_PKT_COPY_TILED_DW_6_x_mask 0x00003FFF 1371 #define SDMA_PKT_COPY_TILED_DW_6_x_shift 0 1372 #define SDMA_PKT_COPY_TILED_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift) 1373 1374 /*define for y field*/ 1375 #define SDMA_PKT_COPY_TILED_DW_6_y_offset 6 1376 #define SDMA_PKT_COPY_TILED_DW_6_y_mask 0x00003FFF 1377 #define SDMA_PKT_COPY_TILED_DW_6_y_shift 16 1378 #define SDMA_PKT_COPY_TILED_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift) 1379 1380 /*define for DW_7 word*/ 1381 /*define for z field*/ 1382 #define SDMA_PKT_COPY_TILED_DW_7_z_offset 7 1383 #define SDMA_PKT_COPY_TILED_DW_7_z_mask 0x00001FFF 1384 #define SDMA_PKT_COPY_TILED_DW_7_z_shift 0 1385 #define SDMA_PKT_COPY_TILED_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift) 1386 1387 /*define for linear_sw field*/ 1388 #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset 7 1389 #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask 0x00000003 1390 #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift 16 1391 #define SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift) 1392 1393 /*define for linear_cache_policy field*/ 1394 #define SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_offset 7 1395 #define SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_mask 0x00000007 1396 #define SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_shift 18 1397 #define SDMA_PKT_COPY_TILED_DW_7_LINEAR_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_shift) 1398 1399 /*define for tile_sw field*/ 1400 #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset 7 1401 #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask 0x00000003 1402 #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift 24 1403 #define SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift) 1404 1405 /*define for tile_cache_policy field*/ 1406 #define SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_offset 7 1407 #define SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_mask 0x00000007 1408 #define SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_shift 26 1409 #define SDMA_PKT_COPY_TILED_DW_7_TILE_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_shift) 1410 1411 /*define for LINEAR_ADDR_LO word*/ 1412 /*define for linear_addr_31_0 field*/ 1413 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 1414 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 1415 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 1416 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift) 1417 1418 /*define for LINEAR_ADDR_HI word*/ 1419 /*define for linear_addr_63_32 field*/ 1420 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 1421 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 1422 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 1423 #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift) 1424 1425 /*define for LINEAR_PITCH word*/ 1426 /*define for linear_pitch field*/ 1427 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset 10 1428 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF 1429 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift 0 1430 #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift) 1431 1432 /*define for LINEAR_SLICE_PITCH word*/ 1433 /*define for linear_slice_pitch field*/ 1434 #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 11 1435 #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF 1436 #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 1437 #define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) 1438 1439 /*define for COUNT word*/ 1440 /*define for count field*/ 1441 #define SDMA_PKT_COPY_TILED_COUNT_count_offset 12 1442 #define SDMA_PKT_COPY_TILED_COUNT_count_mask 0x3FFFFFFF 1443 #define SDMA_PKT_COPY_TILED_COUNT_count_shift 0 1444 #define SDMA_PKT_COPY_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift) 1445 1446 1447 /* 1448 ** Definitions for SDMA_PKT_COPY_TILED_BC packet 1449 */ 1450 1451 /*define for HEADER word*/ 1452 /*define for op field*/ 1453 #define SDMA_PKT_COPY_TILED_BC_HEADER_op_offset 0 1454 #define SDMA_PKT_COPY_TILED_BC_HEADER_op_mask 0x000000FF 1455 #define SDMA_PKT_COPY_TILED_BC_HEADER_op_shift 0 1456 #define SDMA_PKT_COPY_TILED_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_op_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_op_shift) 1457 1458 /*define for sub_op field*/ 1459 #define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset 0 1460 #define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask 0x000000FF 1461 #define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift 8 1462 #define SDMA_PKT_COPY_TILED_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift) 1463 1464 /*define for detile field*/ 1465 #define SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset 0 1466 #define SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask 0x00000001 1467 #define SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift 31 1468 #define SDMA_PKT_COPY_TILED_BC_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift) 1469 1470 /*define for TILED_ADDR_LO word*/ 1471 /*define for tiled_addr_31_0 field*/ 1472 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset 1 1473 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 1474 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift 0 1475 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift) 1476 1477 /*define for TILED_ADDR_HI word*/ 1478 /*define for tiled_addr_63_32 field*/ 1479 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset 2 1480 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 1481 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift 0 1482 #define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift) 1483 1484 /*define for DW_3 word*/ 1485 /*define for width field*/ 1486 #define SDMA_PKT_COPY_TILED_BC_DW_3_width_offset 3 1487 #define SDMA_PKT_COPY_TILED_BC_DW_3_width_mask 0x00003FFF 1488 #define SDMA_PKT_COPY_TILED_BC_DW_3_width_shift 0 1489 #define SDMA_PKT_COPY_TILED_BC_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_3_width_mask) << SDMA_PKT_COPY_TILED_BC_DW_3_width_shift) 1490 1491 /*define for DW_4 word*/ 1492 /*define for height field*/ 1493 #define SDMA_PKT_COPY_TILED_BC_DW_4_height_offset 4 1494 #define SDMA_PKT_COPY_TILED_BC_DW_4_height_mask 0x00003FFF 1495 #define SDMA_PKT_COPY_TILED_BC_DW_4_height_shift 0 1496 #define SDMA_PKT_COPY_TILED_BC_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_4_height_mask) << SDMA_PKT_COPY_TILED_BC_DW_4_height_shift) 1497 1498 /*define for depth field*/ 1499 #define SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset 4 1500 #define SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask 0x000007FF 1501 #define SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift 16 1502 #define SDMA_PKT_COPY_TILED_BC_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift) 1503 1504 /*define for DW_5 word*/ 1505 /*define for element_size field*/ 1506 #define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset 5 1507 #define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask 0x00000007 1508 #define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift 0 1509 #define SDMA_PKT_COPY_TILED_BC_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift) 1510 1511 /*define for array_mode field*/ 1512 #define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset 5 1513 #define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask 0x0000000F 1514 #define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift 3 1515 #define SDMA_PKT_COPY_TILED_BC_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift) 1516 1517 /*define for mit_mode field*/ 1518 #define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset 5 1519 #define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask 0x00000007 1520 #define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift 8 1521 #define SDMA_PKT_COPY_TILED_BC_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift) 1522 1523 /*define for tilesplit_size field*/ 1524 #define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset 5 1525 #define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask 0x00000007 1526 #define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift 11 1527 #define SDMA_PKT_COPY_TILED_BC_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift) 1528 1529 /*define for bank_w field*/ 1530 #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset 5 1531 #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask 0x00000003 1532 #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift 15 1533 #define SDMA_PKT_COPY_TILED_BC_DW_5_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift) 1534 1535 /*define for bank_h field*/ 1536 #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset 5 1537 #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask 0x00000003 1538 #define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift 18 1539 #define SDMA_PKT_COPY_TILED_BC_DW_5_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift) 1540 1541 /*define for num_bank field*/ 1542 #define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset 5 1543 #define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask 0x00000003 1544 #define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift 21 1545 #define SDMA_PKT_COPY_TILED_BC_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift) 1546 1547 /*define for mat_aspt field*/ 1548 #define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset 5 1549 #define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask 0x00000003 1550 #define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift 24 1551 #define SDMA_PKT_COPY_TILED_BC_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift) 1552 1553 /*define for pipe_config field*/ 1554 #define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset 5 1555 #define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask 0x0000001F 1556 #define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift 26 1557 #define SDMA_PKT_COPY_TILED_BC_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift) 1558 1559 /*define for DW_6 word*/ 1560 /*define for x field*/ 1561 #define SDMA_PKT_COPY_TILED_BC_DW_6_x_offset 6 1562 #define SDMA_PKT_COPY_TILED_BC_DW_6_x_mask 0x00003FFF 1563 #define SDMA_PKT_COPY_TILED_BC_DW_6_x_shift 0 1564 #define SDMA_PKT_COPY_TILED_BC_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_6_x_mask) << SDMA_PKT_COPY_TILED_BC_DW_6_x_shift) 1565 1566 /*define for y field*/ 1567 #define SDMA_PKT_COPY_TILED_BC_DW_6_y_offset 6 1568 #define SDMA_PKT_COPY_TILED_BC_DW_6_y_mask 0x00003FFF 1569 #define SDMA_PKT_COPY_TILED_BC_DW_6_y_shift 16 1570 #define SDMA_PKT_COPY_TILED_BC_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_6_y_mask) << SDMA_PKT_COPY_TILED_BC_DW_6_y_shift) 1571 1572 /*define for DW_7 word*/ 1573 /*define for z field*/ 1574 #define SDMA_PKT_COPY_TILED_BC_DW_7_z_offset 7 1575 #define SDMA_PKT_COPY_TILED_BC_DW_7_z_mask 0x000007FF 1576 #define SDMA_PKT_COPY_TILED_BC_DW_7_z_shift 0 1577 #define SDMA_PKT_COPY_TILED_BC_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_z_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_z_shift) 1578 1579 /*define for linear_sw field*/ 1580 #define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset 7 1581 #define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask 0x00000003 1582 #define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift 16 1583 #define SDMA_PKT_COPY_TILED_BC_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift) 1584 1585 /*define for tile_sw field*/ 1586 #define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset 7 1587 #define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask 0x00000003 1588 #define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift 24 1589 #define SDMA_PKT_COPY_TILED_BC_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift) 1590 1591 /*define for LINEAR_ADDR_LO word*/ 1592 /*define for linear_addr_31_0 field*/ 1593 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 1594 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 1595 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 1596 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift) 1597 1598 /*define for LINEAR_ADDR_HI word*/ 1599 /*define for linear_addr_63_32 field*/ 1600 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 1601 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 1602 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 1603 #define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift) 1604 1605 /*define for LINEAR_PITCH word*/ 1606 /*define for linear_pitch field*/ 1607 #define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset 10 1608 #define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF 1609 #define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift 0 1610 #define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift) 1611 1612 /*define for LINEAR_SLICE_PITCH word*/ 1613 /*define for linear_slice_pitch field*/ 1614 #define SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 11 1615 #define SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF 1616 #define SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 1617 #define SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) 1618 1619 /*define for COUNT word*/ 1620 /*define for count field*/ 1621 #define SDMA_PKT_COPY_TILED_BC_COUNT_count_offset 12 1622 #define SDMA_PKT_COPY_TILED_BC_COUNT_count_mask 0x000FFFFF 1623 #define SDMA_PKT_COPY_TILED_BC_COUNT_count_shift 2 1624 #define SDMA_PKT_COPY_TILED_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_BC_COUNT_count_mask) << SDMA_PKT_COPY_TILED_BC_COUNT_count_shift) 1625 1626 1627 /* 1628 ** Definitions for SDMA_PKT_COPY_L2T_BROADCAST packet 1629 */ 1630 1631 /*define for HEADER word*/ 1632 /*define for op field*/ 1633 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 0 1634 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask 0x000000FF 1635 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift 0 1636 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift) 1637 1638 /*define for sub_op field*/ 1639 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 0 1640 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask 0x000000FF 1641 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift 8 1642 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift) 1643 1644 /*define for encrypt field*/ 1645 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset 0 1646 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask 0x00000001 1647 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift 16 1648 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift) 1649 1650 /*define for tmz field*/ 1651 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset 0 1652 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask 0x00000001 1653 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift 18 1654 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift) 1655 1656 /*define for cpv field*/ 1657 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_offset 0 1658 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_mask 0x00000001 1659 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_shift 19 1660 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_shift) 1661 1662 /*define for videocopy field*/ 1663 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 0 1664 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask 0x00000001 1665 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift 26 1666 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift) 1667 1668 /*define for broadcast field*/ 1669 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 0 1670 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask 0x00000001 1671 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift 27 1672 #define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift) 1673 1674 /*define for TILED_ADDR_LO_0 word*/ 1675 /*define for tiled_addr0_31_0 field*/ 1676 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset 1 1677 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask 0xFFFFFFFF 1678 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift 0 1679 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift) 1680 1681 /*define for TILED_ADDR_HI_0 word*/ 1682 /*define for tiled_addr0_63_32 field*/ 1683 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset 2 1684 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask 0xFFFFFFFF 1685 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift 0 1686 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift) 1687 1688 /*define for TILED_ADDR_LO_1 word*/ 1689 /*define for tiled_addr1_31_0 field*/ 1690 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset 3 1691 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask 0xFFFFFFFF 1692 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift 0 1693 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift) 1694 1695 /*define for TILED_ADDR_HI_1 word*/ 1696 /*define for tiled_addr1_63_32 field*/ 1697 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset 4 1698 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask 0xFFFFFFFF 1699 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift 0 1700 #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift) 1701 1702 /*define for DW_5 word*/ 1703 /*define for width field*/ 1704 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset 5 1705 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask 0x00003FFF 1706 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift 0 1707 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift) 1708 1709 /*define for DW_6 word*/ 1710 /*define for height field*/ 1711 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset 6 1712 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask 0x00003FFF 1713 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift 0 1714 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift) 1715 1716 /*define for depth field*/ 1717 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset 6 1718 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask 0x00001FFF 1719 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift 16 1720 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift) 1721 1722 /*define for DW_7 word*/ 1723 /*define for element_size field*/ 1724 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset 7 1725 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask 0x00000007 1726 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift 0 1727 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift) 1728 1729 /*define for swizzle_mode field*/ 1730 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset 7 1731 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask 0x0000001F 1732 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift 3 1733 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift) 1734 1735 /*define for dimension field*/ 1736 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset 7 1737 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask 0x00000003 1738 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift 9 1739 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift) 1740 1741 /*define for mip_max field*/ 1742 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset 7 1743 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask 0x0000000F 1744 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift 16 1745 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIP_MAX(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift) 1746 1747 /*define for DW_8 word*/ 1748 /*define for x field*/ 1749 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset 8 1750 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask 0x00003FFF 1751 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift 0 1752 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift) 1753 1754 /*define for y field*/ 1755 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset 8 1756 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask 0x00003FFF 1757 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift 16 1758 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift) 1759 1760 /*define for DW_9 word*/ 1761 /*define for z field*/ 1762 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset 9 1763 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask 0x00001FFF 1764 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift 0 1765 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift) 1766 1767 /*define for DW_10 word*/ 1768 /*define for dst2_sw field*/ 1769 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset 10 1770 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask 0x00000003 1771 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift 8 1772 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift) 1773 1774 /*define for dst2_cache_policy field*/ 1775 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_offset 10 1776 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_mask 0x00000007 1777 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_shift 10 1778 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_shift) 1779 1780 /*define for linear_sw field*/ 1781 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset 10 1782 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask 0x00000003 1783 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift 16 1784 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift) 1785 1786 /*define for linear_cache_policy field*/ 1787 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_offset 10 1788 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_mask 0x00000007 1789 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_shift 18 1790 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_shift) 1791 1792 /*define for tile_sw field*/ 1793 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset 10 1794 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask 0x00000003 1795 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift 24 1796 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift) 1797 1798 /*define for tile_cache_policy field*/ 1799 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_offset 10 1800 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_mask 0x00000007 1801 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_shift 26 1802 #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_shift) 1803 1804 /*define for LINEAR_ADDR_LO word*/ 1805 /*define for linear_addr_31_0 field*/ 1806 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset 11 1807 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 1808 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 1809 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift) 1810 1811 /*define for LINEAR_ADDR_HI word*/ 1812 /*define for linear_addr_63_32 field*/ 1813 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset 12 1814 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 1815 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 1816 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift) 1817 1818 /*define for LINEAR_PITCH word*/ 1819 /*define for linear_pitch field*/ 1820 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset 13 1821 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF 1822 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift 0 1823 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift) 1824 1825 /*define for LINEAR_SLICE_PITCH word*/ 1826 /*define for linear_slice_pitch field*/ 1827 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 14 1828 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF 1829 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 1830 #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) 1831 1832 /*define for COUNT word*/ 1833 /*define for count field*/ 1834 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset 15 1835 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask 0x3FFFFFFF 1836 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift 0 1837 #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift) 1838 1839 1840 /* 1841 ** Definitions for SDMA_PKT_COPY_T2T packet 1842 */ 1843 1844 /*define for HEADER word*/ 1845 /*define for op field*/ 1846 #define SDMA_PKT_COPY_T2T_HEADER_op_offset 0 1847 #define SDMA_PKT_COPY_T2T_HEADER_op_mask 0x000000FF 1848 #define SDMA_PKT_COPY_T2T_HEADER_op_shift 0 1849 #define SDMA_PKT_COPY_T2T_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift) 1850 1851 /*define for sub_op field*/ 1852 #define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 0 1853 #define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask 0x000000FF 1854 #define SDMA_PKT_COPY_T2T_HEADER_sub_op_shift 8 1855 #define SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift) 1856 1857 /*define for tmz field*/ 1858 #define SDMA_PKT_COPY_T2T_HEADER_tmz_offset 0 1859 #define SDMA_PKT_COPY_T2T_HEADER_tmz_mask 0x00000001 1860 #define SDMA_PKT_COPY_T2T_HEADER_tmz_shift 18 1861 #define SDMA_PKT_COPY_T2T_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_tmz_mask) << SDMA_PKT_COPY_T2T_HEADER_tmz_shift) 1862 1863 /*define for dcc field*/ 1864 #define SDMA_PKT_COPY_T2T_HEADER_dcc_offset 0 1865 #define SDMA_PKT_COPY_T2T_HEADER_dcc_mask 0x00000001 1866 #define SDMA_PKT_COPY_T2T_HEADER_dcc_shift 19 1867 #define SDMA_PKT_COPY_T2T_HEADER_DCC(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_dcc_mask) << SDMA_PKT_COPY_T2T_HEADER_dcc_shift) 1868 1869 /*define for cpv field*/ 1870 #define SDMA_PKT_COPY_T2T_HEADER_cpv_offset 0 1871 #define SDMA_PKT_COPY_T2T_HEADER_cpv_mask 0x00000001 1872 #define SDMA_PKT_COPY_T2T_HEADER_cpv_shift 28 1873 #define SDMA_PKT_COPY_T2T_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_cpv_mask) << SDMA_PKT_COPY_T2T_HEADER_cpv_shift) 1874 1875 /*define for dcc_dir field*/ 1876 #define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset 0 1877 #define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask 0x00000001 1878 #define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift 31 1879 #define SDMA_PKT_COPY_T2T_HEADER_DCC_DIR(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask) << SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift) 1880 1881 /*define for SRC_ADDR_LO word*/ 1882 /*define for src_addr_31_0 field*/ 1883 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset 1 1884 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 1885 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift 0 1886 #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift) 1887 1888 /*define for SRC_ADDR_HI word*/ 1889 /*define for src_addr_63_32 field*/ 1890 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset 2 1891 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 1892 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift 0 1893 #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift) 1894 1895 /*define for DW_3 word*/ 1896 /*define for src_x field*/ 1897 #define SDMA_PKT_COPY_T2T_DW_3_src_x_offset 3 1898 #define SDMA_PKT_COPY_T2T_DW_3_src_x_mask 0x00003FFF 1899 #define SDMA_PKT_COPY_T2T_DW_3_src_x_shift 0 1900 #define SDMA_PKT_COPY_T2T_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift) 1901 1902 /*define for src_y field*/ 1903 #define SDMA_PKT_COPY_T2T_DW_3_src_y_offset 3 1904 #define SDMA_PKT_COPY_T2T_DW_3_src_y_mask 0x00003FFF 1905 #define SDMA_PKT_COPY_T2T_DW_3_src_y_shift 16 1906 #define SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift) 1907 1908 /*define for DW_4 word*/ 1909 /*define for src_z field*/ 1910 #define SDMA_PKT_COPY_T2T_DW_4_src_z_offset 4 1911 #define SDMA_PKT_COPY_T2T_DW_4_src_z_mask 0x00001FFF 1912 #define SDMA_PKT_COPY_T2T_DW_4_src_z_shift 0 1913 #define SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift) 1914 1915 /*define for src_width field*/ 1916 #define SDMA_PKT_COPY_T2T_DW_4_src_width_offset 4 1917 #define SDMA_PKT_COPY_T2T_DW_4_src_width_mask 0x00003FFF 1918 #define SDMA_PKT_COPY_T2T_DW_4_src_width_shift 16 1919 #define SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_DW_4_src_width_shift) 1920 1921 /*define for DW_5 word*/ 1922 /*define for src_height field*/ 1923 #define SDMA_PKT_COPY_T2T_DW_5_src_height_offset 5 1924 #define SDMA_PKT_COPY_T2T_DW_5_src_height_mask 0x00003FFF 1925 #define SDMA_PKT_COPY_T2T_DW_5_src_height_shift 0 1926 #define SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_DW_5_src_height_shift) 1927 1928 /*define for src_depth field*/ 1929 #define SDMA_PKT_COPY_T2T_DW_5_src_depth_offset 5 1930 #define SDMA_PKT_COPY_T2T_DW_5_src_depth_mask 0x00001FFF 1931 #define SDMA_PKT_COPY_T2T_DW_5_src_depth_shift 16 1932 #define SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_DW_5_src_depth_shift) 1933 1934 /*define for DW_6 word*/ 1935 /*define for src_element_size field*/ 1936 #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset 6 1937 #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask 0x00000007 1938 #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift 0 1939 #define SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift) 1940 1941 /*define for src_swizzle_mode field*/ 1942 #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset 6 1943 #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask 0x0000001F 1944 #define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift 3 1945 #define SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift) 1946 1947 /*define for src_dimension field*/ 1948 #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset 6 1949 #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask 0x00000003 1950 #define SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift 9 1951 #define SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask) << SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift) 1952 1953 /*define for src_mip_max field*/ 1954 #define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset 6 1955 #define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask 0x0000000F 1956 #define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift 16 1957 #define SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift) 1958 1959 /*define for src_mip_id field*/ 1960 #define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset 6 1961 #define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask 0x0000000F 1962 #define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift 20 1963 #define SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_ID(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift) 1964 1965 /*define for DST_ADDR_LO word*/ 1966 /*define for dst_addr_31_0 field*/ 1967 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset 7 1968 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 1969 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift 0 1970 #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift) 1971 1972 /*define for DST_ADDR_HI word*/ 1973 /*define for dst_addr_63_32 field*/ 1974 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset 8 1975 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 1976 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift 0 1977 #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift) 1978 1979 /*define for DW_9 word*/ 1980 /*define for dst_x field*/ 1981 #define SDMA_PKT_COPY_T2T_DW_9_dst_x_offset 9 1982 #define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask 0x00003FFF 1983 #define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift 0 1984 #define SDMA_PKT_COPY_T2T_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift) 1985 1986 /*define for dst_y field*/ 1987 #define SDMA_PKT_COPY_T2T_DW_9_dst_y_offset 9 1988 #define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask 0x00003FFF 1989 #define SDMA_PKT_COPY_T2T_DW_9_dst_y_shift 16 1990 #define SDMA_PKT_COPY_T2T_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift) 1991 1992 /*define for DW_10 word*/ 1993 /*define for dst_z field*/ 1994 #define SDMA_PKT_COPY_T2T_DW_10_dst_z_offset 10 1995 #define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask 0x00001FFF 1996 #define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift 0 1997 #define SDMA_PKT_COPY_T2T_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift) 1998 1999 /*define for dst_width field*/ 2000 #define SDMA_PKT_COPY_T2T_DW_10_dst_width_offset 10 2001 #define SDMA_PKT_COPY_T2T_DW_10_dst_width_mask 0x00003FFF 2002 #define SDMA_PKT_COPY_T2T_DW_10_dst_width_shift 16 2003 #define SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_width_shift) 2004 2005 /*define for DW_11 word*/ 2006 /*define for dst_height field*/ 2007 #define SDMA_PKT_COPY_T2T_DW_11_dst_height_offset 11 2008 #define SDMA_PKT_COPY_T2T_DW_11_dst_height_mask 0x00003FFF 2009 #define SDMA_PKT_COPY_T2T_DW_11_dst_height_shift 0 2010 #define SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_height_shift) 2011 2012 /*define for dst_depth field*/ 2013 #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset 11 2014 #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask 0x00001FFF 2015 #define SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift 16 2016 #define SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift) 2017 2018 /*define for DW_12 word*/ 2019 /*define for dst_element_size field*/ 2020 #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset 12 2021 #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask 0x00000007 2022 #define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift 0 2023 #define SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift) 2024 2025 /*define for dst_swizzle_mode field*/ 2026 #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset 12 2027 #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask 0x0000001F 2028 #define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift 3 2029 #define SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift) 2030 2031 /*define for dst_dimension field*/ 2032 #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset 12 2033 #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask 0x00000003 2034 #define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift 9 2035 #define SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift) 2036 2037 /*define for dst_mip_max field*/ 2038 #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset 12 2039 #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask 0x0000000F 2040 #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift 16 2041 #define SDMA_PKT_COPY_T2T_DW_12_DST_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift) 2042 2043 /*define for dst_mip_id field*/ 2044 #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset 12 2045 #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask 0x0000000F 2046 #define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift 20 2047 #define SDMA_PKT_COPY_T2T_DW_12_DST_MIP_ID(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift) 2048 2049 /*define for DW_13 word*/ 2050 /*define for rect_x field*/ 2051 #define SDMA_PKT_COPY_T2T_DW_13_rect_x_offset 13 2052 #define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask 0x00003FFF 2053 #define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift 0 2054 #define SDMA_PKT_COPY_T2T_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift) 2055 2056 /*define for rect_y field*/ 2057 #define SDMA_PKT_COPY_T2T_DW_13_rect_y_offset 13 2058 #define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask 0x00003FFF 2059 #define SDMA_PKT_COPY_T2T_DW_13_rect_y_shift 16 2060 #define SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift) 2061 2062 /*define for DW_14 word*/ 2063 /*define for rect_z field*/ 2064 #define SDMA_PKT_COPY_T2T_DW_14_rect_z_offset 14 2065 #define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask 0x00001FFF 2066 #define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift 0 2067 #define SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift) 2068 2069 /*define for dst_sw field*/ 2070 #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset 14 2071 #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask 0x00000003 2072 #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift 16 2073 #define SDMA_PKT_COPY_T2T_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift) 2074 2075 /*define for dst_cache_policy field*/ 2076 #define SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_offset 14 2077 #define SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_mask 0x00000007 2078 #define SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_shift 18 2079 #define SDMA_PKT_COPY_T2T_DW_14_DST_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_shift) 2080 2081 /*define for src_sw field*/ 2082 #define SDMA_PKT_COPY_T2T_DW_14_src_sw_offset 14 2083 #define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask 0x00000003 2084 #define SDMA_PKT_COPY_T2T_DW_14_src_sw_shift 24 2085 #define SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift) 2086 2087 /*define for src_cache_policy field*/ 2088 #define SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_offset 14 2089 #define SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_mask 0x00000007 2090 #define SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_shift 26 2091 #define SDMA_PKT_COPY_T2T_DW_14_SRC_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_mask) << SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_shift) 2092 2093 /*define for META_ADDR_LO word*/ 2094 /*define for meta_addr_31_0 field*/ 2095 #define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset 15 2096 #define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask 0xFFFFFFFF 2097 #define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift 0 2098 #define SDMA_PKT_COPY_T2T_META_ADDR_LO_META_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask) << SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift) 2099 2100 /*define for META_ADDR_HI word*/ 2101 /*define for meta_addr_63_32 field*/ 2102 #define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset 16 2103 #define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask 0xFFFFFFFF 2104 #define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift 0 2105 #define SDMA_PKT_COPY_T2T_META_ADDR_HI_META_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask) << SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift) 2106 2107 /*define for META_CONFIG word*/ 2108 /*define for data_format field*/ 2109 #define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset 17 2110 #define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask 0x0000007F 2111 #define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift 0 2112 #define SDMA_PKT_COPY_T2T_META_CONFIG_DATA_FORMAT(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift) 2113 2114 /*define for color_transform_disable field*/ 2115 #define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset 17 2116 #define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask 0x00000001 2117 #define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift 7 2118 #define SDMA_PKT_COPY_T2T_META_CONFIG_COLOR_TRANSFORM_DISABLE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift) 2119 2120 /*define for alpha_is_on_msb field*/ 2121 #define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset 17 2122 #define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask 0x00000001 2123 #define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift 8 2124 #define SDMA_PKT_COPY_T2T_META_CONFIG_ALPHA_IS_ON_MSB(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift) 2125 2126 /*define for number_type field*/ 2127 #define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset 17 2128 #define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask 0x00000007 2129 #define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift 9 2130 #define SDMA_PKT_COPY_T2T_META_CONFIG_NUMBER_TYPE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift) 2131 2132 /*define for surface_type field*/ 2133 #define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset 17 2134 #define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask 0x00000003 2135 #define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift 12 2136 #define SDMA_PKT_COPY_T2T_META_CONFIG_SURFACE_TYPE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift) 2137 2138 /*define for meta_llc field*/ 2139 #define SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_offset 17 2140 #define SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_mask 0x00000001 2141 #define SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_shift 14 2142 #define SDMA_PKT_COPY_T2T_META_CONFIG_META_LLC(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_shift) 2143 2144 /*define for max_comp_block_size field*/ 2145 #define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset 17 2146 #define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask 0x00000003 2147 #define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift 24 2148 #define SDMA_PKT_COPY_T2T_META_CONFIG_MAX_COMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift) 2149 2150 /*define for max_uncomp_block_size field*/ 2151 #define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset 17 2152 #define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask 0x00000003 2153 #define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift 26 2154 #define SDMA_PKT_COPY_T2T_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift) 2155 2156 /*define for write_compress_enable field*/ 2157 #define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset 17 2158 #define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask 0x00000001 2159 #define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift 28 2160 #define SDMA_PKT_COPY_T2T_META_CONFIG_WRITE_COMPRESS_ENABLE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift) 2161 2162 /*define for meta_tmz field*/ 2163 #define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset 17 2164 #define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask 0x00000001 2165 #define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift 29 2166 #define SDMA_PKT_COPY_T2T_META_CONFIG_META_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift) 2167 2168 /*define for pipe_aligned field*/ 2169 #define SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_offset 17 2170 #define SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_mask 0x00000001 2171 #define SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_shift 31 2172 #define SDMA_PKT_COPY_T2T_META_CONFIG_PIPE_ALIGNED(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_shift) 2173 2174 2175 /* 2176 ** Definitions for SDMA_PKT_COPY_T2T_BC packet 2177 */ 2178 2179 /*define for HEADER word*/ 2180 /*define for op field*/ 2181 #define SDMA_PKT_COPY_T2T_BC_HEADER_op_offset 0 2182 #define SDMA_PKT_COPY_T2T_BC_HEADER_op_mask 0x000000FF 2183 #define SDMA_PKT_COPY_T2T_BC_HEADER_op_shift 0 2184 #define SDMA_PKT_COPY_T2T_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_BC_HEADER_op_mask) << SDMA_PKT_COPY_T2T_BC_HEADER_op_shift) 2185 2186 /*define for sub_op field*/ 2187 #define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset 0 2188 #define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask 0x000000FF 2189 #define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift 8 2190 #define SDMA_PKT_COPY_T2T_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift) 2191 2192 /*define for SRC_ADDR_LO word*/ 2193 /*define for src_addr_31_0 field*/ 2194 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset 1 2195 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 2196 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift 0 2197 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift) 2198 2199 /*define for SRC_ADDR_HI word*/ 2200 /*define for src_addr_63_32 field*/ 2201 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset 2 2202 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 2203 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift 0 2204 #define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift) 2205 2206 /*define for DW_3 word*/ 2207 /*define for src_x field*/ 2208 #define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset 3 2209 #define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask 0x00003FFF 2210 #define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift 0 2211 #define SDMA_PKT_COPY_T2T_BC_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift) 2212 2213 /*define for src_y field*/ 2214 #define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset 3 2215 #define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask 0x00003FFF 2216 #define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift 16 2217 #define SDMA_PKT_COPY_T2T_BC_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift) 2218 2219 /*define for DW_4 word*/ 2220 /*define for src_z field*/ 2221 #define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset 4 2222 #define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask 0x000007FF 2223 #define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift 0 2224 #define SDMA_PKT_COPY_T2T_BC_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift) 2225 2226 /*define for src_width field*/ 2227 #define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset 4 2228 #define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask 0x00003FFF 2229 #define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift 16 2230 #define SDMA_PKT_COPY_T2T_BC_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift) 2231 2232 /*define for DW_5 word*/ 2233 /*define for src_height field*/ 2234 #define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset 5 2235 #define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask 0x00003FFF 2236 #define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift 0 2237 #define SDMA_PKT_COPY_T2T_BC_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift) 2238 2239 /*define for src_depth field*/ 2240 #define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset 5 2241 #define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask 0x000007FF 2242 #define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift 16 2243 #define SDMA_PKT_COPY_T2T_BC_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift) 2244 2245 /*define for DW_6 word*/ 2246 /*define for src_element_size field*/ 2247 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset 6 2248 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask 0x00000007 2249 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift 0 2250 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift) 2251 2252 /*define for src_array_mode field*/ 2253 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset 6 2254 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask 0x0000000F 2255 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift 3 2256 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift) 2257 2258 /*define for src_mit_mode field*/ 2259 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset 6 2260 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask 0x00000007 2261 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift 8 2262 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift) 2263 2264 /*define for src_tilesplit_size field*/ 2265 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset 6 2266 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask 0x00000007 2267 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift 11 2268 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift) 2269 2270 /*define for src_bank_w field*/ 2271 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset 6 2272 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask 0x00000003 2273 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift 15 2274 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift) 2275 2276 /*define for src_bank_h field*/ 2277 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset 6 2278 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask 0x00000003 2279 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift 18 2280 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift) 2281 2282 /*define for src_num_bank field*/ 2283 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset 6 2284 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask 0x00000003 2285 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift 21 2286 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift) 2287 2288 /*define for src_mat_aspt field*/ 2289 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset 6 2290 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask 0x00000003 2291 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift 24 2292 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift) 2293 2294 /*define for src_pipe_config field*/ 2295 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset 6 2296 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask 0x0000001F 2297 #define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift 26 2298 #define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift) 2299 2300 /*define for DST_ADDR_LO word*/ 2301 /*define for dst_addr_31_0 field*/ 2302 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset 7 2303 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 2304 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 2305 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift) 2306 2307 /*define for DST_ADDR_HI word*/ 2308 /*define for dst_addr_63_32 field*/ 2309 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset 8 2310 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 2311 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 2312 #define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift) 2313 2314 /*define for DW_9 word*/ 2315 /*define for dst_x field*/ 2316 #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset 9 2317 #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask 0x00003FFF 2318 #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift 0 2319 #define SDMA_PKT_COPY_T2T_BC_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift) 2320 2321 /*define for dst_y field*/ 2322 #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset 9 2323 #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask 0x00003FFF 2324 #define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift 16 2325 #define SDMA_PKT_COPY_T2T_BC_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift) 2326 2327 /*define for DW_10 word*/ 2328 /*define for dst_z field*/ 2329 #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset 10 2330 #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask 0x000007FF 2331 #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift 0 2332 #define SDMA_PKT_COPY_T2T_BC_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift) 2333 2334 /*define for dst_width field*/ 2335 #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset 10 2336 #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask 0x00003FFF 2337 #define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift 16 2338 #define SDMA_PKT_COPY_T2T_BC_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift) 2339 2340 /*define for DW_11 word*/ 2341 /*define for dst_height field*/ 2342 #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset 11 2343 #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask 0x00003FFF 2344 #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift 0 2345 #define SDMA_PKT_COPY_T2T_BC_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift) 2346 2347 /*define for dst_depth field*/ 2348 #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset 11 2349 #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask 0x00000FFF 2350 #define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift 16 2351 #define SDMA_PKT_COPY_T2T_BC_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift) 2352 2353 /*define for DW_12 word*/ 2354 /*define for dst_element_size field*/ 2355 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset 12 2356 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask 0x00000007 2357 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift 0 2358 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift) 2359 2360 /*define for dst_array_mode field*/ 2361 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset 12 2362 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask 0x0000000F 2363 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift 3 2364 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift) 2365 2366 /*define for dst_mit_mode field*/ 2367 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset 12 2368 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask 0x00000007 2369 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift 8 2370 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift) 2371 2372 /*define for dst_tilesplit_size field*/ 2373 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset 12 2374 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask 0x00000007 2375 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift 11 2376 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift) 2377 2378 /*define for dst_bank_w field*/ 2379 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset 12 2380 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask 0x00000003 2381 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift 15 2382 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift) 2383 2384 /*define for dst_bank_h field*/ 2385 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset 12 2386 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask 0x00000003 2387 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift 18 2388 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift) 2389 2390 /*define for dst_num_bank field*/ 2391 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset 12 2392 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask 0x00000003 2393 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift 21 2394 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift) 2395 2396 /*define for dst_mat_aspt field*/ 2397 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset 12 2398 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask 0x00000003 2399 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift 24 2400 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift) 2401 2402 /*define for dst_pipe_config field*/ 2403 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset 12 2404 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask 0x0000001F 2405 #define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift 26 2406 #define SDMA_PKT_COPY_T2T_BC_DW_12_DST_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift) 2407 2408 /*define for DW_13 word*/ 2409 /*define for rect_x field*/ 2410 #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset 13 2411 #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask 0x00003FFF 2412 #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift 0 2413 #define SDMA_PKT_COPY_T2T_BC_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift) 2414 2415 /*define for rect_y field*/ 2416 #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset 13 2417 #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask 0x00003FFF 2418 #define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift 16 2419 #define SDMA_PKT_COPY_T2T_BC_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift) 2420 2421 /*define for DW_14 word*/ 2422 /*define for rect_z field*/ 2423 #define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset 14 2424 #define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask 0x000007FF 2425 #define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift 0 2426 #define SDMA_PKT_COPY_T2T_BC_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift) 2427 2428 /*define for dst_sw field*/ 2429 #define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset 14 2430 #define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask 0x00000003 2431 #define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift 16 2432 #define SDMA_PKT_COPY_T2T_BC_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift) 2433 2434 /*define for src_sw field*/ 2435 #define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset 14 2436 #define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask 0x00000003 2437 #define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift 24 2438 #define SDMA_PKT_COPY_T2T_BC_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift) 2439 2440 2441 /* 2442 ** Definitions for SDMA_PKT_COPY_TILED_SUBWIN packet 2443 */ 2444 2445 /*define for HEADER word*/ 2446 /*define for op field*/ 2447 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 0 2448 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask 0x000000FF 2449 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift 0 2450 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift) 2451 2452 /*define for sub_op field*/ 2453 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 0 2454 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask 0x000000FF 2455 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift 8 2456 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift) 2457 2458 /*define for tmz field*/ 2459 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset 0 2460 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask 0x00000001 2461 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift 18 2462 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift) 2463 2464 /*define for dcc field*/ 2465 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset 0 2466 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask 0x00000001 2467 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift 19 2468 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DCC(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift) 2469 2470 /*define for cpv field*/ 2471 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_offset 0 2472 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_mask 0x00000001 2473 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_shift 28 2474 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_shift) 2475 2476 /*define for detile field*/ 2477 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 0 2478 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask 0x00000001 2479 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift 31 2480 #define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift) 2481 2482 /*define for TILED_ADDR_LO word*/ 2483 /*define for tiled_addr_31_0 field*/ 2484 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset 1 2485 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 2486 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift 0 2487 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift) 2488 2489 /*define for TILED_ADDR_HI word*/ 2490 /*define for tiled_addr_63_32 field*/ 2491 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset 2 2492 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 2493 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift 0 2494 #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift) 2495 2496 /*define for DW_3 word*/ 2497 /*define for tiled_x field*/ 2498 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset 3 2499 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask 0x00003FFF 2500 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift 0 2501 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift) 2502 2503 /*define for tiled_y field*/ 2504 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset 3 2505 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask 0x00003FFF 2506 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift 16 2507 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift) 2508 2509 /*define for DW_4 word*/ 2510 /*define for tiled_z field*/ 2511 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset 4 2512 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask 0x00001FFF 2513 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift 0 2514 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift) 2515 2516 /*define for width field*/ 2517 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset 4 2518 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask 0x00003FFF 2519 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift 16 2520 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift) 2521 2522 /*define for DW_5 word*/ 2523 /*define for height field*/ 2524 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset 5 2525 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask 0x00003FFF 2526 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift 0 2527 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift) 2528 2529 /*define for depth field*/ 2530 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset 5 2531 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask 0x00001FFF 2532 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift 16 2533 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift) 2534 2535 /*define for DW_6 word*/ 2536 /*define for element_size field*/ 2537 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset 6 2538 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask 0x00000007 2539 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift 0 2540 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift) 2541 2542 /*define for swizzle_mode field*/ 2543 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset 6 2544 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask 0x0000001F 2545 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift 3 2546 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift) 2547 2548 /*define for dimension field*/ 2549 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset 6 2550 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask 0x00000003 2551 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift 9 2552 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift) 2553 2554 /*define for mip_max field*/ 2555 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset 6 2556 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask 0x0000000F 2557 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift 16 2558 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift) 2559 2560 /*define for mip_id field*/ 2561 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset 6 2562 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask 0x0000000F 2563 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift 20 2564 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_ID(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift) 2565 2566 /*define for LINEAR_ADDR_LO word*/ 2567 /*define for linear_addr_31_0 field*/ 2568 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 2569 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 2570 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 2571 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift) 2572 2573 /*define for LINEAR_ADDR_HI word*/ 2574 /*define for linear_addr_63_32 field*/ 2575 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 2576 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 2577 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 2578 #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift) 2579 2580 /*define for DW_9 word*/ 2581 /*define for linear_x field*/ 2582 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset 9 2583 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask 0x00003FFF 2584 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift 0 2585 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift) 2586 2587 /*define for linear_y field*/ 2588 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset 9 2589 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask 0x00003FFF 2590 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift 16 2591 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift) 2592 2593 /*define for DW_10 word*/ 2594 /*define for linear_z field*/ 2595 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset 10 2596 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask 0x00001FFF 2597 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift 0 2598 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift) 2599 2600 /*define for linear_pitch field*/ 2601 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset 10 2602 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask 0x00003FFF 2603 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift 16 2604 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift) 2605 2606 /*define for DW_11 word*/ 2607 /*define for linear_slice_pitch field*/ 2608 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset 11 2609 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask 0x0FFFFFFF 2610 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift 0 2611 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift) 2612 2613 /*define for DW_12 word*/ 2614 /*define for rect_x field*/ 2615 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset 12 2616 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask 0x00003FFF 2617 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift 0 2618 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift) 2619 2620 /*define for rect_y field*/ 2621 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset 12 2622 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask 0x00003FFF 2623 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift 16 2624 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift) 2625 2626 /*define for DW_13 word*/ 2627 /*define for rect_z field*/ 2628 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset 13 2629 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask 0x00001FFF 2630 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift 0 2631 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift) 2632 2633 /*define for linear_sw field*/ 2634 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset 13 2635 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask 0x00000003 2636 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift 16 2637 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift) 2638 2639 /*define for linear_cache_policy field*/ 2640 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_offset 13 2641 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_mask 0x00000007 2642 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_shift 18 2643 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_shift) 2644 2645 /*define for tile_sw field*/ 2646 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset 13 2647 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask 0x00000003 2648 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift 24 2649 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift) 2650 2651 /*define for tile_cache_policy field*/ 2652 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_offset 13 2653 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_mask 0x00000007 2654 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_shift 26 2655 #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_shift) 2656 2657 /*define for META_ADDR_LO word*/ 2658 /*define for meta_addr_31_0 field*/ 2659 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset 14 2660 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask 0xFFFFFFFF 2661 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift 0 2662 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_META_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift) 2663 2664 /*define for META_ADDR_HI word*/ 2665 /*define for meta_addr_63_32 field*/ 2666 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset 15 2667 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask 0xFFFFFFFF 2668 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift 0 2669 #define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_META_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift) 2670 2671 /*define for META_CONFIG word*/ 2672 /*define for data_format field*/ 2673 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset 16 2674 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask 0x0000007F 2675 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift 0 2676 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_DATA_FORMAT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift) 2677 2678 /*define for color_transform_disable field*/ 2679 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset 16 2680 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask 0x00000001 2681 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift 7 2682 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_COLOR_TRANSFORM_DISABLE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift) 2683 2684 /*define for alpha_is_on_msb field*/ 2685 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset 16 2686 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask 0x00000001 2687 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift 8 2688 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_ALPHA_IS_ON_MSB(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift) 2689 2690 /*define for number_type field*/ 2691 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset 16 2692 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask 0x00000007 2693 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift 9 2694 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_NUMBER_TYPE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift) 2695 2696 /*define for surface_type field*/ 2697 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset 16 2698 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask 0x00000003 2699 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift 12 2700 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_SURFACE_TYPE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift) 2701 2702 /*define for meta_llc field*/ 2703 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_offset 16 2704 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_mask 0x00000001 2705 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_shift 14 2706 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_LLC(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_shift) 2707 2708 /*define for max_comp_block_size field*/ 2709 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset 16 2710 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask 0x00000003 2711 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift 24 2712 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_COMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift) 2713 2714 /*define for max_uncomp_block_size field*/ 2715 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset 16 2716 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask 0x00000003 2717 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift 26 2718 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift) 2719 2720 /*define for write_compress_enable field*/ 2721 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset 16 2722 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask 0x00000001 2723 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift 28 2724 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_WRITE_COMPRESS_ENABLE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift) 2725 2726 /*define for meta_tmz field*/ 2727 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset 16 2728 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask 0x00000001 2729 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift 29 2730 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift) 2731 2732 /*define for pipe_aligned field*/ 2733 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_offset 16 2734 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_mask 0x00000001 2735 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_shift 31 2736 #define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_PIPE_ALIGNED(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_shift) 2737 2738 2739 /* 2740 ** Definitions for SDMA_PKT_COPY_TILED_SUBWIN_BC packet 2741 */ 2742 2743 /*define for HEADER word*/ 2744 /*define for op field*/ 2745 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset 0 2746 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask 0x000000FF 2747 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift 0 2748 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift) 2749 2750 /*define for sub_op field*/ 2751 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset 0 2752 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask 0x000000FF 2753 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift 8 2754 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift) 2755 2756 /*define for detile field*/ 2757 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset 0 2758 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask 0x00000001 2759 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift 31 2760 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift) 2761 2762 /*define for TILED_ADDR_LO word*/ 2763 /*define for tiled_addr_31_0 field*/ 2764 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset 1 2765 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF 2766 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift 0 2767 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift) 2768 2769 /*define for TILED_ADDR_HI word*/ 2770 /*define for tiled_addr_63_32 field*/ 2771 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset 2 2772 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF 2773 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift 0 2774 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift) 2775 2776 /*define for DW_3 word*/ 2777 /*define for tiled_x field*/ 2778 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset 3 2779 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask 0x00003FFF 2780 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift 0 2781 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift) 2782 2783 /*define for tiled_y field*/ 2784 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset 3 2785 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask 0x00003FFF 2786 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift 16 2787 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift) 2788 2789 /*define for DW_4 word*/ 2790 /*define for tiled_z field*/ 2791 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset 4 2792 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask 0x000007FF 2793 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift 0 2794 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift) 2795 2796 /*define for width field*/ 2797 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset 4 2798 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask 0x00003FFF 2799 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift 16 2800 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift) 2801 2802 /*define for DW_5 word*/ 2803 /*define for height field*/ 2804 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset 5 2805 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask 0x00003FFF 2806 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift 0 2807 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift) 2808 2809 /*define for depth field*/ 2810 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset 5 2811 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask 0x000007FF 2812 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift 16 2813 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift) 2814 2815 /*define for DW_6 word*/ 2816 /*define for element_size field*/ 2817 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset 6 2818 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask 0x00000007 2819 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift 0 2820 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift) 2821 2822 /*define for array_mode field*/ 2823 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset 6 2824 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask 0x0000000F 2825 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift 3 2826 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift) 2827 2828 /*define for mit_mode field*/ 2829 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset 6 2830 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask 0x00000007 2831 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift 8 2832 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift) 2833 2834 /*define for tilesplit_size field*/ 2835 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset 6 2836 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask 0x00000007 2837 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift 11 2838 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift) 2839 2840 /*define for bank_w field*/ 2841 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset 6 2842 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask 0x00000003 2843 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift 15 2844 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift) 2845 2846 /*define for bank_h field*/ 2847 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset 6 2848 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask 0x00000003 2849 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift 18 2850 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift) 2851 2852 /*define for num_bank field*/ 2853 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset 6 2854 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask 0x00000003 2855 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift 21 2856 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift) 2857 2858 /*define for mat_aspt field*/ 2859 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset 6 2860 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask 0x00000003 2861 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift 24 2862 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift) 2863 2864 /*define for pipe_config field*/ 2865 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset 6 2866 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask 0x0000001F 2867 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift 26 2868 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift) 2869 2870 /*define for LINEAR_ADDR_LO word*/ 2871 /*define for linear_addr_31_0 field*/ 2872 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 2873 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 2874 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 2875 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift) 2876 2877 /*define for LINEAR_ADDR_HI word*/ 2878 /*define for linear_addr_63_32 field*/ 2879 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 2880 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 2881 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 2882 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift) 2883 2884 /*define for DW_9 word*/ 2885 /*define for linear_x field*/ 2886 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset 9 2887 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask 0x00003FFF 2888 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift 0 2889 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift) 2890 2891 /*define for linear_y field*/ 2892 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset 9 2893 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask 0x00003FFF 2894 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift 16 2895 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift) 2896 2897 /*define for DW_10 word*/ 2898 /*define for linear_z field*/ 2899 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset 10 2900 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask 0x000007FF 2901 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift 0 2902 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift) 2903 2904 /*define for linear_pitch field*/ 2905 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset 10 2906 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask 0x00003FFF 2907 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift 16 2908 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift) 2909 2910 /*define for DW_11 word*/ 2911 /*define for linear_slice_pitch field*/ 2912 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset 11 2913 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask 0x0FFFFFFF 2914 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift 0 2915 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift) 2916 2917 /*define for DW_12 word*/ 2918 /*define for rect_x field*/ 2919 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset 12 2920 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask 0x00003FFF 2921 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift 0 2922 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift) 2923 2924 /*define for rect_y field*/ 2925 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset 12 2926 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask 0x00003FFF 2927 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift 16 2928 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift) 2929 2930 /*define for DW_13 word*/ 2931 /*define for rect_z field*/ 2932 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset 13 2933 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask 0x000007FF 2934 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift 0 2935 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift) 2936 2937 /*define for linear_sw field*/ 2938 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset 13 2939 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask 0x00000003 2940 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift 16 2941 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift) 2942 2943 /*define for tile_sw field*/ 2944 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset 13 2945 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask 0x00000003 2946 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift 24 2947 #define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift) 2948 2949 2950 /* 2951 ** Definitions for SDMA_PKT_COPY_STRUCT packet 2952 */ 2953 2954 /*define for HEADER word*/ 2955 /*define for op field*/ 2956 #define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 0 2957 #define SDMA_PKT_COPY_STRUCT_HEADER_op_mask 0x000000FF 2958 #define SDMA_PKT_COPY_STRUCT_HEADER_op_shift 0 2959 #define SDMA_PKT_COPY_STRUCT_HEADER_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift) 2960 2961 /*define for sub_op field*/ 2962 #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 0 2963 #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask 0x000000FF 2964 #define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift 8 2965 #define SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift) 2966 2967 /*define for tmz field*/ 2968 #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset 0 2969 #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask 0x00000001 2970 #define SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift 18 2971 #define SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask) << SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift) 2972 2973 /*define for cpv field*/ 2974 #define SDMA_PKT_COPY_STRUCT_HEADER_cpv_offset 0 2975 #define SDMA_PKT_COPY_STRUCT_HEADER_cpv_mask 0x00000001 2976 #define SDMA_PKT_COPY_STRUCT_HEADER_cpv_shift 28 2977 #define SDMA_PKT_COPY_STRUCT_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_cpv_mask) << SDMA_PKT_COPY_STRUCT_HEADER_cpv_shift) 2978 2979 /*define for detile field*/ 2980 #define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 0 2981 #define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask 0x00000001 2982 #define SDMA_PKT_COPY_STRUCT_HEADER_detile_shift 31 2983 #define SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift) 2984 2985 /*define for SB_ADDR_LO word*/ 2986 /*define for sb_addr_31_0 field*/ 2987 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset 1 2988 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask 0xFFFFFFFF 2989 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift 0 2990 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift) 2991 2992 /*define for SB_ADDR_HI word*/ 2993 /*define for sb_addr_63_32 field*/ 2994 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset 2 2995 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask 0xFFFFFFFF 2996 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift 0 2997 #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift) 2998 2999 /*define for START_INDEX word*/ 3000 /*define for start_index field*/ 3001 #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset 3 3002 #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask 0xFFFFFFFF 3003 #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift 0 3004 #define SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x) (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift) 3005 3006 /*define for COUNT word*/ 3007 /*define for count field*/ 3008 #define SDMA_PKT_COPY_STRUCT_COUNT_count_offset 4 3009 #define SDMA_PKT_COPY_STRUCT_COUNT_count_mask 0xFFFFFFFF 3010 #define SDMA_PKT_COPY_STRUCT_COUNT_count_shift 0 3011 #define SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift) 3012 3013 /*define for DW_5 word*/ 3014 /*define for stride field*/ 3015 #define SDMA_PKT_COPY_STRUCT_DW_5_stride_offset 5 3016 #define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask 0x000007FF 3017 #define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift 0 3018 #define SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift) 3019 3020 /*define for linear_sw field*/ 3021 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset 5 3022 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask 0x00000003 3023 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift 16 3024 #define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift) 3025 3026 /*define for linear_cache_policy field*/ 3027 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_offset 5 3028 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_mask 0x00000007 3029 #define SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_shift 18 3030 #define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_shift) 3031 3032 /*define for struct_sw field*/ 3033 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset 5 3034 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask 0x00000003 3035 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift 24 3036 #define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift) 3037 3038 /*define for struct_cache_policy field*/ 3039 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_offset 5 3040 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_mask 0x00000007 3041 #define SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_shift 26 3042 #define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_shift) 3043 3044 /*define for LINEAR_ADDR_LO word*/ 3045 /*define for linear_addr_31_0 field*/ 3046 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset 6 3047 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF 3048 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 3049 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift) 3050 3051 /*define for LINEAR_ADDR_HI word*/ 3052 /*define for linear_addr_63_32 field*/ 3053 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset 7 3054 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF 3055 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 3056 #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift) 3057 3058 3059 /* 3060 ** Definitions for SDMA_PKT_WRITE_UNTILED packet 3061 */ 3062 3063 /*define for HEADER word*/ 3064 /*define for op field*/ 3065 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 0 3066 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask 0x000000FF 3067 #define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift 0 3068 #define SDMA_PKT_WRITE_UNTILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift) 3069 3070 /*define for sub_op field*/ 3071 #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 0 3072 #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask 0x000000FF 3073 #define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift 8 3074 #define SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift) 3075 3076 /*define for encrypt field*/ 3077 #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset 0 3078 #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask 0x00000001 3079 #define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift 16 3080 #define SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift) 3081 3082 /*define for tmz field*/ 3083 #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset 0 3084 #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask 0x00000001 3085 #define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift 18 3086 #define SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift) 3087 3088 /*define for cpv field*/ 3089 #define SDMA_PKT_WRITE_UNTILED_HEADER_cpv_offset 0 3090 #define SDMA_PKT_WRITE_UNTILED_HEADER_cpv_mask 0x00000001 3091 #define SDMA_PKT_WRITE_UNTILED_HEADER_cpv_shift 28 3092 #define SDMA_PKT_WRITE_UNTILED_HEADER_CPV(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_cpv_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_cpv_shift) 3093 3094 /*define for DST_ADDR_LO word*/ 3095 /*define for dst_addr_31_0 field*/ 3096 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset 1 3097 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 3098 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift 0 3099 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift) 3100 3101 /*define for DST_ADDR_HI word*/ 3102 /*define for dst_addr_63_32 field*/ 3103 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset 2 3104 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 3105 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift 0 3106 #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift) 3107 3108 /*define for DW_3 word*/ 3109 /*define for count field*/ 3110 #define SDMA_PKT_WRITE_UNTILED_DW_3_count_offset 3 3111 #define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask 0x000FFFFF 3112 #define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift 0 3113 #define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) 3114 3115 /*define for sw field*/ 3116 #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset 3 3117 #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask 0x00000003 3118 #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift 24 3119 #define SDMA_PKT_WRITE_UNTILED_DW_3_SW(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift) 3120 3121 /*define for cache_policy field*/ 3122 #define SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_offset 3 3123 #define SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_mask 0x00000007 3124 #define SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_shift 26 3125 #define SDMA_PKT_WRITE_UNTILED_DW_3_CACHE_POLICY(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_shift) 3126 3127 /*define for DATA0 word*/ 3128 /*define for data0 field*/ 3129 #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset 4 3130 #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask 0xFFFFFFFF 3131 #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift 0 3132 #define SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift) 3133 3134 3135 /* 3136 ** Definitions for SDMA_PKT_WRITE_TILED packet 3137 */ 3138 3139 /*define for HEADER word*/ 3140 /*define for op field*/ 3141 #define SDMA_PKT_WRITE_TILED_HEADER_op_offset 0 3142 #define SDMA_PKT_WRITE_TILED_HEADER_op_mask 0x000000FF 3143 #define SDMA_PKT_WRITE_TILED_HEADER_op_shift 0 3144 #define SDMA_PKT_WRITE_TILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift) 3145 3146 /*define for sub_op field*/ 3147 #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 0 3148 #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask 0x000000FF 3149 #define SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift 8 3150 #define SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift) 3151 3152 /*define for encrypt field*/ 3153 #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset 0 3154 #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask 0x00000001 3155 #define SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift 16 3156 #define SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift) 3157 3158 /*define for tmz field*/ 3159 #define SDMA_PKT_WRITE_TILED_HEADER_tmz_offset 0 3160 #define SDMA_PKT_WRITE_TILED_HEADER_tmz_mask 0x00000001 3161 #define SDMA_PKT_WRITE_TILED_HEADER_tmz_shift 18 3162 #define SDMA_PKT_WRITE_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_TILED_HEADER_tmz_shift) 3163 3164 /*define for cpv field*/ 3165 #define SDMA_PKT_WRITE_TILED_HEADER_cpv_offset 0 3166 #define SDMA_PKT_WRITE_TILED_HEADER_cpv_mask 0x00000001 3167 #define SDMA_PKT_WRITE_TILED_HEADER_cpv_shift 28 3168 #define SDMA_PKT_WRITE_TILED_HEADER_CPV(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_cpv_mask) << SDMA_PKT_WRITE_TILED_HEADER_cpv_shift) 3169 3170 /*define for DST_ADDR_LO word*/ 3171 /*define for dst_addr_31_0 field*/ 3172 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset 1 3173 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 3174 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift 0 3175 #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift) 3176 3177 /*define for DST_ADDR_HI word*/ 3178 /*define for dst_addr_63_32 field*/ 3179 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset 2 3180 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 3181 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift 0 3182 #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift) 3183 3184 /*define for DW_3 word*/ 3185 /*define for width field*/ 3186 #define SDMA_PKT_WRITE_TILED_DW_3_width_offset 3 3187 #define SDMA_PKT_WRITE_TILED_DW_3_width_mask 0x00003FFF 3188 #define SDMA_PKT_WRITE_TILED_DW_3_width_shift 0 3189 #define SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_DW_3_width_shift) 3190 3191 /*define for DW_4 word*/ 3192 /*define for height field*/ 3193 #define SDMA_PKT_WRITE_TILED_DW_4_height_offset 4 3194 #define SDMA_PKT_WRITE_TILED_DW_4_height_mask 0x00003FFF 3195 #define SDMA_PKT_WRITE_TILED_DW_4_height_shift 0 3196 #define SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_DW_4_height_shift) 3197 3198 /*define for depth field*/ 3199 #define SDMA_PKT_WRITE_TILED_DW_4_depth_offset 4 3200 #define SDMA_PKT_WRITE_TILED_DW_4_depth_mask 0x00001FFF 3201 #define SDMA_PKT_WRITE_TILED_DW_4_depth_shift 16 3202 #define SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_DW_4_depth_shift) 3203 3204 /*define for DW_5 word*/ 3205 /*define for element_size field*/ 3206 #define SDMA_PKT_WRITE_TILED_DW_5_element_size_offset 5 3207 #define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask 0x00000007 3208 #define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift 0 3209 #define SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift) 3210 3211 /*define for swizzle_mode field*/ 3212 #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset 5 3213 #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask 0x0000001F 3214 #define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift 3 3215 #define SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift) 3216 3217 /*define for dimension field*/ 3218 #define SDMA_PKT_WRITE_TILED_DW_5_dimension_offset 5 3219 #define SDMA_PKT_WRITE_TILED_DW_5_dimension_mask 0x00000003 3220 #define SDMA_PKT_WRITE_TILED_DW_5_dimension_shift 9 3221 #define SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_dimension_mask) << SDMA_PKT_WRITE_TILED_DW_5_dimension_shift) 3222 3223 /*define for mip_max field*/ 3224 #define SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset 5 3225 #define SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask 0x0000000F 3226 #define SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift 16 3227 #define SDMA_PKT_WRITE_TILED_DW_5_MIP_MAX(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask) << SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift) 3228 3229 /*define for DW_6 word*/ 3230 /*define for x field*/ 3231 #define SDMA_PKT_WRITE_TILED_DW_6_x_offset 6 3232 #define SDMA_PKT_WRITE_TILED_DW_6_x_mask 0x00003FFF 3233 #define SDMA_PKT_WRITE_TILED_DW_6_x_shift 0 3234 #define SDMA_PKT_WRITE_TILED_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift) 3235 3236 /*define for y field*/ 3237 #define SDMA_PKT_WRITE_TILED_DW_6_y_offset 6 3238 #define SDMA_PKT_WRITE_TILED_DW_6_y_mask 0x00003FFF 3239 #define SDMA_PKT_WRITE_TILED_DW_6_y_shift 16 3240 #define SDMA_PKT_WRITE_TILED_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift) 3241 3242 /*define for DW_7 word*/ 3243 /*define for z field*/ 3244 #define SDMA_PKT_WRITE_TILED_DW_7_z_offset 7 3245 #define SDMA_PKT_WRITE_TILED_DW_7_z_mask 0x00001FFF 3246 #define SDMA_PKT_WRITE_TILED_DW_7_z_shift 0 3247 #define SDMA_PKT_WRITE_TILED_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift) 3248 3249 /*define for sw field*/ 3250 #define SDMA_PKT_WRITE_TILED_DW_7_sw_offset 7 3251 #define SDMA_PKT_WRITE_TILED_DW_7_sw_mask 0x00000003 3252 #define SDMA_PKT_WRITE_TILED_DW_7_sw_shift 24 3253 #define SDMA_PKT_WRITE_TILED_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift) 3254 3255 /*define for cache_policy field*/ 3256 #define SDMA_PKT_WRITE_TILED_DW_7_cache_policy_offset 7 3257 #define SDMA_PKT_WRITE_TILED_DW_7_cache_policy_mask 0x00000007 3258 #define SDMA_PKT_WRITE_TILED_DW_7_cache_policy_shift 26 3259 #define SDMA_PKT_WRITE_TILED_DW_7_CACHE_POLICY(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_cache_policy_mask) << SDMA_PKT_WRITE_TILED_DW_7_cache_policy_shift) 3260 3261 /*define for COUNT word*/ 3262 /*define for count field*/ 3263 #define SDMA_PKT_WRITE_TILED_COUNT_count_offset 8 3264 #define SDMA_PKT_WRITE_TILED_COUNT_count_mask 0x000FFFFF 3265 #define SDMA_PKT_WRITE_TILED_COUNT_count_shift 0 3266 #define SDMA_PKT_WRITE_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift) 3267 3268 /*define for DATA0 word*/ 3269 /*define for data0 field*/ 3270 #define SDMA_PKT_WRITE_TILED_DATA0_data0_offset 9 3271 #define SDMA_PKT_WRITE_TILED_DATA0_data0_mask 0xFFFFFFFF 3272 #define SDMA_PKT_WRITE_TILED_DATA0_data0_shift 0 3273 #define SDMA_PKT_WRITE_TILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift) 3274 3275 3276 /* 3277 ** Definitions for SDMA_PKT_WRITE_TILED_BC packet 3278 */ 3279 3280 /*define for HEADER word*/ 3281 /*define for op field*/ 3282 #define SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset 0 3283 #define SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask 0x000000FF 3284 #define SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift 0 3285 #define SDMA_PKT_WRITE_TILED_BC_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift) 3286 3287 /*define for sub_op field*/ 3288 #define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset 0 3289 #define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask 0x000000FF 3290 #define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift 8 3291 #define SDMA_PKT_WRITE_TILED_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift) 3292 3293 /*define for DST_ADDR_LO word*/ 3294 /*define for dst_addr_31_0 field*/ 3295 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset 1 3296 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 3297 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 3298 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift) 3299 3300 /*define for DST_ADDR_HI word*/ 3301 /*define for dst_addr_63_32 field*/ 3302 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset 2 3303 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 3304 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 3305 #define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift) 3306 3307 /*define for DW_3 word*/ 3308 /*define for width field*/ 3309 #define SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset 3 3310 #define SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask 0x00003FFF 3311 #define SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift 0 3312 #define SDMA_PKT_WRITE_TILED_BC_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift) 3313 3314 /*define for DW_4 word*/ 3315 /*define for height field*/ 3316 #define SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset 4 3317 #define SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask 0x00003FFF 3318 #define SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift 0 3319 #define SDMA_PKT_WRITE_TILED_BC_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift) 3320 3321 /*define for depth field*/ 3322 #define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset 4 3323 #define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask 0x000007FF 3324 #define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift 16 3325 #define SDMA_PKT_WRITE_TILED_BC_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift) 3326 3327 /*define for DW_5 word*/ 3328 /*define for element_size field*/ 3329 #define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset 5 3330 #define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask 0x00000007 3331 #define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift 0 3332 #define SDMA_PKT_WRITE_TILED_BC_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift) 3333 3334 /*define for array_mode field*/ 3335 #define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset 5 3336 #define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask 0x0000000F 3337 #define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift 3 3338 #define SDMA_PKT_WRITE_TILED_BC_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift) 3339 3340 /*define for mit_mode field*/ 3341 #define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset 5 3342 #define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask 0x00000007 3343 #define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift 8 3344 #define SDMA_PKT_WRITE_TILED_BC_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift) 3345 3346 /*define for tilesplit_size field*/ 3347 #define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset 5 3348 #define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask 0x00000007 3349 #define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift 11 3350 #define SDMA_PKT_WRITE_TILED_BC_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift) 3351 3352 /*define for bank_w field*/ 3353 #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset 5 3354 #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask 0x00000003 3355 #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift 15 3356 #define SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_W(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift) 3357 3358 /*define for bank_h field*/ 3359 #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset 5 3360 #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask 0x00000003 3361 #define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift 18 3362 #define SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_H(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift) 3363 3364 /*define for num_bank field*/ 3365 #define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset 5 3366 #define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask 0x00000003 3367 #define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift 21 3368 #define SDMA_PKT_WRITE_TILED_BC_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift) 3369 3370 /*define for mat_aspt field*/ 3371 #define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset 5 3372 #define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask 0x00000003 3373 #define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift 24 3374 #define SDMA_PKT_WRITE_TILED_BC_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift) 3375 3376 /*define for pipe_config field*/ 3377 #define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset 5 3378 #define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask 0x0000001F 3379 #define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift 26 3380 #define SDMA_PKT_WRITE_TILED_BC_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift) 3381 3382 /*define for DW_6 word*/ 3383 /*define for x field*/ 3384 #define SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset 6 3385 #define SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask 0x00003FFF 3386 #define SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift 0 3387 #define SDMA_PKT_WRITE_TILED_BC_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift) 3388 3389 /*define for y field*/ 3390 #define SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset 6 3391 #define SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask 0x00003FFF 3392 #define SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift 16 3393 #define SDMA_PKT_WRITE_TILED_BC_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift) 3394 3395 /*define for DW_7 word*/ 3396 /*define for z field*/ 3397 #define SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset 7 3398 #define SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask 0x000007FF 3399 #define SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift 0 3400 #define SDMA_PKT_WRITE_TILED_BC_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift) 3401 3402 /*define for sw field*/ 3403 #define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset 7 3404 #define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask 0x00000003 3405 #define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift 24 3406 #define SDMA_PKT_WRITE_TILED_BC_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift) 3407 3408 /*define for COUNT word*/ 3409 /*define for count field*/ 3410 #define SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset 8 3411 #define SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask 0x000FFFFF 3412 #define SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift 2 3413 #define SDMA_PKT_WRITE_TILED_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift) 3414 3415 /*define for DATA0 word*/ 3416 /*define for data0 field*/ 3417 #define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset 9 3418 #define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask 0xFFFFFFFF 3419 #define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift 0 3420 #define SDMA_PKT_WRITE_TILED_BC_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift) 3421 3422 3423 /* 3424 ** Definitions for SDMA_PKT_PTEPDE_COPY packet 3425 */ 3426 3427 /*define for HEADER word*/ 3428 /*define for op field*/ 3429 #define SDMA_PKT_PTEPDE_COPY_HEADER_op_offset 0 3430 #define SDMA_PKT_PTEPDE_COPY_HEADER_op_mask 0x000000FF 3431 #define SDMA_PKT_PTEPDE_COPY_HEADER_op_shift 0 3432 #define SDMA_PKT_PTEPDE_COPY_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_op_shift) 3433 3434 /*define for sub_op field*/ 3435 #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset 0 3436 #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask 0x000000FF 3437 #define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift 8 3438 #define SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift) 3439 3440 /*define for tmz field*/ 3441 #define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset 0 3442 #define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask 0x00000001 3443 #define SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift 18 3444 #define SDMA_PKT_PTEPDE_COPY_HEADER_TMZ(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift) 3445 3446 /*define for cpv field*/ 3447 #define SDMA_PKT_PTEPDE_COPY_HEADER_cpv_offset 0 3448 #define SDMA_PKT_PTEPDE_COPY_HEADER_cpv_mask 0x00000001 3449 #define SDMA_PKT_PTEPDE_COPY_HEADER_cpv_shift 28 3450 #define SDMA_PKT_PTEPDE_COPY_HEADER_CPV(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_cpv_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_cpv_shift) 3451 3452 /*define for ptepde_op field*/ 3453 #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset 0 3454 #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask 0x00000001 3455 #define SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift 31 3456 #define SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift) 3457 3458 /*define for SRC_ADDR_LO word*/ 3459 /*define for src_addr_31_0 field*/ 3460 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset 1 3461 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 3462 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift 0 3463 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift) 3464 3465 /*define for SRC_ADDR_HI word*/ 3466 /*define for src_addr_63_32 field*/ 3467 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset 2 3468 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 3469 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift 0 3470 #define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift) 3471 3472 /*define for DST_ADDR_LO word*/ 3473 /*define for dst_addr_31_0 field*/ 3474 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset 3 3475 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 3476 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift 0 3477 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift) 3478 3479 /*define for DST_ADDR_HI word*/ 3480 /*define for dst_addr_63_32 field*/ 3481 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset 4 3482 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 3483 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift 0 3484 #define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift) 3485 3486 /*define for MASK_DW0 word*/ 3487 /*define for mask_dw0 field*/ 3488 #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset 5 3489 #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask 0xFFFFFFFF 3490 #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift 0 3491 #define SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift) 3492 3493 /*define for MASK_DW1 word*/ 3494 /*define for mask_dw1 field*/ 3495 #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset 6 3496 #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask 0xFFFFFFFF 3497 #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift 0 3498 #define SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift) 3499 3500 /*define for COUNT word*/ 3501 /*define for count field*/ 3502 #define SDMA_PKT_PTEPDE_COPY_COUNT_count_offset 7 3503 #define SDMA_PKT_PTEPDE_COPY_COUNT_count_mask 0x0007FFFF 3504 #define SDMA_PKT_PTEPDE_COPY_COUNT_count_shift 0 3505 #define SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_count_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_count_shift) 3506 3507 /*define for dst_cache_policy field*/ 3508 #define SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_offset 7 3509 #define SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_mask 0x00000007 3510 #define SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_shift 22 3511 #define SDMA_PKT_PTEPDE_COPY_COUNT_DST_CACHE_POLICY(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_shift) 3512 3513 /*define for src_cache_policy field*/ 3514 #define SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_offset 7 3515 #define SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_mask 0x00000007 3516 #define SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_shift 29 3517 #define SDMA_PKT_PTEPDE_COPY_COUNT_SRC_CACHE_POLICY(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_shift) 3518 3519 3520 /* 3521 ** Definitions for SDMA_PKT_PTEPDE_COPY_BACKWARDS packet 3522 */ 3523 3524 /*define for HEADER word*/ 3525 /*define for op field*/ 3526 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset 0 3527 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask 0x000000FF 3528 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift 0 3529 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift) 3530 3531 /*define for sub_op field*/ 3532 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset 0 3533 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask 0x000000FF 3534 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift 8 3535 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift) 3536 3537 /*define for pte_size field*/ 3538 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset 0 3539 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask 0x00000003 3540 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift 28 3541 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift) 3542 3543 /*define for direction field*/ 3544 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset 0 3545 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask 0x00000001 3546 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift 30 3547 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift) 3548 3549 /*define for ptepde_op field*/ 3550 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset 0 3551 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask 0x00000001 3552 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift 31 3553 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift) 3554 3555 /*define for SRC_ADDR_LO word*/ 3556 /*define for src_addr_31_0 field*/ 3557 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset 1 3558 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 3559 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift 0 3560 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift) 3561 3562 /*define for SRC_ADDR_HI word*/ 3563 /*define for src_addr_63_32 field*/ 3564 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset 2 3565 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 3566 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift 0 3567 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift) 3568 3569 /*define for DST_ADDR_LO word*/ 3570 /*define for dst_addr_31_0 field*/ 3571 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset 3 3572 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 3573 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift 0 3574 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift) 3575 3576 /*define for DST_ADDR_HI word*/ 3577 /*define for dst_addr_63_32 field*/ 3578 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset 4 3579 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 3580 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift 0 3581 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift) 3582 3583 /*define for MASK_BIT_FOR_DW word*/ 3584 /*define for mask_first_xfer field*/ 3585 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset 5 3586 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask 0x000000FF 3587 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift 0 3588 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift) 3589 3590 /*define for mask_last_xfer field*/ 3591 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset 5 3592 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask 0x000000FF 3593 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift 8 3594 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift) 3595 3596 /*define for COUNT_IN_32B_XFER word*/ 3597 /*define for count field*/ 3598 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset 6 3599 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask 0x0001FFFF 3600 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift 0 3601 #define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift) 3602 3603 3604 /* 3605 ** Definitions for SDMA_PKT_PTEPDE_RMW packet 3606 */ 3607 3608 /*define for HEADER word*/ 3609 /*define for op field*/ 3610 #define SDMA_PKT_PTEPDE_RMW_HEADER_op_offset 0 3611 #define SDMA_PKT_PTEPDE_RMW_HEADER_op_mask 0x000000FF 3612 #define SDMA_PKT_PTEPDE_RMW_HEADER_op_shift 0 3613 #define SDMA_PKT_PTEPDE_RMW_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_op_shift) 3614 3615 /*define for sub_op field*/ 3616 #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset 0 3617 #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask 0x000000FF 3618 #define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift 8 3619 #define SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift) 3620 3621 /*define for mtype field*/ 3622 #define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset 0 3623 #define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask 0x00000007 3624 #define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift 16 3625 #define SDMA_PKT_PTEPDE_RMW_HEADER_MTYPE(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift) 3626 3627 /*define for gcc field*/ 3628 #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset 0 3629 #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask 0x00000001 3630 #define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift 19 3631 #define SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift) 3632 3633 /*define for sys field*/ 3634 #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset 0 3635 #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask 0x00000001 3636 #define SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift 20 3637 #define SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift) 3638 3639 /*define for snp field*/ 3640 #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset 0 3641 #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask 0x00000001 3642 #define SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift 22 3643 #define SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift) 3644 3645 /*define for gpa field*/ 3646 #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset 0 3647 #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask 0x00000001 3648 #define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift 23 3649 #define SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift) 3650 3651 /*define for l2_policy field*/ 3652 #define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset 0 3653 #define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask 0x00000003 3654 #define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift 24 3655 #define SDMA_PKT_PTEPDE_RMW_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift) 3656 3657 /*define for llc_policy field*/ 3658 #define SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_offset 0 3659 #define SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_mask 0x00000001 3660 #define SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_shift 26 3661 #define SDMA_PKT_PTEPDE_RMW_HEADER_LLC_POLICY(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_shift) 3662 3663 /*define for cpv field*/ 3664 #define SDMA_PKT_PTEPDE_RMW_HEADER_cpv_offset 0 3665 #define SDMA_PKT_PTEPDE_RMW_HEADER_cpv_mask 0x00000001 3666 #define SDMA_PKT_PTEPDE_RMW_HEADER_cpv_shift 28 3667 #define SDMA_PKT_PTEPDE_RMW_HEADER_CPV(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_cpv_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_cpv_shift) 3668 3669 /*define for ADDR_LO word*/ 3670 /*define for addr_31_0 field*/ 3671 #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset 1 3672 #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 3673 #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift 0 3674 #define SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift) 3675 3676 /*define for ADDR_HI word*/ 3677 /*define for addr_63_32 field*/ 3678 #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset 2 3679 #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 3680 #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift 0 3681 #define SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift) 3682 3683 /*define for MASK_LO word*/ 3684 /*define for mask_31_0 field*/ 3685 #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset 3 3686 #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask 0xFFFFFFFF 3687 #define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift 0 3688 #define SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask) << SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift) 3689 3690 /*define for MASK_HI word*/ 3691 /*define for mask_63_32 field*/ 3692 #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset 4 3693 #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask 0xFFFFFFFF 3694 #define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift 0 3695 #define SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask) << SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift) 3696 3697 /*define for VALUE_LO word*/ 3698 /*define for value_31_0 field*/ 3699 #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset 5 3700 #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask 0xFFFFFFFF 3701 #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift 0 3702 #define SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift) 3703 3704 /*define for VALUE_HI word*/ 3705 /*define for value_63_32 field*/ 3706 #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset 6 3707 #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask 0xFFFFFFFF 3708 #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift 0 3709 #define SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift) 3710 3711 /*define for COUNT word*/ 3712 /*define for num_of_pte field*/ 3713 #define SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_offset 7 3714 #define SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_mask 0xFFFFFFFF 3715 #define SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_shift 0 3716 #define SDMA_PKT_PTEPDE_RMW_COUNT_NUM_OF_PTE(x) (((x) & SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_mask) << SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_shift) 3717 3718 3719 /* 3720 ** Definitions for SDMA_PKT_REGISTER_RMW packet 3721 */ 3722 3723 /*define for HEADER word*/ 3724 /*define for op field*/ 3725 #define SDMA_PKT_REGISTER_RMW_HEADER_op_offset 0 3726 #define SDMA_PKT_REGISTER_RMW_HEADER_op_mask 0x000000FF 3727 #define SDMA_PKT_REGISTER_RMW_HEADER_op_shift 0 3728 #define SDMA_PKT_REGISTER_RMW_HEADER_OP(x) (((x) & SDMA_PKT_REGISTER_RMW_HEADER_op_mask) << SDMA_PKT_REGISTER_RMW_HEADER_op_shift) 3729 3730 /*define for sub_op field*/ 3731 #define SDMA_PKT_REGISTER_RMW_HEADER_sub_op_offset 0 3732 #define SDMA_PKT_REGISTER_RMW_HEADER_sub_op_mask 0x000000FF 3733 #define SDMA_PKT_REGISTER_RMW_HEADER_sub_op_shift 8 3734 #define SDMA_PKT_REGISTER_RMW_HEADER_SUB_OP(x) (((x) & SDMA_PKT_REGISTER_RMW_HEADER_sub_op_mask) << SDMA_PKT_REGISTER_RMW_HEADER_sub_op_shift) 3735 3736 /*define for ADDR word*/ 3737 /*define for addr field*/ 3738 #define SDMA_PKT_REGISTER_RMW_ADDR_addr_offset 1 3739 #define SDMA_PKT_REGISTER_RMW_ADDR_addr_mask 0x000FFFFF 3740 #define SDMA_PKT_REGISTER_RMW_ADDR_addr_shift 0 3741 #define SDMA_PKT_REGISTER_RMW_ADDR_ADDR(x) (((x) & SDMA_PKT_REGISTER_RMW_ADDR_addr_mask) << SDMA_PKT_REGISTER_RMW_ADDR_addr_shift) 3742 3743 /*define for aperture_id field*/ 3744 #define SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_offset 1 3745 #define SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_mask 0x00000FFF 3746 #define SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_shift 20 3747 #define SDMA_PKT_REGISTER_RMW_ADDR_APERTURE_ID(x) (((x) & SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_mask) << SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_shift) 3748 3749 /*define for MASK word*/ 3750 /*define for mask field*/ 3751 #define SDMA_PKT_REGISTER_RMW_MASK_mask_offset 2 3752 #define SDMA_PKT_REGISTER_RMW_MASK_mask_mask 0xFFFFFFFF 3753 #define SDMA_PKT_REGISTER_RMW_MASK_mask_shift 0 3754 #define SDMA_PKT_REGISTER_RMW_MASK_MASK(x) (((x) & SDMA_PKT_REGISTER_RMW_MASK_mask_mask) << SDMA_PKT_REGISTER_RMW_MASK_mask_shift) 3755 3756 /*define for VALUE word*/ 3757 /*define for value field*/ 3758 #define SDMA_PKT_REGISTER_RMW_VALUE_value_offset 3 3759 #define SDMA_PKT_REGISTER_RMW_VALUE_value_mask 0xFFFFFFFF 3760 #define SDMA_PKT_REGISTER_RMW_VALUE_value_shift 0 3761 #define SDMA_PKT_REGISTER_RMW_VALUE_VALUE(x) (((x) & SDMA_PKT_REGISTER_RMW_VALUE_value_mask) << SDMA_PKT_REGISTER_RMW_VALUE_value_shift) 3762 3763 /*define for MISC word*/ 3764 /*define for stride field*/ 3765 #define SDMA_PKT_REGISTER_RMW_MISC_stride_offset 4 3766 #define SDMA_PKT_REGISTER_RMW_MISC_stride_mask 0x000FFFFF 3767 #define SDMA_PKT_REGISTER_RMW_MISC_stride_shift 0 3768 #define SDMA_PKT_REGISTER_RMW_MISC_STRIDE(x) (((x) & SDMA_PKT_REGISTER_RMW_MISC_stride_mask) << SDMA_PKT_REGISTER_RMW_MISC_stride_shift) 3769 3770 /*define for num_of_reg field*/ 3771 #define SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_offset 4 3772 #define SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_mask 0x00000FFF 3773 #define SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_shift 20 3774 #define SDMA_PKT_REGISTER_RMW_MISC_NUM_OF_REG(x) (((x) & SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_mask) << SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_shift) 3775 3776 3777 /* 3778 ** Definitions for SDMA_PKT_WRITE_INCR packet 3779 */ 3780 3781 /*define for HEADER word*/ 3782 /*define for op field*/ 3783 #define SDMA_PKT_WRITE_INCR_HEADER_op_offset 0 3784 #define SDMA_PKT_WRITE_INCR_HEADER_op_mask 0x000000FF 3785 #define SDMA_PKT_WRITE_INCR_HEADER_op_shift 0 3786 #define SDMA_PKT_WRITE_INCR_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift) 3787 3788 /*define for sub_op field*/ 3789 #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 0 3790 #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask 0x000000FF 3791 #define SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift 8 3792 #define SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift) 3793 3794 /*define for cache_policy field*/ 3795 #define SDMA_PKT_WRITE_INCR_HEADER_cache_policy_offset 0 3796 #define SDMA_PKT_WRITE_INCR_HEADER_cache_policy_mask 0x00000007 3797 #define SDMA_PKT_WRITE_INCR_HEADER_cache_policy_shift 24 3798 #define SDMA_PKT_WRITE_INCR_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_cache_policy_mask) << SDMA_PKT_WRITE_INCR_HEADER_cache_policy_shift) 3799 3800 /*define for cpv field*/ 3801 #define SDMA_PKT_WRITE_INCR_HEADER_cpv_offset 0 3802 #define SDMA_PKT_WRITE_INCR_HEADER_cpv_mask 0x00000001 3803 #define SDMA_PKT_WRITE_INCR_HEADER_cpv_shift 28 3804 #define SDMA_PKT_WRITE_INCR_HEADER_CPV(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_cpv_mask) << SDMA_PKT_WRITE_INCR_HEADER_cpv_shift) 3805 3806 /*define for DST_ADDR_LO word*/ 3807 /*define for dst_addr_31_0 field*/ 3808 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset 1 3809 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 3810 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift 0 3811 #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift) 3812 3813 /*define for DST_ADDR_HI word*/ 3814 /*define for dst_addr_63_32 field*/ 3815 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset 2 3816 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 3817 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift 0 3818 #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift) 3819 3820 /*define for MASK_DW0 word*/ 3821 /*define for mask_dw0 field*/ 3822 #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset 3 3823 #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask 0xFFFFFFFF 3824 #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift 0 3825 #define SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift) 3826 3827 /*define for MASK_DW1 word*/ 3828 /*define for mask_dw1 field*/ 3829 #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset 4 3830 #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask 0xFFFFFFFF 3831 #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift 0 3832 #define SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift) 3833 3834 /*define for INIT_DW0 word*/ 3835 /*define for init_dw0 field*/ 3836 #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset 5 3837 #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask 0xFFFFFFFF 3838 #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift 0 3839 #define SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift) 3840 3841 /*define for INIT_DW1 word*/ 3842 /*define for init_dw1 field*/ 3843 #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset 6 3844 #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask 0xFFFFFFFF 3845 #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift 0 3846 #define SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift) 3847 3848 /*define for INCR_DW0 word*/ 3849 /*define for incr_dw0 field*/ 3850 #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset 7 3851 #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask 0xFFFFFFFF 3852 #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift 0 3853 #define SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift) 3854 3855 /*define for INCR_DW1 word*/ 3856 /*define for incr_dw1 field*/ 3857 #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset 8 3858 #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask 0xFFFFFFFF 3859 #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift 0 3860 #define SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift) 3861 3862 /*define for COUNT word*/ 3863 /*define for count field*/ 3864 #define SDMA_PKT_WRITE_INCR_COUNT_count_offset 9 3865 #define SDMA_PKT_WRITE_INCR_COUNT_count_mask 0x0007FFFF 3866 #define SDMA_PKT_WRITE_INCR_COUNT_count_shift 0 3867 #define SDMA_PKT_WRITE_INCR_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift) 3868 3869 3870 /* 3871 ** Definitions for SDMA_PKT_INDIRECT packet 3872 */ 3873 3874 /*define for HEADER word*/ 3875 /*define for op field*/ 3876 #define SDMA_PKT_INDIRECT_HEADER_op_offset 0 3877 #define SDMA_PKT_INDIRECT_HEADER_op_mask 0x000000FF 3878 #define SDMA_PKT_INDIRECT_HEADER_op_shift 0 3879 #define SDMA_PKT_INDIRECT_HEADER_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift) 3880 3881 /*define for sub_op field*/ 3882 #define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 0 3883 #define SDMA_PKT_INDIRECT_HEADER_sub_op_mask 0x000000FF 3884 #define SDMA_PKT_INDIRECT_HEADER_sub_op_shift 8 3885 #define SDMA_PKT_INDIRECT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift) 3886 3887 /*define for vmid field*/ 3888 #define SDMA_PKT_INDIRECT_HEADER_vmid_offset 0 3889 #define SDMA_PKT_INDIRECT_HEADER_vmid_mask 0x0000000F 3890 #define SDMA_PKT_INDIRECT_HEADER_vmid_shift 16 3891 #define SDMA_PKT_INDIRECT_HEADER_VMID(x) (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift) 3892 3893 /*define for priv field*/ 3894 #define SDMA_PKT_INDIRECT_HEADER_priv_offset 0 3895 #define SDMA_PKT_INDIRECT_HEADER_priv_mask 0x00000001 3896 #define SDMA_PKT_INDIRECT_HEADER_priv_shift 31 3897 #define SDMA_PKT_INDIRECT_HEADER_PRIV(x) (((x) & SDMA_PKT_INDIRECT_HEADER_priv_mask) << SDMA_PKT_INDIRECT_HEADER_priv_shift) 3898 3899 /*define for BASE_LO word*/ 3900 /*define for ib_base_31_0 field*/ 3901 #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset 1 3902 #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask 0xFFFFFFFF 3903 #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift 0 3904 #define SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x) (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift) 3905 3906 /*define for BASE_HI word*/ 3907 /*define for ib_base_63_32 field*/ 3908 #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset 2 3909 #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask 0xFFFFFFFF 3910 #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift 0 3911 #define SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x) (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift) 3912 3913 /*define for IB_SIZE word*/ 3914 /*define for ib_size field*/ 3915 #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset 3 3916 #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask 0x000FFFFF 3917 #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift 0 3918 #define SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x) (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift) 3919 3920 /*define for CSA_ADDR_LO word*/ 3921 /*define for csa_addr_31_0 field*/ 3922 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset 4 3923 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask 0xFFFFFFFF 3924 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift 0 3925 #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift) 3926 3927 /*define for CSA_ADDR_HI word*/ 3928 /*define for csa_addr_63_32 field*/ 3929 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset 5 3930 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask 0xFFFFFFFF 3931 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift 0 3932 #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift) 3933 3934 3935 /* 3936 ** Definitions for SDMA_PKT_SEMAPHORE packet 3937 */ 3938 3939 /*define for HEADER word*/ 3940 /*define for op field*/ 3941 #define SDMA_PKT_SEMAPHORE_HEADER_op_offset 0 3942 #define SDMA_PKT_SEMAPHORE_HEADER_op_mask 0x000000FF 3943 #define SDMA_PKT_SEMAPHORE_HEADER_op_shift 0 3944 #define SDMA_PKT_SEMAPHORE_HEADER_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift) 3945 3946 /*define for sub_op field*/ 3947 #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 0 3948 #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask 0x000000FF 3949 #define SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift 8 3950 #define SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift) 3951 3952 /*define for write_one field*/ 3953 #define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 0 3954 #define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask 0x00000001 3955 #define SDMA_PKT_SEMAPHORE_HEADER_write_one_shift 29 3956 #define SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift) 3957 3958 /*define for signal field*/ 3959 #define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 0 3960 #define SDMA_PKT_SEMAPHORE_HEADER_signal_mask 0x00000001 3961 #define SDMA_PKT_SEMAPHORE_HEADER_signal_shift 30 3962 #define SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift) 3963 3964 /*define for mailbox field*/ 3965 #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 0 3966 #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask 0x00000001 3967 #define SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift 31 3968 #define SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift) 3969 3970 /*define for ADDR_LO word*/ 3971 /*define for addr_31_0 field*/ 3972 #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset 1 3973 #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 3974 #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift 0 3975 #define SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift) 3976 3977 /*define for ADDR_HI word*/ 3978 /*define for addr_63_32 field*/ 3979 #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset 2 3980 #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 3981 #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift 0 3982 #define SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift) 3983 3984 3985 /* 3986 ** Definitions for SDMA_PKT_MEM_INCR packet 3987 */ 3988 3989 /*define for HEADER word*/ 3990 /*define for op field*/ 3991 #define SDMA_PKT_MEM_INCR_HEADER_op_offset 0 3992 #define SDMA_PKT_MEM_INCR_HEADER_op_mask 0x000000FF 3993 #define SDMA_PKT_MEM_INCR_HEADER_op_shift 0 3994 #define SDMA_PKT_MEM_INCR_HEADER_OP(x) (((x) & SDMA_PKT_MEM_INCR_HEADER_op_mask) << SDMA_PKT_MEM_INCR_HEADER_op_shift) 3995 3996 /*define for sub_op field*/ 3997 #define SDMA_PKT_MEM_INCR_HEADER_sub_op_offset 0 3998 #define SDMA_PKT_MEM_INCR_HEADER_sub_op_mask 0x000000FF 3999 #define SDMA_PKT_MEM_INCR_HEADER_sub_op_shift 8 4000 #define SDMA_PKT_MEM_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_MEM_INCR_HEADER_sub_op_mask) << SDMA_PKT_MEM_INCR_HEADER_sub_op_shift) 4001 4002 /*define for l2_policy field*/ 4003 #define SDMA_PKT_MEM_INCR_HEADER_l2_policy_offset 0 4004 #define SDMA_PKT_MEM_INCR_HEADER_l2_policy_mask 0x00000003 4005 #define SDMA_PKT_MEM_INCR_HEADER_l2_policy_shift 24 4006 #define SDMA_PKT_MEM_INCR_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_MEM_INCR_HEADER_l2_policy_mask) << SDMA_PKT_MEM_INCR_HEADER_l2_policy_shift) 4007 4008 /*define for llc_policy field*/ 4009 #define SDMA_PKT_MEM_INCR_HEADER_llc_policy_offset 0 4010 #define SDMA_PKT_MEM_INCR_HEADER_llc_policy_mask 0x00000001 4011 #define SDMA_PKT_MEM_INCR_HEADER_llc_policy_shift 26 4012 #define SDMA_PKT_MEM_INCR_HEADER_LLC_POLICY(x) (((x) & SDMA_PKT_MEM_INCR_HEADER_llc_policy_mask) << SDMA_PKT_MEM_INCR_HEADER_llc_policy_shift) 4013 4014 /*define for cpv field*/ 4015 #define SDMA_PKT_MEM_INCR_HEADER_cpv_offset 0 4016 #define SDMA_PKT_MEM_INCR_HEADER_cpv_mask 0x00000001 4017 #define SDMA_PKT_MEM_INCR_HEADER_cpv_shift 28 4018 #define SDMA_PKT_MEM_INCR_HEADER_CPV(x) (((x) & SDMA_PKT_MEM_INCR_HEADER_cpv_mask) << SDMA_PKT_MEM_INCR_HEADER_cpv_shift) 4019 4020 /*define for ADDR_LO word*/ 4021 /*define for addr_31_0 field*/ 4022 #define SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_offset 1 4023 #define SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 4024 #define SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_shift 0 4025 #define SDMA_PKT_MEM_INCR_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_mask) << SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_shift) 4026 4027 /*define for ADDR_HI word*/ 4028 /*define for addr_63_32 field*/ 4029 #define SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_offset 2 4030 #define SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 4031 #define SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_shift 0 4032 #define SDMA_PKT_MEM_INCR_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_mask) << SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_shift) 4033 4034 4035 /* 4036 ** Definitions for SDMA_PKT_VM_INVALIDATION packet 4037 */ 4038 4039 /*define for HEADER word*/ 4040 /*define for op field*/ 4041 #define SDMA_PKT_VM_INVALIDATION_HEADER_op_offset 0 4042 #define SDMA_PKT_VM_INVALIDATION_HEADER_op_mask 0x000000FF 4043 #define SDMA_PKT_VM_INVALIDATION_HEADER_op_shift 0 4044 #define SDMA_PKT_VM_INVALIDATION_HEADER_OP(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_op_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_op_shift) 4045 4046 /*define for sub_op field*/ 4047 #define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset 0 4048 #define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask 0x000000FF 4049 #define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift 8 4050 #define SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift) 4051 4052 /*define for gfx_eng_id field*/ 4053 #define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_offset 0 4054 #define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask 0x0000001F 4055 #define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift 16 4056 #define SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift) 4057 4058 /*define for mm_eng_id field*/ 4059 #define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_offset 0 4060 #define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask 0x0000001F 4061 #define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift 24 4062 #define SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift) 4063 4064 /*define for INVALIDATEREQ word*/ 4065 /*define for invalidatereq field*/ 4066 #define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset 1 4067 #define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask 0xFFFFFFFF 4068 #define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift 0 4069 #define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_INVALIDATEREQ(x) (((x) & SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask) << SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift) 4070 4071 /*define for ADDRESSRANGELO word*/ 4072 /*define for addressrangelo field*/ 4073 #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset 2 4074 #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask 0xFFFFFFFF 4075 #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift 0 4076 #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_ADDRESSRANGELO(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift) 4077 4078 /*define for ADDRESSRANGEHI word*/ 4079 /*define for invalidateack field*/ 4080 #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset 3 4081 #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask 0x0000FFFF 4082 #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift 0 4083 #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift) 4084 4085 /*define for addressrangehi field*/ 4086 #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset 3 4087 #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask 0x0000001F 4088 #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift 16 4089 #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift) 4090 4091 /*define for reserved field*/ 4092 #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset 3 4093 #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask 0x000001FF 4094 #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift 23 4095 #define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_RESERVED(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift) 4096 4097 4098 /* 4099 ** Definitions for SDMA_PKT_FENCE packet 4100 */ 4101 4102 /*define for HEADER word*/ 4103 /*define for op field*/ 4104 #define SDMA_PKT_FENCE_HEADER_op_offset 0 4105 #define SDMA_PKT_FENCE_HEADER_op_mask 0x000000FF 4106 #define SDMA_PKT_FENCE_HEADER_op_shift 0 4107 #define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift) 4108 4109 /*define for sub_op field*/ 4110 #define SDMA_PKT_FENCE_HEADER_sub_op_offset 0 4111 #define SDMA_PKT_FENCE_HEADER_sub_op_mask 0x000000FF 4112 #define SDMA_PKT_FENCE_HEADER_sub_op_shift 8 4113 #define SDMA_PKT_FENCE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift) 4114 4115 /*define for mtype field*/ 4116 #define SDMA_PKT_FENCE_HEADER_mtype_offset 0 4117 #define SDMA_PKT_FENCE_HEADER_mtype_mask 0x00000007 4118 #define SDMA_PKT_FENCE_HEADER_mtype_shift 16 4119 #define SDMA_PKT_FENCE_HEADER_MTYPE(x) (((x) & SDMA_PKT_FENCE_HEADER_mtype_mask) << SDMA_PKT_FENCE_HEADER_mtype_shift) 4120 4121 /*define for gcc field*/ 4122 #define SDMA_PKT_FENCE_HEADER_gcc_offset 0 4123 #define SDMA_PKT_FENCE_HEADER_gcc_mask 0x00000001 4124 #define SDMA_PKT_FENCE_HEADER_gcc_shift 19 4125 #define SDMA_PKT_FENCE_HEADER_GCC(x) (((x) & SDMA_PKT_FENCE_HEADER_gcc_mask) << SDMA_PKT_FENCE_HEADER_gcc_shift) 4126 4127 /*define for sys field*/ 4128 #define SDMA_PKT_FENCE_HEADER_sys_offset 0 4129 #define SDMA_PKT_FENCE_HEADER_sys_mask 0x00000001 4130 #define SDMA_PKT_FENCE_HEADER_sys_shift 20 4131 #define SDMA_PKT_FENCE_HEADER_SYS(x) (((x) & SDMA_PKT_FENCE_HEADER_sys_mask) << SDMA_PKT_FENCE_HEADER_sys_shift) 4132 4133 /*define for snp field*/ 4134 #define SDMA_PKT_FENCE_HEADER_snp_offset 0 4135 #define SDMA_PKT_FENCE_HEADER_snp_mask 0x00000001 4136 #define SDMA_PKT_FENCE_HEADER_snp_shift 22 4137 #define SDMA_PKT_FENCE_HEADER_SNP(x) (((x) & SDMA_PKT_FENCE_HEADER_snp_mask) << SDMA_PKT_FENCE_HEADER_snp_shift) 4138 4139 /*define for gpa field*/ 4140 #define SDMA_PKT_FENCE_HEADER_gpa_offset 0 4141 #define SDMA_PKT_FENCE_HEADER_gpa_mask 0x00000001 4142 #define SDMA_PKT_FENCE_HEADER_gpa_shift 23 4143 #define SDMA_PKT_FENCE_HEADER_GPA(x) (((x) & SDMA_PKT_FENCE_HEADER_gpa_mask) << SDMA_PKT_FENCE_HEADER_gpa_shift) 4144 4145 /*define for l2_policy field*/ 4146 #define SDMA_PKT_FENCE_HEADER_l2_policy_offset 0 4147 #define SDMA_PKT_FENCE_HEADER_l2_policy_mask 0x00000003 4148 #define SDMA_PKT_FENCE_HEADER_l2_policy_shift 24 4149 #define SDMA_PKT_FENCE_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_FENCE_HEADER_l2_policy_mask) << SDMA_PKT_FENCE_HEADER_l2_policy_shift) 4150 4151 /*define for llc_policy field*/ 4152 #define SDMA_PKT_FENCE_HEADER_llc_policy_offset 0 4153 #define SDMA_PKT_FENCE_HEADER_llc_policy_mask 0x00000001 4154 #define SDMA_PKT_FENCE_HEADER_llc_policy_shift 26 4155 #define SDMA_PKT_FENCE_HEADER_LLC_POLICY(x) (((x) & SDMA_PKT_FENCE_HEADER_llc_policy_mask) << SDMA_PKT_FENCE_HEADER_llc_policy_shift) 4156 4157 /*define for cpv field*/ 4158 #define SDMA_PKT_FENCE_HEADER_cpv_offset 0 4159 #define SDMA_PKT_FENCE_HEADER_cpv_mask 0x00000001 4160 #define SDMA_PKT_FENCE_HEADER_cpv_shift 28 4161 #define SDMA_PKT_FENCE_HEADER_CPV(x) (((x) & SDMA_PKT_FENCE_HEADER_cpv_mask) << SDMA_PKT_FENCE_HEADER_cpv_shift) 4162 4163 /*define for ADDR_LO word*/ 4164 /*define for addr_31_0 field*/ 4165 #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset 1 4166 #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 4167 #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift 0 4168 #define SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift) 4169 4170 /*define for ADDR_HI word*/ 4171 /*define for addr_63_32 field*/ 4172 #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset 2 4173 #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 4174 #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift 0 4175 #define SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift) 4176 4177 /*define for DATA word*/ 4178 /*define for data field*/ 4179 #define SDMA_PKT_FENCE_DATA_data_offset 3 4180 #define SDMA_PKT_FENCE_DATA_data_mask 0xFFFFFFFF 4181 #define SDMA_PKT_FENCE_DATA_data_shift 0 4182 #define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift) 4183 4184 4185 /* 4186 ** Definitions for SDMA_PKT_SRBM_WRITE packet 4187 */ 4188 4189 /*define for HEADER word*/ 4190 /*define for op field*/ 4191 #define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 0 4192 #define SDMA_PKT_SRBM_WRITE_HEADER_op_mask 0x000000FF 4193 #define SDMA_PKT_SRBM_WRITE_HEADER_op_shift 0 4194 #define SDMA_PKT_SRBM_WRITE_HEADER_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift) 4195 4196 /*define for sub_op field*/ 4197 #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 0 4198 #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask 0x000000FF 4199 #define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift 8 4200 #define SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift) 4201 4202 /*define for byte_en field*/ 4203 #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 0 4204 #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask 0x0000000F 4205 #define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift 28 4206 #define SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift) 4207 4208 /*define for ADDR word*/ 4209 /*define for addr field*/ 4210 #define SDMA_PKT_SRBM_WRITE_ADDR_addr_offset 1 4211 #define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask 0x0003FFFF 4212 #define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift 0 4213 #define SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift) 4214 4215 /*define for apertureid field*/ 4216 #define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset 1 4217 #define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask 0x00000FFF 4218 #define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift 20 4219 #define SDMA_PKT_SRBM_WRITE_ADDR_APERTUREID(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask) << SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift) 4220 4221 /*define for DATA word*/ 4222 /*define for data field*/ 4223 #define SDMA_PKT_SRBM_WRITE_DATA_data_offset 2 4224 #define SDMA_PKT_SRBM_WRITE_DATA_data_mask 0xFFFFFFFF 4225 #define SDMA_PKT_SRBM_WRITE_DATA_data_shift 0 4226 #define SDMA_PKT_SRBM_WRITE_DATA_DATA(x) (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift) 4227 4228 4229 /* 4230 ** Definitions for SDMA_PKT_PRE_EXE packet 4231 */ 4232 4233 /*define for HEADER word*/ 4234 /*define for op field*/ 4235 #define SDMA_PKT_PRE_EXE_HEADER_op_offset 0 4236 #define SDMA_PKT_PRE_EXE_HEADER_op_mask 0x000000FF 4237 #define SDMA_PKT_PRE_EXE_HEADER_op_shift 0 4238 #define SDMA_PKT_PRE_EXE_HEADER_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift) 4239 4240 /*define for sub_op field*/ 4241 #define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 0 4242 #define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask 0x000000FF 4243 #define SDMA_PKT_PRE_EXE_HEADER_sub_op_shift 8 4244 #define SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift) 4245 4246 /*define for dev_sel field*/ 4247 #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 0 4248 #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask 0x000000FF 4249 #define SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift 16 4250 #define SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift) 4251 4252 /*define for EXEC_COUNT word*/ 4253 /*define for exec_count field*/ 4254 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset 1 4255 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF 4256 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift 0 4257 #define SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift) 4258 4259 4260 /* 4261 ** Definitions for SDMA_PKT_COND_EXE packet 4262 */ 4263 4264 /*define for HEADER word*/ 4265 /*define for op field*/ 4266 #define SDMA_PKT_COND_EXE_HEADER_op_offset 0 4267 #define SDMA_PKT_COND_EXE_HEADER_op_mask 0x000000FF 4268 #define SDMA_PKT_COND_EXE_HEADER_op_shift 0 4269 #define SDMA_PKT_COND_EXE_HEADER_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift) 4270 4271 /*define for sub_op field*/ 4272 #define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 0 4273 #define SDMA_PKT_COND_EXE_HEADER_sub_op_mask 0x000000FF 4274 #define SDMA_PKT_COND_EXE_HEADER_sub_op_shift 8 4275 #define SDMA_PKT_COND_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift) 4276 4277 /*define for cache_policy field*/ 4278 #define SDMA_PKT_COND_EXE_HEADER_cache_policy_offset 0 4279 #define SDMA_PKT_COND_EXE_HEADER_cache_policy_mask 0x00000007 4280 #define SDMA_PKT_COND_EXE_HEADER_cache_policy_shift 24 4281 #define SDMA_PKT_COND_EXE_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_COND_EXE_HEADER_cache_policy_mask) << SDMA_PKT_COND_EXE_HEADER_cache_policy_shift) 4282 4283 /*define for cpv field*/ 4284 #define SDMA_PKT_COND_EXE_HEADER_cpv_offset 0 4285 #define SDMA_PKT_COND_EXE_HEADER_cpv_mask 0x00000001 4286 #define SDMA_PKT_COND_EXE_HEADER_cpv_shift 28 4287 #define SDMA_PKT_COND_EXE_HEADER_CPV(x) (((x) & SDMA_PKT_COND_EXE_HEADER_cpv_mask) << SDMA_PKT_COND_EXE_HEADER_cpv_shift) 4288 4289 /*define for ADDR_LO word*/ 4290 /*define for addr_31_0 field*/ 4291 #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset 1 4292 #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 4293 #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift 0 4294 #define SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift) 4295 4296 /*define for ADDR_HI word*/ 4297 /*define for addr_63_32 field*/ 4298 #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset 2 4299 #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 4300 #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift 0 4301 #define SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift) 4302 4303 /*define for REFERENCE word*/ 4304 /*define for reference field*/ 4305 #define SDMA_PKT_COND_EXE_REFERENCE_reference_offset 3 4306 #define SDMA_PKT_COND_EXE_REFERENCE_reference_mask 0xFFFFFFFF 4307 #define SDMA_PKT_COND_EXE_REFERENCE_reference_shift 0 4308 #define SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x) (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift) 4309 4310 /*define for EXEC_COUNT word*/ 4311 /*define for exec_count field*/ 4312 #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset 4 4313 #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF 4314 #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift 0 4315 #define SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift) 4316 4317 4318 /* 4319 ** Definitions for SDMA_PKT_CONSTANT_FILL packet 4320 */ 4321 4322 /*define for HEADER word*/ 4323 /*define for op field*/ 4324 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 0 4325 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask 0x000000FF 4326 #define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift 0 4327 #define SDMA_PKT_CONSTANT_FILL_HEADER_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift) 4328 4329 /*define for sub_op field*/ 4330 #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 0 4331 #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask 0x000000FF 4332 #define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift 8 4333 #define SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift) 4334 4335 /*define for sw field*/ 4336 #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 0 4337 #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask 0x00000003 4338 #define SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift 16 4339 #define SDMA_PKT_CONSTANT_FILL_HEADER_SW(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift) 4340 4341 /*define for cache_policy field*/ 4342 #define SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_offset 0 4343 #define SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_mask 0x00000007 4344 #define SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_shift 24 4345 #define SDMA_PKT_CONSTANT_FILL_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_shift) 4346 4347 /*define for cpv field*/ 4348 #define SDMA_PKT_CONSTANT_FILL_HEADER_cpv_offset 0 4349 #define SDMA_PKT_CONSTANT_FILL_HEADER_cpv_mask 0x00000001 4350 #define SDMA_PKT_CONSTANT_FILL_HEADER_cpv_shift 28 4351 #define SDMA_PKT_CONSTANT_FILL_HEADER_CPV(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_cpv_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_cpv_shift) 4352 4353 /*define for fillsize field*/ 4354 #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 0 4355 #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask 0x00000003 4356 #define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift 30 4357 #define SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift) 4358 4359 /*define for DST_ADDR_LO word*/ 4360 /*define for dst_addr_31_0 field*/ 4361 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset 1 4362 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 4363 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift 0 4364 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift) 4365 4366 /*define for DST_ADDR_HI word*/ 4367 /*define for dst_addr_63_32 field*/ 4368 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset 2 4369 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 4370 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift 0 4371 #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift) 4372 4373 /*define for DATA word*/ 4374 /*define for src_data_31_0 field*/ 4375 #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset 3 4376 #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask 0xFFFFFFFF 4377 #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift 0 4378 #define SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift) 4379 4380 /*define for COUNT word*/ 4381 /*define for count field*/ 4382 #define SDMA_PKT_CONSTANT_FILL_COUNT_count_offset 4 4383 #define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask 0x3FFFFFFF 4384 #define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift 0 4385 #define SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x) (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift) 4386 4387 4388 /* 4389 ** Definitions for SDMA_PKT_DATA_FILL_MULTI packet 4390 */ 4391 4392 /*define for HEADER word*/ 4393 /*define for op field*/ 4394 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset 0 4395 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask 0x000000FF 4396 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift 0 4397 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift) 4398 4399 /*define for sub_op field*/ 4400 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset 0 4401 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask 0x000000FF 4402 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift 8 4403 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift) 4404 4405 /*define for cache_policy field*/ 4406 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_offset 0 4407 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_mask 0x00000007 4408 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_shift 24 4409 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_shift) 4410 4411 /*define for cpv field*/ 4412 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_offset 0 4413 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_mask 0x00000001 4414 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_shift 28 4415 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_CPV(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_shift) 4416 4417 /*define for memlog_clr field*/ 4418 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset 0 4419 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask 0x00000001 4420 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift 31 4421 #define SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift) 4422 4423 /*define for BYTE_STRIDE word*/ 4424 /*define for byte_stride field*/ 4425 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset 1 4426 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask 0xFFFFFFFF 4427 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift 0 4428 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift) 4429 4430 /*define for DMA_COUNT word*/ 4431 /*define for dma_count field*/ 4432 #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset 2 4433 #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask 0xFFFFFFFF 4434 #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift 0 4435 #define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask) << SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift) 4436 4437 /*define for DST_ADDR_LO word*/ 4438 /*define for dst_addr_31_0 field*/ 4439 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset 3 4440 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 4441 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift 0 4442 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift) 4443 4444 /*define for DST_ADDR_HI word*/ 4445 /*define for dst_addr_63_32 field*/ 4446 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset 4 4447 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 4448 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift 0 4449 #define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift) 4450 4451 /*define for BYTE_COUNT word*/ 4452 /*define for count field*/ 4453 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset 5 4454 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask 0x03FFFFFF 4455 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift 0 4456 #define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift) 4457 4458 4459 /* 4460 ** Definitions for SDMA_PKT_POLL_REGMEM packet 4461 */ 4462 4463 /*define for HEADER word*/ 4464 /*define for op field*/ 4465 #define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 0 4466 #define SDMA_PKT_POLL_REGMEM_HEADER_op_mask 0x000000FF 4467 #define SDMA_PKT_POLL_REGMEM_HEADER_op_shift 0 4468 #define SDMA_PKT_POLL_REGMEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift) 4469 4470 /*define for sub_op field*/ 4471 #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 0 4472 #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask 0x000000FF 4473 #define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift 8 4474 #define SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift) 4475 4476 /*define for cache_policy field*/ 4477 #define SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_offset 0 4478 #define SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_mask 0x00000007 4479 #define SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_shift 20 4480 #define SDMA_PKT_POLL_REGMEM_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_mask) << SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_shift) 4481 4482 /*define for cpv field*/ 4483 #define SDMA_PKT_POLL_REGMEM_HEADER_cpv_offset 0 4484 #define SDMA_PKT_POLL_REGMEM_HEADER_cpv_mask 0x00000001 4485 #define SDMA_PKT_POLL_REGMEM_HEADER_cpv_shift 24 4486 #define SDMA_PKT_POLL_REGMEM_HEADER_CPV(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_cpv_mask) << SDMA_PKT_POLL_REGMEM_HEADER_cpv_shift) 4487 4488 /*define for hdp_flush field*/ 4489 #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 0 4490 #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask 0x00000001 4491 #define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift 26 4492 #define SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift) 4493 4494 /*define for func field*/ 4495 #define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 0 4496 #define SDMA_PKT_POLL_REGMEM_HEADER_func_mask 0x00000007 4497 #define SDMA_PKT_POLL_REGMEM_HEADER_func_shift 28 4498 #define SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift) 4499 4500 /*define for mem_poll field*/ 4501 #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 0 4502 #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask 0x00000001 4503 #define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift 31 4504 #define SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift) 4505 4506 /*define for ADDR_LO word*/ 4507 /*define for addr_31_0 field*/ 4508 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset 1 4509 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 4510 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift 0 4511 #define SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift) 4512 4513 /*define for ADDR_HI word*/ 4514 /*define for addr_63_32 field*/ 4515 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset 2 4516 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 4517 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift 0 4518 #define SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift) 4519 4520 /*define for VALUE word*/ 4521 /*define for value field*/ 4522 #define SDMA_PKT_POLL_REGMEM_VALUE_value_offset 3 4523 #define SDMA_PKT_POLL_REGMEM_VALUE_value_mask 0xFFFFFFFF 4524 #define SDMA_PKT_POLL_REGMEM_VALUE_value_shift 0 4525 #define SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x) (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift) 4526 4527 /*define for MASK word*/ 4528 /*define for mask field*/ 4529 #define SDMA_PKT_POLL_REGMEM_MASK_mask_offset 4 4530 #define SDMA_PKT_POLL_REGMEM_MASK_mask_mask 0xFFFFFFFF 4531 #define SDMA_PKT_POLL_REGMEM_MASK_mask_shift 0 4532 #define SDMA_PKT_POLL_REGMEM_MASK_MASK(x) (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift) 4533 4534 /*define for DW5 word*/ 4535 /*define for interval field*/ 4536 #define SDMA_PKT_POLL_REGMEM_DW5_interval_offset 5 4537 #define SDMA_PKT_POLL_REGMEM_DW5_interval_mask 0x0000FFFF 4538 #define SDMA_PKT_POLL_REGMEM_DW5_interval_shift 0 4539 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) 4540 4541 /*define for retry_count field*/ 4542 #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset 5 4543 #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask 0x00000FFF 4544 #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift 16 4545 #define SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift) 4546 4547 4548 /* 4549 ** Definitions for SDMA_PKT_POLL_REG_WRITE_MEM packet 4550 */ 4551 4552 /*define for HEADER word*/ 4553 /*define for op field*/ 4554 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset 0 4555 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask 0x000000FF 4556 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift 0 4557 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift) 4558 4559 /*define for sub_op field*/ 4560 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset 0 4561 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask 0x000000FF 4562 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift 8 4563 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift) 4564 4565 /*define for cache_policy field*/ 4566 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_offset 0 4567 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_mask 0x00000007 4568 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_shift 24 4569 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_shift) 4570 4571 /*define for cpv field*/ 4572 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_offset 0 4573 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_mask 0x00000001 4574 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_shift 28 4575 #define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_CPV(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_shift) 4576 4577 /*define for SRC_ADDR word*/ 4578 /*define for addr_31_2 field*/ 4579 #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset 1 4580 #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask 0x3FFFFFFF 4581 #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift 2 4582 #define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift) 4583 4584 /*define for DST_ADDR_LO word*/ 4585 /*define for addr_31_0 field*/ 4586 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 2 4587 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 4588 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 4589 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) 4590 4591 /*define for DST_ADDR_HI word*/ 4592 /*define for addr_63_32 field*/ 4593 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 3 4594 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 4595 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 4596 #define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) 4597 4598 4599 /* 4600 ** Definitions for SDMA_PKT_POLL_DBIT_WRITE_MEM packet 4601 */ 4602 4603 /*define for HEADER word*/ 4604 /*define for op field*/ 4605 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset 0 4606 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask 0x000000FF 4607 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift 0 4608 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift) 4609 4610 /*define for sub_op field*/ 4611 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset 0 4612 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask 0x000000FF 4613 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift 8 4614 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift) 4615 4616 /*define for ea field*/ 4617 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset 0 4618 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask 0x00000003 4619 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift 16 4620 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift) 4621 4622 /*define for cache_policy field*/ 4623 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_offset 0 4624 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_mask 0x00000007 4625 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_shift 24 4626 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_shift) 4627 4628 /*define for cpv field*/ 4629 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_offset 0 4630 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_mask 0x00000001 4631 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_shift 28 4632 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_CPV(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_shift) 4633 4634 /*define for DST_ADDR_LO word*/ 4635 /*define for addr_31_0 field*/ 4636 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 1 4637 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 4638 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 4639 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) 4640 4641 /*define for DST_ADDR_HI word*/ 4642 /*define for addr_63_32 field*/ 4643 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 2 4644 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 4645 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 4646 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) 4647 4648 /*define for START_PAGE word*/ 4649 /*define for addr_31_4 field*/ 4650 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset 3 4651 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask 0x0FFFFFFF 4652 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift 4 4653 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift) 4654 4655 /*define for PAGE_NUM word*/ 4656 /*define for page_num_31_0 field*/ 4657 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset 4 4658 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask 0xFFFFFFFF 4659 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift 0 4660 #define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift) 4661 4662 4663 /* 4664 ** Definitions for SDMA_PKT_POLL_MEM_VERIFY packet 4665 */ 4666 4667 /*define for HEADER word*/ 4668 /*define for op field*/ 4669 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset 0 4670 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask 0x000000FF 4671 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift 0 4672 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift) 4673 4674 /*define for sub_op field*/ 4675 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset 0 4676 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask 0x000000FF 4677 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift 8 4678 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift) 4679 4680 /*define for cache_policy field*/ 4681 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_offset 0 4682 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_mask 0x00000007 4683 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_shift 24 4684 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_shift) 4685 4686 /*define for cpv field*/ 4687 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_offset 0 4688 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_mask 0x00000001 4689 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_shift 28 4690 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_CPV(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_shift) 4691 4692 /*define for mode field*/ 4693 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset 0 4694 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask 0x00000001 4695 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift 31 4696 #define SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift) 4697 4698 /*define for PATTERN word*/ 4699 /*define for pattern field*/ 4700 #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset 1 4701 #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask 0xFFFFFFFF 4702 #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift 0 4703 #define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask) << SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift) 4704 4705 /*define for CMP0_ADDR_START_LO word*/ 4706 /*define for cmp0_start_31_0 field*/ 4707 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset 2 4708 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask 0xFFFFFFFF 4709 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift 0 4710 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift) 4711 4712 /*define for CMP0_ADDR_START_HI word*/ 4713 /*define for cmp0_start_63_32 field*/ 4714 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset 3 4715 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask 0xFFFFFFFF 4716 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift 0 4717 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift) 4718 4719 /*define for CMP0_ADDR_END_LO word*/ 4720 /*define for cmp0_end_31_0 field*/ 4721 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_offset 4 4722 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_mask 0xFFFFFFFF 4723 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_shift 0 4724 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP0_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_shift) 4725 4726 /*define for CMP0_ADDR_END_HI word*/ 4727 /*define for cmp0_end_63_32 field*/ 4728 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_offset 5 4729 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_mask 0xFFFFFFFF 4730 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_shift 0 4731 #define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP0_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_shift) 4732 4733 /*define for CMP1_ADDR_START_LO word*/ 4734 /*define for cmp1_start_31_0 field*/ 4735 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset 6 4736 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask 0xFFFFFFFF 4737 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift 0 4738 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift) 4739 4740 /*define for CMP1_ADDR_START_HI word*/ 4741 /*define for cmp1_start_63_32 field*/ 4742 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset 7 4743 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask 0xFFFFFFFF 4744 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift 0 4745 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift) 4746 4747 /*define for CMP1_ADDR_END_LO word*/ 4748 /*define for cmp1_end_31_0 field*/ 4749 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset 8 4750 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF 4751 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift 0 4752 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift) 4753 4754 /*define for CMP1_ADDR_END_HI word*/ 4755 /*define for cmp1_end_63_32 field*/ 4756 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset 9 4757 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF 4758 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift 0 4759 #define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift) 4760 4761 /*define for REC_ADDR_LO word*/ 4762 /*define for rec_31_0 field*/ 4763 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset 10 4764 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask 0xFFFFFFFF 4765 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift 0 4766 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift) 4767 4768 /*define for REC_ADDR_HI word*/ 4769 /*define for rec_63_32 field*/ 4770 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset 11 4771 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask 0xFFFFFFFF 4772 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift 0 4773 #define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift) 4774 4775 /*define for RESERVED word*/ 4776 /*define for reserved field*/ 4777 #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset 12 4778 #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask 0xFFFFFFFF 4779 #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift 0 4780 #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask) << SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift) 4781 4782 4783 /* 4784 ** Definitions for SDMA_PKT_ATOMIC packet 4785 */ 4786 4787 /*define for HEADER word*/ 4788 /*define for op field*/ 4789 #define SDMA_PKT_ATOMIC_HEADER_op_offset 0 4790 #define SDMA_PKT_ATOMIC_HEADER_op_mask 0x000000FF 4791 #define SDMA_PKT_ATOMIC_HEADER_op_shift 0 4792 #define SDMA_PKT_ATOMIC_HEADER_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_op_mask) << SDMA_PKT_ATOMIC_HEADER_op_shift) 4793 4794 /*define for loop field*/ 4795 #define SDMA_PKT_ATOMIC_HEADER_loop_offset 0 4796 #define SDMA_PKT_ATOMIC_HEADER_loop_mask 0x00000001 4797 #define SDMA_PKT_ATOMIC_HEADER_loop_shift 16 4798 #define SDMA_PKT_ATOMIC_HEADER_LOOP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_loop_mask) << SDMA_PKT_ATOMIC_HEADER_loop_shift) 4799 4800 /*define for tmz field*/ 4801 #define SDMA_PKT_ATOMIC_HEADER_tmz_offset 0 4802 #define SDMA_PKT_ATOMIC_HEADER_tmz_mask 0x00000001 4803 #define SDMA_PKT_ATOMIC_HEADER_tmz_shift 18 4804 #define SDMA_PKT_ATOMIC_HEADER_TMZ(x) (((x) & SDMA_PKT_ATOMIC_HEADER_tmz_mask) << SDMA_PKT_ATOMIC_HEADER_tmz_shift) 4805 4806 /*define for cache_policy field*/ 4807 #define SDMA_PKT_ATOMIC_HEADER_cache_policy_offset 0 4808 #define SDMA_PKT_ATOMIC_HEADER_cache_policy_mask 0x00000007 4809 #define SDMA_PKT_ATOMIC_HEADER_cache_policy_shift 20 4810 #define SDMA_PKT_ATOMIC_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_ATOMIC_HEADER_cache_policy_mask) << SDMA_PKT_ATOMIC_HEADER_cache_policy_shift) 4811 4812 /*define for cpv field*/ 4813 #define SDMA_PKT_ATOMIC_HEADER_cpv_offset 0 4814 #define SDMA_PKT_ATOMIC_HEADER_cpv_mask 0x00000001 4815 #define SDMA_PKT_ATOMIC_HEADER_cpv_shift 24 4816 #define SDMA_PKT_ATOMIC_HEADER_CPV(x) (((x) & SDMA_PKT_ATOMIC_HEADER_cpv_mask) << SDMA_PKT_ATOMIC_HEADER_cpv_shift) 4817 4818 /*define for atomic_op field*/ 4819 #define SDMA_PKT_ATOMIC_HEADER_atomic_op_offset 0 4820 #define SDMA_PKT_ATOMIC_HEADER_atomic_op_mask 0x0000007F 4821 #define SDMA_PKT_ATOMIC_HEADER_atomic_op_shift 25 4822 #define SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_atomic_op_mask) << SDMA_PKT_ATOMIC_HEADER_atomic_op_shift) 4823 4824 /*define for ADDR_LO word*/ 4825 /*define for addr_31_0 field*/ 4826 #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset 1 4827 #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask 0xFFFFFFFF 4828 #define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift 0 4829 #define SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask) << SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift) 4830 4831 /*define for ADDR_HI word*/ 4832 /*define for addr_63_32 field*/ 4833 #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset 2 4834 #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask 0xFFFFFFFF 4835 #define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift 0 4836 #define SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask) << SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift) 4837 4838 /*define for SRC_DATA_LO word*/ 4839 /*define for src_data_31_0 field*/ 4840 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset 3 4841 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask 0xFFFFFFFF 4842 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift 0 4843 #define SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask) << SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift) 4844 4845 /*define for SRC_DATA_HI word*/ 4846 /*define for src_data_63_32 field*/ 4847 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset 4 4848 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask 0xFFFFFFFF 4849 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift 0 4850 #define SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask) << SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift) 4851 4852 /*define for CMP_DATA_LO word*/ 4853 /*define for cmp_data_31_0 field*/ 4854 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset 5 4855 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask 0xFFFFFFFF 4856 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift 0 4857 #define SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask) << SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift) 4858 4859 /*define for CMP_DATA_HI word*/ 4860 /*define for cmp_data_63_32 field*/ 4861 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset 6 4862 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask 0xFFFFFFFF 4863 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift 0 4864 #define SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask) << SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift) 4865 4866 /*define for LOOP_INTERVAL word*/ 4867 /*define for loop_interval field*/ 4868 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset 7 4869 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask 0x00001FFF 4870 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift 0 4871 #define SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x) (((x) & SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask) << SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift) 4872 4873 4874 /* 4875 ** Definitions for SDMA_PKT_TIMESTAMP_SET packet 4876 */ 4877 4878 /*define for HEADER word*/ 4879 /*define for op field*/ 4880 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 0 4881 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask 0x000000FF 4882 #define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift 0 4883 #define SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift) 4884 4885 /*define for sub_op field*/ 4886 #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 0 4887 #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask 0x000000FF 4888 #define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift 8 4889 #define SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift) 4890 4891 /*define for INIT_DATA_LO word*/ 4892 /*define for init_data_31_0 field*/ 4893 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset 1 4894 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask 0xFFFFFFFF 4895 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift 0 4896 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift) 4897 4898 /*define for INIT_DATA_HI word*/ 4899 /*define for init_data_63_32 field*/ 4900 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset 2 4901 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask 0xFFFFFFFF 4902 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift 0 4903 #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift) 4904 4905 4906 /* 4907 ** Definitions for SDMA_PKT_TIMESTAMP_GET packet 4908 */ 4909 4910 /*define for HEADER word*/ 4911 /*define for op field*/ 4912 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 0 4913 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask 0x000000FF 4914 #define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift 0 4915 #define SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift) 4916 4917 /*define for sub_op field*/ 4918 #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 0 4919 #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask 0x000000FF 4920 #define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift 8 4921 #define SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift) 4922 4923 /*define for l2_policy field*/ 4924 #define SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_offset 0 4925 #define SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_mask 0x00000003 4926 #define SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_shift 24 4927 #define SDMA_PKT_TIMESTAMP_GET_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_shift) 4928 4929 /*define for llc_policy field*/ 4930 #define SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_offset 0 4931 #define SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_mask 0x00000001 4932 #define SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_shift 26 4933 #define SDMA_PKT_TIMESTAMP_GET_HEADER_LLC_POLICY(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_shift) 4934 4935 /*define for cpv field*/ 4936 #define SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_offset 0 4937 #define SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_mask 0x00000001 4938 #define SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_shift 28 4939 #define SDMA_PKT_TIMESTAMP_GET_HEADER_CPV(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_shift) 4940 4941 /*define for WRITE_ADDR_LO word*/ 4942 /*define for write_addr_31_3 field*/ 4943 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset 1 4944 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF 4945 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift 3 4946 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift) 4947 4948 /*define for WRITE_ADDR_HI word*/ 4949 /*define for write_addr_63_32 field*/ 4950 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset 2 4951 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF 4952 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift 0 4953 #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift) 4954 4955 4956 /* 4957 ** Definitions for SDMA_PKT_TIMESTAMP_GET_GLOBAL packet 4958 */ 4959 4960 /*define for HEADER word*/ 4961 /*define for op field*/ 4962 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 0 4963 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask 0x000000FF 4964 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift 0 4965 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift) 4966 4967 /*define for sub_op field*/ 4968 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 0 4969 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask 0x000000FF 4970 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift 8 4971 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift) 4972 4973 /*define for l2_policy field*/ 4974 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_offset 0 4975 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_mask 0x00000003 4976 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_shift 24 4977 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_shift) 4978 4979 /*define for llc_policy field*/ 4980 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_offset 0 4981 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_mask 0x00000001 4982 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_shift 26 4983 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_LLC_POLICY(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_shift) 4984 4985 /*define for cpv field*/ 4986 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_offset 0 4987 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_mask 0x00000001 4988 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_shift 28 4989 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_CPV(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_shift) 4990 4991 /*define for WRITE_ADDR_LO word*/ 4992 /*define for write_addr_31_3 field*/ 4993 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset 1 4994 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF 4995 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift 3 4996 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift) 4997 4998 /*define for WRITE_ADDR_HI word*/ 4999 /*define for write_addr_63_32 field*/ 5000 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset 2 5001 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF 5002 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift 0 5003 #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift) 5004 5005 5006 /* 5007 ** Definitions for SDMA_PKT_TRAP packet 5008 */ 5009 5010 /*define for HEADER word*/ 5011 /*define for op field*/ 5012 #define SDMA_PKT_TRAP_HEADER_op_offset 0 5013 #define SDMA_PKT_TRAP_HEADER_op_mask 0x000000FF 5014 #define SDMA_PKT_TRAP_HEADER_op_shift 0 5015 #define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift) 5016 5017 /*define for sub_op field*/ 5018 #define SDMA_PKT_TRAP_HEADER_sub_op_offset 0 5019 #define SDMA_PKT_TRAP_HEADER_sub_op_mask 0x000000FF 5020 #define SDMA_PKT_TRAP_HEADER_sub_op_shift 8 5021 #define SDMA_PKT_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift) 5022 5023 /*define for INT_CONTEXT word*/ 5024 /*define for int_context field*/ 5025 #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset 1 5026 #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF 5027 #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift 0 5028 #define SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift) 5029 5030 5031 /* 5032 ** Definitions for SDMA_PKT_DUMMY_TRAP packet 5033 */ 5034 5035 /*define for HEADER word*/ 5036 /*define for op field*/ 5037 #define SDMA_PKT_DUMMY_TRAP_HEADER_op_offset 0 5038 #define SDMA_PKT_DUMMY_TRAP_HEADER_op_mask 0x000000FF 5039 #define SDMA_PKT_DUMMY_TRAP_HEADER_op_shift 0 5040 #define SDMA_PKT_DUMMY_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_op_shift) 5041 5042 /*define for sub_op field*/ 5043 #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset 0 5044 #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask 0x000000FF 5045 #define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift 8 5046 #define SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift) 5047 5048 /*define for INT_CONTEXT word*/ 5049 /*define for int_context field*/ 5050 #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset 1 5051 #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF 5052 #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift 0 5053 #define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift) 5054 5055 5056 /* 5057 ** Definitions for SDMA_PKT_GPUVM_INV packet 5058 */ 5059 5060 /*define for HEADER word*/ 5061 /*define for op field*/ 5062 #define SDMA_PKT_GPUVM_INV_HEADER_op_offset 0 5063 #define SDMA_PKT_GPUVM_INV_HEADER_op_mask 0x000000FF 5064 #define SDMA_PKT_GPUVM_INV_HEADER_op_shift 0 5065 #define SDMA_PKT_GPUVM_INV_HEADER_OP(x) (((x) & SDMA_PKT_GPUVM_INV_HEADER_op_mask) << SDMA_PKT_GPUVM_INV_HEADER_op_shift) 5066 5067 /*define for sub_op field*/ 5068 #define SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset 0 5069 #define SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask 0x000000FF 5070 #define SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift 8 5071 #define SDMA_PKT_GPUVM_INV_HEADER_SUB_OP(x) (((x) & SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask) << SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift) 5072 5073 /*define for PAYLOAD1 word*/ 5074 /*define for per_vmid_inv_req field*/ 5075 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset 1 5076 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask 0x0000FFFF 5077 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift 0 5078 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_PER_VMID_INV_REQ(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift) 5079 5080 /*define for flush_type field*/ 5081 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset 1 5082 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask 0x00000007 5083 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift 16 5084 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_FLUSH_TYPE(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift) 5085 5086 /*define for l2_ptes field*/ 5087 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset 1 5088 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask 0x00000001 5089 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift 19 5090 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift) 5091 5092 /*define for l2_pde0 field*/ 5093 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset 1 5094 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask 0x00000001 5095 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift 20 5096 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE0(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift) 5097 5098 /*define for l2_pde1 field*/ 5099 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset 1 5100 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask 0x00000001 5101 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift 21 5102 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE1(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift) 5103 5104 /*define for l2_pde2 field*/ 5105 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset 1 5106 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask 0x00000001 5107 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift 22 5108 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE2(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift) 5109 5110 /*define for l1_ptes field*/ 5111 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset 1 5112 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask 0x00000001 5113 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift 23 5114 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_L1_PTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift) 5115 5116 /*define for clr_protection_fault_status_addr field*/ 5117 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset 1 5118 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask 0x00000001 5119 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift 24 5120 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_CLR_PROTECTION_FAULT_STATUS_ADDR(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift) 5121 5122 /*define for log_request field*/ 5123 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset 1 5124 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask 0x00000001 5125 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift 25 5126 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_LOG_REQUEST(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift) 5127 5128 /*define for four_kilobytes field*/ 5129 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset 1 5130 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask 0x00000001 5131 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift 26 5132 #define SDMA_PKT_GPUVM_INV_PAYLOAD1_FOUR_KILOBYTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift) 5133 5134 /*define for PAYLOAD2 word*/ 5135 /*define for s field*/ 5136 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset 2 5137 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask 0x00000001 5138 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift 0 5139 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_S(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift) 5140 5141 /*define for page_va_42_12 field*/ 5142 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset 2 5143 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask 0x7FFFFFFF 5144 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift 1 5145 #define SDMA_PKT_GPUVM_INV_PAYLOAD2_PAGE_VA_42_12(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift) 5146 5147 /*define for PAYLOAD3 word*/ 5148 /*define for page_va_47_43 field*/ 5149 #define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset 3 5150 #define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask 0x0000003F 5151 #define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift 0 5152 #define SDMA_PKT_GPUVM_INV_PAYLOAD3_PAGE_VA_47_43(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift) 5153 5154 5155 /* 5156 ** Definitions for SDMA_PKT_GCR_REQ packet 5157 */ 5158 5159 /*define for HEADER word*/ 5160 /*define for op field*/ 5161 #define SDMA_PKT_GCR_REQ_HEADER_op_offset 0 5162 #define SDMA_PKT_GCR_REQ_HEADER_op_mask 0x000000FF 5163 #define SDMA_PKT_GCR_REQ_HEADER_op_shift 0 5164 #define SDMA_PKT_GCR_REQ_HEADER_OP(x) (((x) & SDMA_PKT_GCR_REQ_HEADER_op_mask) << SDMA_PKT_GCR_REQ_HEADER_op_shift) 5165 5166 /*define for sub_op field*/ 5167 #define SDMA_PKT_GCR_REQ_HEADER_sub_op_offset 0 5168 #define SDMA_PKT_GCR_REQ_HEADER_sub_op_mask 0x000000FF 5169 #define SDMA_PKT_GCR_REQ_HEADER_sub_op_shift 8 5170 #define SDMA_PKT_GCR_REQ_HEADER_SUB_OP(x) (((x) & SDMA_PKT_GCR_REQ_HEADER_sub_op_mask) << SDMA_PKT_GCR_REQ_HEADER_sub_op_shift) 5171 5172 /*define for PAYLOAD1 word*/ 5173 /*define for base_va_31_7 field*/ 5174 #define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset 1 5175 #define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask 0x01FFFFFF 5176 #define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift 7 5177 #define SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask) << SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift) 5178 5179 /*define for PAYLOAD2 word*/ 5180 /*define for base_va_47_32 field*/ 5181 #define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_offset 2 5182 #define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask 0x0000FFFF 5183 #define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift 0 5184 #define SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask) << SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift) 5185 5186 /*define for gcr_control_15_0 field*/ 5187 #define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_offset 2 5188 #define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask 0x0000FFFF 5189 #define SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift 16 5190 #define SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask) << SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift) 5191 5192 /*define for PAYLOAD3 word*/ 5193 /*define for gcr_control_18_16 field*/ 5194 #define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_offset 3 5195 #define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask 0x00000007 5196 #define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift 0 5197 #define SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask) << SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift) 5198 5199 /*define for limit_va_31_7 field*/ 5200 #define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_offset 3 5201 #define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask 0x01FFFFFF 5202 #define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift 7 5203 #define SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask) << SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift) 5204 5205 /*define for PAYLOAD4 word*/ 5206 /*define for limit_va_47_32 field*/ 5207 #define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_offset 4 5208 #define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask 0x0000FFFF 5209 #define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift 0 5210 #define SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask) << SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift) 5211 5212 /*define for vmid field*/ 5213 #define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_offset 4 5214 #define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask 0x0000000F 5215 #define SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift 24 5216 #define SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask) << SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift) 5217 5218 5219 /* 5220 ** Definitions for SDMA_PKT_NOP packet 5221 */ 5222 5223 /*define for HEADER word*/ 5224 /*define for op field*/ 5225 #define SDMA_PKT_NOP_HEADER_op_offset 0 5226 #define SDMA_PKT_NOP_HEADER_op_mask 0x000000FF 5227 #define SDMA_PKT_NOP_HEADER_op_shift 0 5228 #define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift) 5229 5230 /*define for sub_op field*/ 5231 #define SDMA_PKT_NOP_HEADER_sub_op_offset 0 5232 #define SDMA_PKT_NOP_HEADER_sub_op_mask 0x000000FF 5233 #define SDMA_PKT_NOP_HEADER_sub_op_shift 8 5234 #define SDMA_PKT_NOP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift) 5235 5236 /*define for count field*/ 5237 #define SDMA_PKT_NOP_HEADER_count_offset 0 5238 #define SDMA_PKT_NOP_HEADER_count_mask 0x00003FFF 5239 #define SDMA_PKT_NOP_HEADER_count_shift 16 5240 #define SDMA_PKT_NOP_HEADER_COUNT(x) (((x) & SDMA_PKT_NOP_HEADER_count_mask) << SDMA_PKT_NOP_HEADER_count_shift) 5241 5242 /*define for DATA0 word*/ 5243 /*define for data0 field*/ 5244 #define SDMA_PKT_NOP_DATA0_data0_offset 1 5245 #define SDMA_PKT_NOP_DATA0_data0_mask 0xFFFFFFFF 5246 #define SDMA_PKT_NOP_DATA0_data0_shift 0 5247 #define SDMA_PKT_NOP_DATA0_DATA0(x) (((x) & SDMA_PKT_NOP_DATA0_data0_mask) << SDMA_PKT_NOP_DATA0_data0_shift) 5248 5249 5250 /* 5251 ** Definitions for SDMA_AQL_PKT_HEADER packet 5252 */ 5253 5254 /*define for HEADER word*/ 5255 /*define for format field*/ 5256 #define SDMA_AQL_PKT_HEADER_HEADER_format_offset 0 5257 #define SDMA_AQL_PKT_HEADER_HEADER_format_mask 0x000000FF 5258 #define SDMA_AQL_PKT_HEADER_HEADER_format_shift 0 5259 #define SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_format_mask) << SDMA_AQL_PKT_HEADER_HEADER_format_shift) 5260 5261 /*define for barrier field*/ 5262 #define SDMA_AQL_PKT_HEADER_HEADER_barrier_offset 0 5263 #define SDMA_AQL_PKT_HEADER_HEADER_barrier_mask 0x00000001 5264 #define SDMA_AQL_PKT_HEADER_HEADER_barrier_shift 8 5265 #define SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_barrier_mask) << SDMA_AQL_PKT_HEADER_HEADER_barrier_shift) 5266 5267 /*define for acquire_fence_scope field*/ 5268 #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset 0 5269 #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask 0x00000003 5270 #define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift 9 5271 #define SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift) 5272 5273 /*define for release_fence_scope field*/ 5274 #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset 0 5275 #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask 0x00000003 5276 #define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift 11 5277 #define SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift) 5278 5279 /*define for reserved field*/ 5280 #define SDMA_AQL_PKT_HEADER_HEADER_reserved_offset 0 5281 #define SDMA_AQL_PKT_HEADER_HEADER_reserved_mask 0x00000007 5282 #define SDMA_AQL_PKT_HEADER_HEADER_reserved_shift 13 5283 #define SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_reserved_mask) << SDMA_AQL_PKT_HEADER_HEADER_reserved_shift) 5284 5285 /*define for op field*/ 5286 #define SDMA_AQL_PKT_HEADER_HEADER_op_offset 0 5287 #define SDMA_AQL_PKT_HEADER_HEADER_op_mask 0x0000000F 5288 #define SDMA_AQL_PKT_HEADER_HEADER_op_shift 16 5289 #define SDMA_AQL_PKT_HEADER_HEADER_OP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_op_mask) << SDMA_AQL_PKT_HEADER_HEADER_op_shift) 5290 5291 /*define for subop field*/ 5292 #define SDMA_AQL_PKT_HEADER_HEADER_subop_offset 0 5293 #define SDMA_AQL_PKT_HEADER_HEADER_subop_mask 0x00000007 5294 #define SDMA_AQL_PKT_HEADER_HEADER_subop_shift 20 5295 #define SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_subop_mask) << SDMA_AQL_PKT_HEADER_HEADER_subop_shift) 5296 5297 /*define for cpv field*/ 5298 #define SDMA_AQL_PKT_HEADER_HEADER_cpv_offset 0 5299 #define SDMA_AQL_PKT_HEADER_HEADER_cpv_mask 0x00000001 5300 #define SDMA_AQL_PKT_HEADER_HEADER_cpv_shift 28 5301 #define SDMA_AQL_PKT_HEADER_HEADER_CPV(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_cpv_mask) << SDMA_AQL_PKT_HEADER_HEADER_cpv_shift) 5302 5303 5304 /* 5305 ** Definitions for SDMA_AQL_PKT_COPY_LINEAR packet 5306 */ 5307 5308 /*define for HEADER word*/ 5309 /*define for format field*/ 5310 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset 0 5311 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask 0x000000FF 5312 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift 0 5313 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift) 5314 5315 /*define for barrier field*/ 5316 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset 0 5317 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask 0x00000001 5318 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift 8 5319 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift) 5320 5321 /*define for acquire_fence_scope field*/ 5322 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset 0 5323 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask 0x00000003 5324 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift 9 5325 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift) 5326 5327 /*define for release_fence_scope field*/ 5328 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset 0 5329 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask 0x00000003 5330 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift 11 5331 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift) 5332 5333 /*define for reserved field*/ 5334 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset 0 5335 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask 0x00000007 5336 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift 13 5337 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift) 5338 5339 /*define for op field*/ 5340 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset 0 5341 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask 0x0000000F 5342 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift 16 5343 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift) 5344 5345 /*define for subop field*/ 5346 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset 0 5347 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask 0x00000007 5348 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift 20 5349 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift) 5350 5351 /*define for cpv field*/ 5352 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_offset 0 5353 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_mask 0x00000001 5354 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_shift 28 5355 #define SDMA_AQL_PKT_COPY_LINEAR_HEADER_CPV(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_shift) 5356 5357 /*define for RESERVED_DW1 word*/ 5358 /*define for reserved_dw1 field*/ 5359 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset 1 5360 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF 5361 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift 0 5362 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift) 5363 5364 /*define for RETURN_ADDR_LO word*/ 5365 /*define for return_addr_31_0 field*/ 5366 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset 2 5367 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask 0xFFFFFFFF 5368 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift 0 5369 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift) 5370 5371 /*define for RETURN_ADDR_HI word*/ 5372 /*define for return_addr_63_32 field*/ 5373 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset 3 5374 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask 0xFFFFFFFF 5375 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift 0 5376 #define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift) 5377 5378 /*define for COUNT word*/ 5379 /*define for count field*/ 5380 #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset 4 5381 #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF 5382 #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift 0 5383 #define SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift) 5384 5385 /*define for PARAMETER word*/ 5386 /*define for dst_sw field*/ 5387 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 5 5388 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 5389 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 5390 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) 5391 5392 /*define for dst_cache_policy field*/ 5393 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset 5 5394 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask 0x00000007 5395 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift 18 5396 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_CACHE_POLICY(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift) 5397 5398 /*define for src_sw field*/ 5399 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 5 5400 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 5401 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 5402 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) 5403 5404 /*define for src_cache_policy field*/ 5405 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset 5 5406 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask 0x00000007 5407 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift 26 5408 #define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_CACHE_POLICY(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift) 5409 5410 /*define for SRC_ADDR_LO word*/ 5411 /*define for src_addr_31_0 field*/ 5412 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 6 5413 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF 5414 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 5415 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) 5416 5417 /*define for SRC_ADDR_HI word*/ 5418 /*define for src_addr_63_32 field*/ 5419 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 7 5420 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF 5421 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 5422 #define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) 5423 5424 /*define for DST_ADDR_LO word*/ 5425 /*define for dst_addr_31_0 field*/ 5426 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 8 5427 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF 5428 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 5429 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) 5430 5431 /*define for DST_ADDR_HI word*/ 5432 /*define for dst_addr_63_32 field*/ 5433 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 9 5434 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF 5435 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 5436 #define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) 5437 5438 /*define for RESERVED_DW10 word*/ 5439 /*define for reserved_dw10 field*/ 5440 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset 10 5441 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask 0xFFFFFFFF 5442 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift 0 5443 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift) 5444 5445 /*define for RESERVED_DW11 word*/ 5446 /*define for reserved_dw11 field*/ 5447 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset 11 5448 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask 0xFFFFFFFF 5449 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift 0 5450 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift) 5451 5452 /*define for RESERVED_DW12 word*/ 5453 /*define for reserved_dw12 field*/ 5454 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset 12 5455 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF 5456 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift 0 5457 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift) 5458 5459 /*define for RESERVED_DW13 word*/ 5460 /*define for reserved_dw13 field*/ 5461 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset 13 5462 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF 5463 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift 0 5464 #define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift) 5465 5466 /*define for COMPLETION_SIGNAL_LO word*/ 5467 /*define for completion_signal_31_0 field*/ 5468 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 5469 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF 5470 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 5471 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) 5472 5473 /*define for COMPLETION_SIGNAL_HI word*/ 5474 /*define for completion_signal_63_32 field*/ 5475 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 5476 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF 5477 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 5478 #define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) 5479 5480 5481 /* 5482 ** Definitions for SDMA_AQL_PKT_BARRIER_OR packet 5483 */ 5484 5485 /*define for HEADER word*/ 5486 /*define for format field*/ 5487 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset 0 5488 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask 0x000000FF 5489 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift 0 5490 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift) 5491 5492 /*define for barrier field*/ 5493 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset 0 5494 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask 0x00000001 5495 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift 8 5496 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift) 5497 5498 /*define for acquire_fence_scope field*/ 5499 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset 0 5500 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask 0x00000003 5501 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift 9 5502 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift) 5503 5504 /*define for release_fence_scope field*/ 5505 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset 0 5506 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask 0x00000003 5507 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift 11 5508 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift) 5509 5510 /*define for reserved field*/ 5511 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset 0 5512 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask 0x00000007 5513 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift 13 5514 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift) 5515 5516 /*define for op field*/ 5517 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset 0 5518 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask 0x0000000F 5519 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift 16 5520 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift) 5521 5522 /*define for subop field*/ 5523 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset 0 5524 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask 0x00000007 5525 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift 20 5526 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift) 5527 5528 /*define for cpv field*/ 5529 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_offset 0 5530 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_mask 0x00000001 5531 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_shift 28 5532 #define SDMA_AQL_PKT_BARRIER_OR_HEADER_CPV(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_shift) 5533 5534 /*define for RESERVED_DW1 word*/ 5535 /*define for reserved_dw1 field*/ 5536 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset 1 5537 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF 5538 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift 0 5539 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift) 5540 5541 /*define for DEPENDENT_ADDR_0_LO word*/ 5542 /*define for dependent_addr_0_31_0 field*/ 5543 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset 2 5544 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask 0xFFFFFFFF 5545 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift 0 5546 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift) 5547 5548 /*define for DEPENDENT_ADDR_0_HI word*/ 5549 /*define for dependent_addr_0_63_32 field*/ 5550 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset 3 5551 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask 0xFFFFFFFF 5552 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift 0 5553 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift) 5554 5555 /*define for DEPENDENT_ADDR_1_LO word*/ 5556 /*define for dependent_addr_1_31_0 field*/ 5557 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset 4 5558 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask 0xFFFFFFFF 5559 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift 0 5560 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift) 5561 5562 /*define for DEPENDENT_ADDR_1_HI word*/ 5563 /*define for dependent_addr_1_63_32 field*/ 5564 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset 5 5565 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask 0xFFFFFFFF 5566 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift 0 5567 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift) 5568 5569 /*define for DEPENDENT_ADDR_2_LO word*/ 5570 /*define for dependent_addr_2_31_0 field*/ 5571 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset 6 5572 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask 0xFFFFFFFF 5573 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift 0 5574 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift) 5575 5576 /*define for DEPENDENT_ADDR_2_HI word*/ 5577 /*define for dependent_addr_2_63_32 field*/ 5578 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset 7 5579 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask 0xFFFFFFFF 5580 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift 0 5581 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift) 5582 5583 /*define for DEPENDENT_ADDR_3_LO word*/ 5584 /*define for dependent_addr_3_31_0 field*/ 5585 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset 8 5586 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask 0xFFFFFFFF 5587 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift 0 5588 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift) 5589 5590 /*define for DEPENDENT_ADDR_3_HI word*/ 5591 /*define for dependent_addr_3_63_32 field*/ 5592 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset 9 5593 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask 0xFFFFFFFF 5594 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift 0 5595 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift) 5596 5597 /*define for DEPENDENT_ADDR_4_LO word*/ 5598 /*define for dependent_addr_4_31_0 field*/ 5599 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset 10 5600 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask 0xFFFFFFFF 5601 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift 0 5602 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift) 5603 5604 /*define for DEPENDENT_ADDR_4_HI word*/ 5605 /*define for dependent_addr_4_63_32 field*/ 5606 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset 11 5607 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask 0xFFFFFFFF 5608 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift 0 5609 #define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift) 5610 5611 /*define for CACHE_POLICY word*/ 5612 /*define for cache_policy0 field*/ 5613 #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_offset 12 5614 #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_mask 0x00000007 5615 #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_shift 0 5616 #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_shift) 5617 5618 /*define for cache_policy1 field*/ 5619 #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_offset 12 5620 #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_mask 0x00000007 5621 #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_shift 5 5622 #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY1(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_shift) 5623 5624 /*define for cache_policy2 field*/ 5625 #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_offset 12 5626 #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_mask 0x00000007 5627 #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_shift 10 5628 #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY2(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_shift) 5629 5630 /*define for cache_policy3 field*/ 5631 #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_offset 12 5632 #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_mask 0x00000007 5633 #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_shift 15 5634 #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY3(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_shift) 5635 5636 /*define for cache_policy4 field*/ 5637 #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_offset 12 5638 #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_mask 0x00000007 5639 #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_shift 20 5640 #define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY4(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_shift) 5641 5642 /*define for RESERVED_DW13 word*/ 5643 /*define for reserved_dw13 field*/ 5644 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset 13 5645 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF 5646 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift 0 5647 #define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift) 5648 5649 /*define for COMPLETION_SIGNAL_LO word*/ 5650 /*define for completion_signal_31_0 field*/ 5651 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 5652 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF 5653 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 5654 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) 5655 5656 /*define for COMPLETION_SIGNAL_HI word*/ 5657 /*define for completion_signal_63_32 field*/ 5658 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 5659 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF 5660 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 5661 #define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) 5662 5663 5664 #endif /* __SDMA_V6_0_0_PKT_OPEN_H_ */ 5665