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Searched refs:SDMA3_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma3/
H A Dsdma3_4_2_2_sh_mask.h2495 #define SDMA3_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_0_sh_mask.h10671 #define SDMA3_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_3_0_sh_mask.h43984 #define SDMA3_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT … macro