1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _sdma_4_4_0_SH_MASK_HEADER 24 #define _sdma_4_4_0_SH_MASK_HEADER 25 26 27 // addressBlock: sdma0_sdma0dec 28 //SDMA0_UCODE_ADDR 29 #define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 30 #define SDMA0_UCODE_ADDR__VALUE_MASK 0x00003FFFL 31 //SDMA0_UCODE_DATA 32 #define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 33 #define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 34 //SDMA0_VF_ENABLE 35 #define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 36 #define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 37 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 38 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 39 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L 40 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L 41 //SDMA0_CONTEXT_GROUP_BOUNDARY 42 #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 43 #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 44 //SDMA0_POWER_CNTL 45 #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 46 #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 47 #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 48 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 49 #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 50 #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 51 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 52 #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 53 #define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 54 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a 55 #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L 56 #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L 57 #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L 58 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 59 #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 60 #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 61 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 62 #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 63 #define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 64 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 65 //SDMA0_CLK_CTRL 66 #define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 67 #define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 68 #define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc 69 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 70 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 71 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 72 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 73 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 74 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 75 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 76 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 77 #define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 78 #define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 79 #define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L 80 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 81 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 82 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 83 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 84 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 85 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 86 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 87 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 88 //SDMA0_CNTL 89 #define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 90 #define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 91 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 92 #define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 93 #define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 94 #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 95 #define SDMA0_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x6 96 #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 97 #define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 98 #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 99 #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 100 #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 101 #define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L 102 #define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 103 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 104 #define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 105 #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 106 #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 107 #define SDMA0_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000040L 108 #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 109 #define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 110 #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 111 #define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 112 #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 113 //SDMA0_CHICKEN_BITS 114 #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 115 #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 116 #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 117 #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 118 #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 119 #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 120 #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 121 #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 122 #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 123 #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 124 #define SDMA0_CHICKEN_BITS__SRAM_FGCG_ENABLE__SHIFT 0x1a 125 #define SDMA0_CHICKEN_BITS__RESERVED__SHIFT 0x1b 126 #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 127 #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 128 #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 129 #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 130 #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 131 #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 132 #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 133 #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 134 #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 135 #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 136 #define SDMA0_CHICKEN_BITS__SRAM_FGCG_ENABLE_MASK 0x04000000L 137 #define SDMA0_CHICKEN_BITS__RESERVED_MASK 0xF8000000L 138 //SDMA0_GB_ADDR_CONFIG 139 #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 140 #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 141 #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 142 #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 143 #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 144 #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 145 #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 146 #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 147 #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 148 #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 149 //SDMA0_GB_ADDR_CONFIG_READ 150 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 151 #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 152 #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 153 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 154 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 155 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 156 #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 157 #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 158 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 159 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 160 //SDMA0_RB_RPTR_FETCH_HI 161 #define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 162 #define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 163 //SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 164 #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 165 #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 166 //SDMA0_RB_RPTR_FETCH 167 #define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 168 #define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 169 //SDMA0_IB_OFFSET_FETCH 170 #define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 171 #define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 172 //SDMA0_PROGRAM 173 #define SDMA0_PROGRAM__STREAM__SHIFT 0x0 174 #define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL 175 //SDMA0_STATUS_REG 176 #define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 177 #define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 178 #define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 179 #define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 180 #define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 181 #define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 182 #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 183 #define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 184 #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 185 #define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 186 #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa 187 #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 188 #define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc 189 #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 190 #define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe 191 #define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 192 #define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 193 #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 194 #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 195 #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 196 #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 197 #define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 198 #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 199 #define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 200 #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a 201 #define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 202 #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 203 #define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e 204 #define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 205 #define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L 206 #define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L 207 #define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L 208 #define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L 209 #define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 210 #define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 211 #define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 212 #define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 213 #define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 214 #define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L 215 #define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L 216 #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 217 #define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L 218 #define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 219 #define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 220 #define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 221 #define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 222 #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 223 #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 224 #define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 225 #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 226 #define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 227 #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 228 #define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 229 #define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L 230 #define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 231 #define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 232 #define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L 233 #define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 234 //SDMA0_STATUS1_REG 235 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 236 #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 237 #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 238 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 239 #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 240 #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 241 #define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 242 #define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 243 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 244 #define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 245 #define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 246 #define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf 247 #define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 248 #define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 249 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 250 #define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 251 #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 252 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 253 #define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 254 #define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 255 #define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 256 #define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 257 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 258 #define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 259 #define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 260 #define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L 261 #define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 262 #define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 263 //SDMA0_RD_BURST_CNTL 264 #define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 265 #define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 266 #define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 267 #define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL 268 //SDMA0_HBM_PAGE_CONFIG 269 #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 270 #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L 271 //SDMA0_UCODE_CHECKSUM 272 #define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 273 #define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 274 //SDMA0_F32_CNTL 275 #define SDMA0_F32_CNTL__HALT__SHIFT 0x0 276 #define SDMA0_F32_CNTL__STEP__SHIFT 0x1 277 #define SDMA0_F32_CNTL__RESET__SHIFT 0x8 278 #define SDMA0_F32_CNTL__HALT_MASK 0x00000001L 279 #define SDMA0_F32_CNTL__STEP_MASK 0x00000002L 280 #define SDMA0_F32_CNTL__RESET_MASK 0x00000100L 281 //SDMA0_FREEZE 282 #define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 283 #define SDMA0_FREEZE__FREEZE__SHIFT 0x4 284 #define SDMA0_FREEZE__FROZEN__SHIFT 0x5 285 #define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 286 #define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L 287 #define SDMA0_FREEZE__FREEZE_MASK 0x00000010L 288 #define SDMA0_FREEZE__FROZEN_MASK 0x00000020L 289 #define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L 290 //SDMA0_PHASE0_QUANTUM 291 #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 292 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 293 #define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 294 #define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 295 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 296 #define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 297 //SDMA0_PHASE1_QUANTUM 298 #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 299 #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 300 #define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 301 #define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 302 #define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 303 #define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 304 //SDMA_POWER_GATING 305 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 306 #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 307 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 308 #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 309 #define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 310 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L 311 #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L 312 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L 313 #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L 314 #define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L 315 //SDMA_PGFSM_CONFIG 316 #define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 317 #define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 318 #define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 319 #define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa 320 #define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb 321 #define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc 322 #define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd 323 #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b 324 #define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c 325 #define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL 326 #define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L 327 #define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L 328 #define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L 329 #define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L 330 #define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L 331 #define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L 332 #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L 333 #define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L 334 //SDMA_PGFSM_WRITE 335 #define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 336 #define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL 337 //SDMA_PGFSM_READ 338 #define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 339 #define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL 340 //CC_SDMA0_EDC_CONFIG 341 #define CC_SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 342 #define CC_SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 343 //SDMA0_BA_THRESHOLD 344 #define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 345 #define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 346 #define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 347 #define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 348 //SDMA0_ID 349 #define SDMA0_ID__DEVICE_ID__SHIFT 0x0 350 #define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL 351 //SDMA0_VERSION 352 #define SDMA0_VERSION__MINVER__SHIFT 0x0 353 #define SDMA0_VERSION__MAJVER__SHIFT 0x8 354 #define SDMA0_VERSION__REV__SHIFT 0x10 355 #define SDMA0_VERSION__MINVER_MASK 0x0000007FL 356 #define SDMA0_VERSION__MAJVER_MASK 0x00007F00L 357 #define SDMA0_VERSION__REV_MASK 0x003F0000L 358 //SDMA0_EDC_COUNTER 359 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x0 360 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x2 361 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x4 362 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0x6 363 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0x8 364 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa 365 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xc 366 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 367 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0x10 368 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x12 369 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x14 370 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x16 371 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x18 372 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x1a 373 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x1c 374 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x1e 375 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000003L 376 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x0000000CL 377 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000030L 378 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x000000C0L 379 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000300L 380 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00000C00L 381 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00003000L 382 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x0000C000L 383 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00030000L 384 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x000C0000L 385 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00300000L 386 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00C00000L 387 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x03000000L 388 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x0C000000L 389 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x30000000L 390 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0xC0000000L 391 //SDMA0_EDC_COUNTER2 392 #define SDMA0_EDC_COUNTER2__SDMA_UCODE_BUF_SED__SHIFT 0x0 393 #define SDMA0_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 394 #define SDMA0_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED__SHIFT 0x4 395 #define SDMA0_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x6 396 #define SDMA0_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x8 397 #define SDMA0_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED__SHIFT 0xa 398 #define SDMA0_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED__SHIFT 0xc 399 #define SDMA0_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED__SHIFT 0xe 400 #define SDMA0_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 401 #define SDMA0_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED__SHIFT 0x12 402 #define SDMA0_EDC_COUNTER2__SDMA_UCODE_BUF_SED_MASK 0x00000003L 403 #define SDMA0_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED_MASK 0x0000000CL 404 #define SDMA0_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED_MASK 0x00000030L 405 #define SDMA0_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED_MASK 0x000000C0L 406 #define SDMA0_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000300L 407 #define SDMA0_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED_MASK 0x00000C00L 408 #define SDMA0_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED_MASK 0x00003000L 409 #define SDMA0_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED_MASK 0x0000C000L 410 #define SDMA0_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00030000L 411 #define SDMA0_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED_MASK 0x000C0000L 412 //SDMA0_STATUS2_REG 413 #define SDMA0_STATUS2_REG__ID__SHIFT 0x0 414 #define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 415 #define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 416 #define SDMA0_STATUS2_REG__ID_MASK 0x00000007L 417 #define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L 418 #define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 419 //SDMA0_ATOMIC_CNTL 420 #define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 421 #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 422 #define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 423 #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 424 //SDMA0_ATOMIC_PREOP_LO 425 #define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 426 #define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 427 //SDMA0_ATOMIC_PREOP_HI 428 #define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 429 #define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 430 //SDMA0_UTCL1_CNTL 431 #define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 432 #define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 433 #define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 434 #define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 435 #define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 436 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 437 #define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 438 #define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 439 #define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 440 #define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 441 #define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 442 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 443 //SDMA0_UTCL1_WATERMK 444 #define SDMA0_UTCL1_WATERMK__REQ_WATERMK__SHIFT 0x0 445 #define SDMA0_UTCL1_WATERMK__REQ_DEPTH__SHIFT 0x3 446 #define SDMA0_UTCL1_WATERMK__PAGE_WATERMK__SHIFT 0x5 447 #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x8 448 #define SDMA0_UTCL1_WATERMK__RESERVED__SHIFT 0x10 449 #define SDMA0_UTCL1_WATERMK__REQ_WATERMK_MASK 0x00000007L 450 #define SDMA0_UTCL1_WATERMK__REQ_DEPTH_MASK 0x00000018L 451 #define SDMA0_UTCL1_WATERMK__PAGE_WATERMK_MASK 0x000000E0L 452 #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x0000FF00L 453 #define SDMA0_UTCL1_WATERMK__RESERVED_MASK 0xFFFF0000L 454 //SDMA0_UTCL1_RD_STATUS 455 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 456 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 457 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 458 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 459 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 460 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 461 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 462 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 463 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 464 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 465 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 466 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 467 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 468 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 469 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 470 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 471 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 472 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 473 #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 474 #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 475 #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 476 #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 477 #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 478 #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 479 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 480 #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 481 #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 482 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 483 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 484 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 485 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 486 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 487 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 488 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 489 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 490 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 491 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 492 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 493 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 494 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 495 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 496 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 497 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 498 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 499 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 500 #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 501 #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 502 #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 503 #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 504 #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 505 #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 506 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 507 #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 508 #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 509 //SDMA0_UTCL1_WR_STATUS 510 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 511 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 512 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 513 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 514 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 515 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 516 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 517 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 518 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 519 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 520 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 521 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 522 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 523 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 524 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 525 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 526 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 527 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 528 #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 529 #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 530 #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 531 #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 532 #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 533 #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 534 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 535 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 536 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 537 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 538 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 539 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 540 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 541 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 542 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 543 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 544 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 545 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 546 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 547 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 548 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 549 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 550 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 551 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 552 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 553 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 554 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 555 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 556 #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 557 #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 558 #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 559 #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 560 #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 561 #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 562 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 563 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 564 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 565 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 566 //SDMA0_UTCL1_INV0 567 #define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 568 #define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 569 #define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 570 #define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 571 #define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 572 #define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 573 #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 574 #define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 575 #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 576 #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 577 #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 578 #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 579 #define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 580 #define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 581 #define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 582 #define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 583 #define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 584 #define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 585 #define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 586 #define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 587 #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 588 #define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 589 #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 590 #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 591 #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 592 #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 593 #define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 594 #define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 595 //SDMA0_UTCL1_INV1 596 #define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 597 #define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 598 //SDMA0_UTCL1_INV2 599 #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 600 #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 601 //SDMA0_UTCL1_RD_XNACK0 602 #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 603 #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 604 //SDMA0_UTCL1_RD_XNACK1 605 #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 606 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 607 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 608 #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 609 #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 610 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 611 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 612 #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 613 //SDMA0_UTCL1_WR_XNACK0 614 #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 615 #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 616 //SDMA0_UTCL1_WR_XNACK1 617 #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 618 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 619 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 620 #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 621 #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 622 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 623 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 624 #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 625 //SDMA0_UTCL1_TIMEOUT 626 #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 627 #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 628 #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 629 #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 630 //SDMA0_UTCL1_PAGE 631 #define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 632 #define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 633 #define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 634 #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 635 #define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 636 #define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 637 #define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 638 #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 639 //SDMA0_POWER_CNTL_IDLE 640 #define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 641 #define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 642 #define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 643 #define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 644 #define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 645 #define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 646 //SDMA0_RELAX_ORDERING_LUT 647 #define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 648 #define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 649 #define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 650 #define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 651 #define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 652 #define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 653 #define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 654 #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 655 #define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 656 #define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 657 #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 658 #define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 659 #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 660 #define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 661 #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 662 #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 663 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 664 #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 665 #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 666 #define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 667 #define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 668 #define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 669 #define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 670 #define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 671 #define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 672 #define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 673 #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 674 #define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 675 #define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 676 #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 677 #define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 678 #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 679 #define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 680 #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 681 #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 682 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 683 #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 684 #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 685 //SDMA0_CHICKEN_BITS_2 686 #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 687 #define SDMA0_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x4 688 #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 689 #define SDMA0_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00000010L 690 //SDMA0_STATUS3_REG 691 #define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 692 #define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 693 #define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 694 #define SDMA0_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 695 #define SDMA0_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 696 #define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 697 #define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 698 #define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 699 #define SDMA0_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L 700 #define SDMA0_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L 701 //SDMA0_PHYSICAL_ADDR_LO 702 #define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 703 #define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 704 #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 705 #define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 706 #define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 707 #define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 708 #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 709 #define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 710 //SDMA0_PHYSICAL_ADDR_HI 711 #define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 712 #define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 713 //SDMA0_PHASE2_QUANTUM 714 #define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0 715 #define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8 716 #define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 717 #define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 718 #define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 719 #define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 720 //SDMA0_ERROR_LOG 721 #define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 722 #define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 723 #define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 724 #define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L 725 //SDMA0_PUB_DUMMY_REG0 726 #define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 727 #define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 728 //SDMA0_PUB_DUMMY_REG1 729 #define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 730 #define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 731 //SDMA0_PUB_DUMMY_REG2 732 #define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 733 #define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 734 //SDMA0_PUB_DUMMY_REG3 735 #define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 736 #define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 737 //SDMA0_F32_COUNTER 738 #define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 739 #define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 740 //SDMA0_PERFCNT_PERFCOUNTER0_CFG 741 #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 742 #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 743 #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 744 #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 745 #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 746 #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 747 #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 748 #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 749 #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 750 #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 751 //SDMA0_PERFCNT_PERFCOUNTER1_CFG 752 #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 753 #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 754 #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 755 #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 756 #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 757 #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 758 #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 759 #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 760 #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 761 #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 762 //SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL 763 #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 764 #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 765 #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 766 #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 767 #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 768 #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 769 #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 770 #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 771 #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 772 #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 773 #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 774 #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 775 //SDMA0_PERFCNT_MISC_CNTL 776 #define SDMA0_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 777 #define SDMA0_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL 778 //SDMA0_PERFCNT_PERFCOUNTER_LO 779 #define SDMA0_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 780 #define SDMA0_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 781 //SDMA0_PERFCNT_PERFCOUNTER_HI 782 #define SDMA0_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 783 #define SDMA0_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 784 #define SDMA0_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 785 #define SDMA0_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 786 //SDMA0_CRD_CNTL 787 #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 788 #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 789 #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 790 #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 791 //SDMA0_ULV_CNTL 792 #define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 793 #define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b 794 #define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c 795 #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 796 #define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 797 #define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 798 #define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 799 #define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L 800 #define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L 801 #define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 802 #define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 803 #define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 804 //SDMA0_EA_DBIT_ADDR_DATA 805 #define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 806 #define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 807 //SDMA0_EA_DBIT_ADDR_INDEX 808 #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 809 #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 810 //SDMA0_STATUS4_REG 811 #define SDMA0_STATUS4_REG__IDLE__SHIFT 0x0 812 #define SDMA0_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2 813 #define SDMA0_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3 814 #define SDMA0_STATUS4_REG__MMHUB_RD_OUTSTANDING__SHIFT 0x4 815 #define SDMA0_STATUS4_REG__MMHUB_WR_OUTSTANDING__SHIFT 0x5 816 #define SDMA0_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x6 817 #define SDMA0_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x7 818 #define SDMA0_STATUS4_REG__REG_POLLING__SHIFT 0x8 819 #define SDMA0_STATUS4_REG__MEM_POLLING__SHIFT 0x9 820 #define SDMA0_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xa 821 #define SDMA0_STATUS4_REG__UTCL2_WR_XNACK__SHIFT 0xc 822 #define SDMA0_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0xe 823 #define SDMA0_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x12 824 #define SDMA0_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x13 825 #define SDMA0_STATUS4_REG__IDLE_MASK 0x00000001L 826 #define SDMA0_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L 827 #define SDMA0_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L 828 #define SDMA0_STATUS4_REG__MMHUB_RD_OUTSTANDING_MASK 0x00000010L 829 #define SDMA0_STATUS4_REG__MMHUB_WR_OUTSTANDING_MASK 0x00000020L 830 #define SDMA0_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000040L 831 #define SDMA0_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000080L 832 #define SDMA0_STATUS4_REG__REG_POLLING_MASK 0x00000100L 833 #define SDMA0_STATUS4_REG__MEM_POLLING_MASK 0x00000200L 834 #define SDMA0_STATUS4_REG__UTCL2_RD_XNACK_MASK 0x00000C00L 835 #define SDMA0_STATUS4_REG__UTCL2_WR_XNACK_MASK 0x00003000L 836 #define SDMA0_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x0003C000L 837 #define SDMA0_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00040000L 838 #define SDMA0_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00080000L 839 //SDMA0_SCRATCH_RAM_DATA 840 #define SDMA0_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 841 #define SDMA0_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL 842 //SDMA0_SCRATCH_RAM_ADDR 843 #define SDMA0_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 844 #define SDMA0_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL 845 //SDMA0_CE_CTRL 846 #define SDMA0_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 847 #define SDMA0_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 848 #define SDMA0_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5 849 #define SDMA0_CE_CTRL__RESERVED__SHIFT 0x8 850 #define SDMA0_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L 851 #define SDMA0_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L 852 #define SDMA0_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L 853 #define SDMA0_CE_CTRL__RESERVED_MASK 0xFFFFFF00L 854 //SDMA0_RAS_STATUS 855 #define SDMA0_RAS_STATUS__RB_FETCH_ECC__SHIFT 0x0 856 #define SDMA0_RAS_STATUS__IB_FETCH_ECC__SHIFT 0x1 857 #define SDMA0_RAS_STATUS__F32_DATA_ECC__SHIFT 0x2 858 #define SDMA0_RAS_STATUS__SEM_WPTR_ATOMIC_ECC__SHIFT 0x3 859 #define SDMA0_RAS_STATUS__COPY_DATA_ECC__SHIFT 0x4 860 #define SDMA0_RAS_STATUS__SRAM_ECC__SHIFT 0x5 861 #define SDMA0_RAS_STATUS__RB_FETCH_NACK_GEN_ERR__SHIFT 0x8 862 #define SDMA0_RAS_STATUS__IB_FETCH_NACK_GEN_ERR__SHIFT 0x9 863 #define SDMA0_RAS_STATUS__F32_DATA_NACK_GEN_ERR__SHIFT 0xa 864 #define SDMA0_RAS_STATUS__COPY_DATA_NACK_GEN_ERR__SHIFT 0xb 865 #define SDMA0_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR__SHIFT 0xc 866 #define SDMA0_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR__SHIFT 0xd 867 #define SDMA0_RAS_STATUS__RB_FETCH_ECC_MASK 0x00000001L 868 #define SDMA0_RAS_STATUS__IB_FETCH_ECC_MASK 0x00000002L 869 #define SDMA0_RAS_STATUS__F32_DATA_ECC_MASK 0x00000004L 870 #define SDMA0_RAS_STATUS__SEM_WPTR_ATOMIC_ECC_MASK 0x00000008L 871 #define SDMA0_RAS_STATUS__COPY_DATA_ECC_MASK 0x00000010L 872 #define SDMA0_RAS_STATUS__SRAM_ECC_MASK 0x00000020L 873 #define SDMA0_RAS_STATUS__RB_FETCH_NACK_GEN_ERR_MASK 0x00000100L 874 #define SDMA0_RAS_STATUS__IB_FETCH_NACK_GEN_ERR_MASK 0x00000200L 875 #define SDMA0_RAS_STATUS__F32_DATA_NACK_GEN_ERR_MASK 0x00000400L 876 #define SDMA0_RAS_STATUS__COPY_DATA_NACK_GEN_ERR_MASK 0x00000800L 877 #define SDMA0_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR_MASK 0x00001000L 878 #define SDMA0_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR_MASK 0x00002000L 879 //SDMA0_CLK_STATUS 880 #define SDMA0_CLK_STATUS__DYN_CLK__SHIFT 0x0 881 #define SDMA0_CLK_STATUS__PTR_CLK__SHIFT 0x1 882 #define SDMA0_CLK_STATUS__REG_CLK__SHIFT 0x2 883 #define SDMA0_CLK_STATUS__F32_CLK__SHIFT 0x3 884 #define SDMA0_CLK_STATUS__DYN_CLK_MASK 0x00000001L 885 #define SDMA0_CLK_STATUS__PTR_CLK_MASK 0x00000002L 886 #define SDMA0_CLK_STATUS__REG_CLK_MASK 0x00000004L 887 #define SDMA0_CLK_STATUS__F32_CLK_MASK 0x00000008L 888 //SDMA0_GFX_RB_CNTL 889 #define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 890 #define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 891 #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 892 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 893 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 894 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 895 #define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 896 #define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 897 #define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 898 #define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL 899 #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 900 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 901 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 902 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 903 #define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 904 #define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 905 //SDMA0_GFX_RB_BASE 906 #define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 907 #define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 908 //SDMA0_GFX_RB_BASE_HI 909 #define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 910 #define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 911 //SDMA0_GFX_RB_RPTR 912 #define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 913 #define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 914 //SDMA0_GFX_RB_RPTR_HI 915 #define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 916 #define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 917 //SDMA0_GFX_RB_WPTR 918 #define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 919 #define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 920 //SDMA0_GFX_RB_WPTR_HI 921 #define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 922 #define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 923 //SDMA0_GFX_RB_WPTR_POLL_CNTL 924 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 925 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 926 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 927 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 928 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 929 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 930 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 931 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 932 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 933 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 934 //SDMA0_GFX_RB_RPTR_ADDR_HI 935 #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 936 #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 937 //SDMA0_GFX_RB_RPTR_ADDR_LO 938 #define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 939 #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 940 #define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 941 #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 942 //SDMA0_GFX_IB_CNTL 943 #define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 944 #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 945 #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 946 #define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 947 #define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 948 #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 949 #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 950 #define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 951 //SDMA0_GFX_IB_RPTR 952 #define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 953 #define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 954 //SDMA0_GFX_IB_OFFSET 955 #define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 956 #define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 957 //SDMA0_GFX_IB_BASE_LO 958 #define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 959 #define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 960 //SDMA0_GFX_IB_BASE_HI 961 #define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 962 #define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 963 //SDMA0_GFX_IB_SIZE 964 #define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 965 #define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 966 //SDMA0_GFX_SKIP_CNTL 967 #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 968 #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 969 //SDMA0_GFX_CONTEXT_STATUS 970 #define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 971 #define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 972 #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 973 #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 974 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 975 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 976 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 977 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 978 #define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 979 #define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 980 #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 981 #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 982 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 983 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 984 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 985 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 986 //SDMA0_GFX_DOORBELL 987 #define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c 988 #define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 989 #define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L 990 #define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 991 //SDMA0_GFX_CONTEXT_CNTL 992 #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 993 #define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 994 #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 995 #define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0x0F000000L 996 //SDMA0_GFX_STATUS 997 #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 998 #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 999 #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1000 #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1001 //SDMA0_GFX_DOORBELL_LOG 1002 #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1003 #define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 1004 #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1005 #define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1006 //SDMA0_GFX_WATERMARK 1007 #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1008 #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1009 #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1010 #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1011 //SDMA0_GFX_DOORBELL_OFFSET 1012 #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1013 #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1014 //SDMA0_GFX_CSA_ADDR_LO 1015 #define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 1016 #define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1017 //SDMA0_GFX_CSA_ADDR_HI 1018 #define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 1019 #define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1020 //SDMA0_GFX_IB_SUB_REMAIN 1021 #define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1022 #define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1023 //SDMA0_GFX_PREEMPT 1024 #define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 1025 #define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1026 //SDMA0_GFX_DUMMY_REG 1027 #define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 1028 #define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1029 //SDMA0_GFX_RB_WPTR_POLL_ADDR_HI 1030 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1031 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1032 //SDMA0_GFX_RB_WPTR_POLL_ADDR_LO 1033 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1034 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1035 //SDMA0_GFX_RB_AQL_CNTL 1036 #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1037 #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1038 #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1039 #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1040 #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1041 #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1042 //SDMA0_GFX_MINOR_PTR_UPDATE 1043 #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1044 #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1045 //SDMA0_GFX_MIDCMD_DATA0 1046 #define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 1047 #define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1048 //SDMA0_GFX_MIDCMD_DATA1 1049 #define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 1050 #define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1051 //SDMA0_GFX_MIDCMD_DATA2 1052 #define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 1053 #define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1054 //SDMA0_GFX_MIDCMD_DATA3 1055 #define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 1056 #define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1057 //SDMA0_GFX_MIDCMD_DATA4 1058 #define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 1059 #define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1060 //SDMA0_GFX_MIDCMD_DATA5 1061 #define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 1062 #define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1063 //SDMA0_GFX_MIDCMD_DATA6 1064 #define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 1065 #define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1066 //SDMA0_GFX_MIDCMD_DATA7 1067 #define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 1068 #define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1069 //SDMA0_GFX_MIDCMD_DATA8 1070 #define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 1071 #define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1072 //SDMA0_GFX_MIDCMD_DATA9 1073 #define SDMA0_GFX_MIDCMD_DATA9__DATA9__SHIFT 0x0 1074 #define SDMA0_GFX_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 1075 //SDMA0_GFX_MIDCMD_DATA10 1076 #define SDMA0_GFX_MIDCMD_DATA10__DATA10__SHIFT 0x0 1077 #define SDMA0_GFX_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 1078 //SDMA0_GFX_MIDCMD_CNTL 1079 #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1080 #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1081 #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1082 #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1083 #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1084 #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1085 #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1086 #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1087 //SDMA0_PAGE_RB_CNTL 1088 #define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 1089 #define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 1090 #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1091 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1092 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1093 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1094 #define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 1095 #define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 1096 #define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1097 #define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1098 #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1099 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1100 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1101 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1102 #define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 1103 #define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 1104 //SDMA0_PAGE_RB_BASE 1105 #define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0 1106 #define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1107 //SDMA0_PAGE_RB_BASE_HI 1108 #define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 1109 #define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1110 //SDMA0_PAGE_RB_RPTR 1111 #define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 1112 #define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1113 //SDMA0_PAGE_RB_RPTR_HI 1114 #define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 1115 #define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1116 //SDMA0_PAGE_RB_WPTR 1117 #define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 1118 #define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1119 //SDMA0_PAGE_RB_WPTR_HI 1120 #define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 1121 #define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1122 //SDMA0_PAGE_RB_WPTR_POLL_CNTL 1123 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1124 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1125 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1126 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1127 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1128 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1129 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1130 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1131 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1132 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1133 //SDMA0_PAGE_RB_RPTR_ADDR_HI 1134 #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1135 #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1136 //SDMA0_PAGE_RB_RPTR_ADDR_LO 1137 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1138 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1139 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1140 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1141 //SDMA0_PAGE_IB_CNTL 1142 #define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 1143 #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1144 #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1145 #define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 1146 #define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1147 #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1148 #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1149 #define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1150 //SDMA0_PAGE_IB_RPTR 1151 #define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 1152 #define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1153 //SDMA0_PAGE_IB_OFFSET 1154 #define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 1155 #define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1156 //SDMA0_PAGE_IB_BASE_LO 1157 #define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 1158 #define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1159 //SDMA0_PAGE_IB_BASE_HI 1160 #define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 1161 #define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1162 //SDMA0_PAGE_IB_SIZE 1163 #define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0 1164 #define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 1165 //SDMA0_PAGE_SKIP_CNTL 1166 #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1167 #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1168 //SDMA0_PAGE_CONTEXT_STATUS 1169 #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1170 #define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 1171 #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1172 #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1173 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1174 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1175 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1176 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1177 #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1178 #define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1179 #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1180 #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1181 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1182 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1183 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1184 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1185 //SDMA0_PAGE_DOORBELL 1186 #define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 1187 #define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 1188 #define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 1189 #define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 1190 //SDMA0_PAGE_STATUS 1191 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1192 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1193 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1194 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1195 //SDMA0_PAGE_DOORBELL_LOG 1196 #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1197 #define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 1198 #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1199 #define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1200 //SDMA0_PAGE_WATERMARK 1201 #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1202 #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1203 #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1204 #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1205 //SDMA0_PAGE_DOORBELL_OFFSET 1206 #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1207 #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1208 //SDMA0_PAGE_CSA_ADDR_LO 1209 #define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 1210 #define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1211 //SDMA0_PAGE_CSA_ADDR_HI 1212 #define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 1213 #define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1214 //SDMA0_PAGE_IB_SUB_REMAIN 1215 #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1216 #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1217 //SDMA0_PAGE_PREEMPT 1218 #define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 1219 #define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1220 //SDMA0_PAGE_DUMMY_REG 1221 #define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 1222 #define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1223 //SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 1224 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1225 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1226 //SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 1227 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1228 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1229 //SDMA0_PAGE_RB_AQL_CNTL 1230 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1231 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1232 #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1233 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1234 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1235 #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1236 //SDMA0_PAGE_MINOR_PTR_UPDATE 1237 #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1238 #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1239 //SDMA0_PAGE_MIDCMD_DATA0 1240 #define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 1241 #define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1242 //SDMA0_PAGE_MIDCMD_DATA1 1243 #define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 1244 #define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1245 //SDMA0_PAGE_MIDCMD_DATA2 1246 #define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 1247 #define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1248 //SDMA0_PAGE_MIDCMD_DATA3 1249 #define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 1250 #define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1251 //SDMA0_PAGE_MIDCMD_DATA4 1252 #define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 1253 #define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1254 //SDMA0_PAGE_MIDCMD_DATA5 1255 #define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 1256 #define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1257 //SDMA0_PAGE_MIDCMD_DATA6 1258 #define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 1259 #define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1260 //SDMA0_PAGE_MIDCMD_DATA7 1261 #define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 1262 #define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1263 //SDMA0_PAGE_MIDCMD_DATA8 1264 #define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 1265 #define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1266 //SDMA0_PAGE_MIDCMD_DATA9 1267 #define SDMA0_PAGE_MIDCMD_DATA9__DATA9__SHIFT 0x0 1268 #define SDMA0_PAGE_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 1269 //SDMA0_PAGE_MIDCMD_DATA10 1270 #define SDMA0_PAGE_MIDCMD_DATA10__DATA10__SHIFT 0x0 1271 #define SDMA0_PAGE_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 1272 //SDMA0_PAGE_MIDCMD_CNTL 1273 #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1274 #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1275 #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1276 #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1277 #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1278 #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1279 #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1280 #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1281 //SDMA0_RLC0_RB_CNTL 1282 #define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1283 #define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 1284 #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1285 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1286 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1287 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1288 #define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 1289 #define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 1290 #define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1291 #define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1292 #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1293 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1294 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1295 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1296 #define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 1297 #define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 1298 //SDMA0_RLC0_RB_BASE 1299 #define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 1300 #define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1301 //SDMA0_RLC0_RB_BASE_HI 1302 #define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 1303 #define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1304 //SDMA0_RLC0_RB_RPTR 1305 #define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 1306 #define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1307 //SDMA0_RLC0_RB_RPTR_HI 1308 #define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 1309 #define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1310 //SDMA0_RLC0_RB_WPTR 1311 #define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 1312 #define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1313 //SDMA0_RLC0_RB_WPTR_HI 1314 #define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 1315 #define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1316 //SDMA0_RLC0_RB_WPTR_POLL_CNTL 1317 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1318 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1319 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1320 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1321 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1322 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1323 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1324 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1325 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1326 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1327 //SDMA0_RLC0_RB_RPTR_ADDR_HI 1328 #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1329 #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1330 //SDMA0_RLC0_RB_RPTR_ADDR_LO 1331 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1332 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1333 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1334 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1335 //SDMA0_RLC0_IB_CNTL 1336 #define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1337 #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1338 #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1339 #define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 1340 #define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1341 #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1342 #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1343 #define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1344 //SDMA0_RLC0_IB_RPTR 1345 #define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 1346 #define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1347 //SDMA0_RLC0_IB_OFFSET 1348 #define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 1349 #define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1350 //SDMA0_RLC0_IB_BASE_LO 1351 #define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 1352 #define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1353 //SDMA0_RLC0_IB_BASE_HI 1354 #define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 1355 #define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1356 //SDMA0_RLC0_IB_SIZE 1357 #define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 1358 #define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 1359 //SDMA0_RLC0_SKIP_CNTL 1360 #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1361 #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1362 //SDMA0_RLC0_CONTEXT_STATUS 1363 #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1364 #define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1365 #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1366 #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1367 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1368 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1369 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1370 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1371 #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1372 #define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1373 #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1374 #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1375 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1376 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1377 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1378 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1379 //SDMA0_RLC0_DOORBELL 1380 #define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 1381 #define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 1382 #define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 1383 #define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 1384 //SDMA0_RLC0_STATUS 1385 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1386 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1387 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1388 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1389 //SDMA0_RLC0_DOORBELL_LOG 1390 #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1391 #define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 1392 #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1393 #define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1394 //SDMA0_RLC0_WATERMARK 1395 #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1396 #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1397 #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1398 #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1399 //SDMA0_RLC0_DOORBELL_OFFSET 1400 #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1401 #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1402 //SDMA0_RLC0_CSA_ADDR_LO 1403 #define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1404 #define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1405 //SDMA0_RLC0_CSA_ADDR_HI 1406 #define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1407 #define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1408 //SDMA0_RLC0_IB_SUB_REMAIN 1409 #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1410 #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1411 //SDMA0_RLC0_PREEMPT 1412 #define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1413 #define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1414 //SDMA0_RLC0_DUMMY_REG 1415 #define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 1416 #define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1417 //SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 1418 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1419 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1420 //SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 1421 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1422 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1423 //SDMA0_RLC0_RB_AQL_CNTL 1424 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1425 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1426 #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1427 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1428 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1429 #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1430 //SDMA0_RLC0_MINOR_PTR_UPDATE 1431 #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1432 #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1433 //SDMA0_RLC0_MIDCMD_DATA0 1434 #define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1435 #define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1436 //SDMA0_RLC0_MIDCMD_DATA1 1437 #define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1438 #define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1439 //SDMA0_RLC0_MIDCMD_DATA2 1440 #define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1441 #define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1442 //SDMA0_RLC0_MIDCMD_DATA3 1443 #define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1444 #define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1445 //SDMA0_RLC0_MIDCMD_DATA4 1446 #define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1447 #define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1448 //SDMA0_RLC0_MIDCMD_DATA5 1449 #define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1450 #define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1451 //SDMA0_RLC0_MIDCMD_DATA6 1452 #define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1453 #define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1454 //SDMA0_RLC0_MIDCMD_DATA7 1455 #define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1456 #define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1457 //SDMA0_RLC0_MIDCMD_DATA8 1458 #define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1459 #define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1460 //SDMA0_RLC0_MIDCMD_DATA9 1461 #define SDMA0_RLC0_MIDCMD_DATA9__DATA9__SHIFT 0x0 1462 #define SDMA0_RLC0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 1463 //SDMA0_RLC0_MIDCMD_DATA10 1464 #define SDMA0_RLC0_MIDCMD_DATA10__DATA10__SHIFT 0x0 1465 #define SDMA0_RLC0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 1466 //SDMA0_RLC0_MIDCMD_CNTL 1467 #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1468 #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1469 #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1470 #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1471 #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1472 #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1473 #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1474 #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1475 //SDMA0_RLC1_RB_CNTL 1476 #define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1477 #define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 1478 #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1479 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1480 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1481 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1482 #define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 1483 #define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 1484 #define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1485 #define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1486 #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1487 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1488 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1489 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1490 #define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 1491 #define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 1492 //SDMA0_RLC1_RB_BASE 1493 #define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 1494 #define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1495 //SDMA0_RLC1_RB_BASE_HI 1496 #define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 1497 #define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1498 //SDMA0_RLC1_RB_RPTR 1499 #define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 1500 #define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1501 //SDMA0_RLC1_RB_RPTR_HI 1502 #define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1503 #define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1504 //SDMA0_RLC1_RB_WPTR 1505 #define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 1506 #define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1507 //SDMA0_RLC1_RB_WPTR_HI 1508 #define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1509 #define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1510 //SDMA0_RLC1_RB_WPTR_POLL_CNTL 1511 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1512 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1513 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1514 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1515 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1516 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1517 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1518 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1519 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1520 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1521 //SDMA0_RLC1_RB_RPTR_ADDR_HI 1522 #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1523 #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1524 //SDMA0_RLC1_RB_RPTR_ADDR_LO 1525 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1526 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1527 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1528 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1529 //SDMA0_RLC1_IB_CNTL 1530 #define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1531 #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1532 #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1533 #define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 1534 #define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1535 #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1536 #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1537 #define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1538 //SDMA0_RLC1_IB_RPTR 1539 #define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 1540 #define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1541 //SDMA0_RLC1_IB_OFFSET 1542 #define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 1543 #define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1544 //SDMA0_RLC1_IB_BASE_LO 1545 #define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 1546 #define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1547 //SDMA0_RLC1_IB_BASE_HI 1548 #define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 1549 #define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1550 //SDMA0_RLC1_IB_SIZE 1551 #define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 1552 #define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1553 //SDMA0_RLC1_SKIP_CNTL 1554 #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1555 #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1556 //SDMA0_RLC1_CONTEXT_STATUS 1557 #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1558 #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1559 #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1560 #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1561 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1562 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1563 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1564 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1565 #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1566 #define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1567 #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1568 #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1569 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1570 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1571 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1572 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1573 //SDMA0_RLC1_DOORBELL 1574 #define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 1575 #define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 1576 #define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 1577 #define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 1578 //SDMA0_RLC1_STATUS 1579 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1580 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1581 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1582 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1583 //SDMA0_RLC1_DOORBELL_LOG 1584 #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1585 #define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 1586 #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1587 #define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1588 //SDMA0_RLC1_WATERMARK 1589 #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1590 #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1591 #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1592 #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1593 //SDMA0_RLC1_DOORBELL_OFFSET 1594 #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1595 #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1596 //SDMA0_RLC1_CSA_ADDR_LO 1597 #define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 1598 #define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1599 //SDMA0_RLC1_CSA_ADDR_HI 1600 #define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1601 #define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1602 //SDMA0_RLC1_IB_SUB_REMAIN 1603 #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1604 #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1605 //SDMA0_RLC1_PREEMPT 1606 #define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1607 #define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1608 //SDMA0_RLC1_DUMMY_REG 1609 #define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 1610 #define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1611 //SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 1612 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1613 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1614 //SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 1615 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1616 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1617 //SDMA0_RLC1_RB_AQL_CNTL 1618 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1619 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1620 #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1621 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1622 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1623 #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1624 //SDMA0_RLC1_MINOR_PTR_UPDATE 1625 #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1626 #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1627 //SDMA0_RLC1_MIDCMD_DATA0 1628 #define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 1629 #define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1630 //SDMA0_RLC1_MIDCMD_DATA1 1631 #define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 1632 #define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1633 //SDMA0_RLC1_MIDCMD_DATA2 1634 #define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 1635 #define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1636 //SDMA0_RLC1_MIDCMD_DATA3 1637 #define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 1638 #define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1639 //SDMA0_RLC1_MIDCMD_DATA4 1640 #define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 1641 #define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1642 //SDMA0_RLC1_MIDCMD_DATA5 1643 #define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 1644 #define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1645 //SDMA0_RLC1_MIDCMD_DATA6 1646 #define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 1647 #define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1648 //SDMA0_RLC1_MIDCMD_DATA7 1649 #define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 1650 #define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1651 //SDMA0_RLC1_MIDCMD_DATA8 1652 #define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 1653 #define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1654 //SDMA0_RLC1_MIDCMD_DATA9 1655 #define SDMA0_RLC1_MIDCMD_DATA9__DATA9__SHIFT 0x0 1656 #define SDMA0_RLC1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 1657 //SDMA0_RLC1_MIDCMD_DATA10 1658 #define SDMA0_RLC1_MIDCMD_DATA10__DATA10__SHIFT 0x0 1659 #define SDMA0_RLC1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 1660 //SDMA0_RLC1_MIDCMD_CNTL 1661 #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1662 #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1663 #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1664 #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1665 #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1666 #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1667 #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1668 #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1669 //SDMA0_RLC2_RB_CNTL 1670 #define SDMA0_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 1671 #define SDMA0_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 1672 #define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1673 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1674 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1675 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1676 #define SDMA0_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 1677 #define SDMA0_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 1678 #define SDMA0_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1679 #define SDMA0_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1680 #define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1681 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1682 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1683 #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1684 #define SDMA0_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L 1685 #define SDMA0_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L 1686 //SDMA0_RLC2_RB_BASE 1687 #define SDMA0_RLC2_RB_BASE__ADDR__SHIFT 0x0 1688 #define SDMA0_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1689 //SDMA0_RLC2_RB_BASE_HI 1690 #define SDMA0_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 1691 #define SDMA0_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1692 //SDMA0_RLC2_RB_RPTR 1693 #define SDMA0_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 1694 #define SDMA0_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1695 //SDMA0_RLC2_RB_RPTR_HI 1696 #define SDMA0_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 1697 #define SDMA0_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1698 //SDMA0_RLC2_RB_WPTR 1699 #define SDMA0_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 1700 #define SDMA0_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1701 //SDMA0_RLC2_RB_WPTR_HI 1702 #define SDMA0_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 1703 #define SDMA0_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1704 //SDMA0_RLC2_RB_WPTR_POLL_CNTL 1705 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1706 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1707 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1708 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1709 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1710 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1711 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1712 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1713 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1714 #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1715 //SDMA0_RLC2_RB_RPTR_ADDR_HI 1716 #define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1717 #define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1718 //SDMA0_RLC2_RB_RPTR_ADDR_LO 1719 #define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1720 #define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1721 #define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1722 #define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1723 //SDMA0_RLC2_IB_CNTL 1724 #define SDMA0_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 1725 #define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1726 #define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1727 #define SDMA0_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 1728 #define SDMA0_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1729 #define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1730 #define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1731 #define SDMA0_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1732 //SDMA0_RLC2_IB_RPTR 1733 #define SDMA0_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 1734 #define SDMA0_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1735 //SDMA0_RLC2_IB_OFFSET 1736 #define SDMA0_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 1737 #define SDMA0_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1738 //SDMA0_RLC2_IB_BASE_LO 1739 #define SDMA0_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 1740 #define SDMA0_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1741 //SDMA0_RLC2_IB_BASE_HI 1742 #define SDMA0_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 1743 #define SDMA0_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1744 //SDMA0_RLC2_IB_SIZE 1745 #define SDMA0_RLC2_IB_SIZE__SIZE__SHIFT 0x0 1746 #define SDMA0_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL 1747 //SDMA0_RLC2_SKIP_CNTL 1748 #define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1749 #define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1750 //SDMA0_RLC2_CONTEXT_STATUS 1751 #define SDMA0_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1752 #define SDMA0_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 1753 #define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1754 #define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1755 #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1756 #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1757 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1758 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1759 #define SDMA0_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1760 #define SDMA0_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1761 #define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1762 #define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1763 #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1764 #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1765 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1766 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1767 //SDMA0_RLC2_DOORBELL 1768 #define SDMA0_RLC2_DOORBELL__ENABLE__SHIFT 0x1c 1769 #define SDMA0_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e 1770 #define SDMA0_RLC2_DOORBELL__ENABLE_MASK 0x10000000L 1771 #define SDMA0_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L 1772 //SDMA0_RLC2_STATUS 1773 #define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1774 #define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1775 #define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1776 #define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1777 //SDMA0_RLC2_DOORBELL_LOG 1778 #define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1779 #define SDMA0_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 1780 #define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1781 #define SDMA0_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1782 //SDMA0_RLC2_WATERMARK 1783 #define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1784 #define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1785 #define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1786 #define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1787 //SDMA0_RLC2_DOORBELL_OFFSET 1788 #define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1789 #define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1790 //SDMA0_RLC2_CSA_ADDR_LO 1791 #define SDMA0_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 1792 #define SDMA0_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1793 //SDMA0_RLC2_CSA_ADDR_HI 1794 #define SDMA0_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 1795 #define SDMA0_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1796 //SDMA0_RLC2_IB_SUB_REMAIN 1797 #define SDMA0_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1798 #define SDMA0_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1799 //SDMA0_RLC2_PREEMPT 1800 #define SDMA0_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 1801 #define SDMA0_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1802 //SDMA0_RLC2_DUMMY_REG 1803 #define SDMA0_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 1804 #define SDMA0_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1805 //SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI 1806 #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1807 #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1808 //SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO 1809 #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1810 #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1811 //SDMA0_RLC2_RB_AQL_CNTL 1812 #define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1813 #define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1814 #define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1815 #define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1816 #define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1817 #define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1818 //SDMA0_RLC2_MINOR_PTR_UPDATE 1819 #define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1820 #define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1821 //SDMA0_RLC2_MIDCMD_DATA0 1822 #define SDMA0_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 1823 #define SDMA0_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1824 //SDMA0_RLC2_MIDCMD_DATA1 1825 #define SDMA0_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 1826 #define SDMA0_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1827 //SDMA0_RLC2_MIDCMD_DATA2 1828 #define SDMA0_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 1829 #define SDMA0_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1830 //SDMA0_RLC2_MIDCMD_DATA3 1831 #define SDMA0_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 1832 #define SDMA0_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1833 //SDMA0_RLC2_MIDCMD_DATA4 1834 #define SDMA0_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 1835 #define SDMA0_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1836 //SDMA0_RLC2_MIDCMD_DATA5 1837 #define SDMA0_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 1838 #define SDMA0_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1839 //SDMA0_RLC2_MIDCMD_DATA6 1840 #define SDMA0_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 1841 #define SDMA0_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1842 //SDMA0_RLC2_MIDCMD_DATA7 1843 #define SDMA0_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 1844 #define SDMA0_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1845 //SDMA0_RLC2_MIDCMD_DATA8 1846 #define SDMA0_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 1847 #define SDMA0_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1848 //SDMA0_RLC2_MIDCMD_DATA9 1849 #define SDMA0_RLC2_MIDCMD_DATA9__DATA9__SHIFT 0x0 1850 #define SDMA0_RLC2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 1851 //SDMA0_RLC2_MIDCMD_DATA10 1852 #define SDMA0_RLC2_MIDCMD_DATA10__DATA10__SHIFT 0x0 1853 #define SDMA0_RLC2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 1854 //SDMA0_RLC2_MIDCMD_CNTL 1855 #define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1856 #define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1857 #define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1858 #define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1859 #define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1860 #define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1861 #define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1862 #define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1863 //SDMA0_RLC3_RB_CNTL 1864 #define SDMA0_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 1865 #define SDMA0_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 1866 #define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1867 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1868 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1869 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1870 #define SDMA0_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 1871 #define SDMA0_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 1872 #define SDMA0_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1873 #define SDMA0_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1874 #define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1875 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1876 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1877 #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1878 #define SDMA0_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L 1879 #define SDMA0_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L 1880 //SDMA0_RLC3_RB_BASE 1881 #define SDMA0_RLC3_RB_BASE__ADDR__SHIFT 0x0 1882 #define SDMA0_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1883 //SDMA0_RLC3_RB_BASE_HI 1884 #define SDMA0_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 1885 #define SDMA0_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1886 //SDMA0_RLC3_RB_RPTR 1887 #define SDMA0_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 1888 #define SDMA0_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1889 //SDMA0_RLC3_RB_RPTR_HI 1890 #define SDMA0_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 1891 #define SDMA0_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1892 //SDMA0_RLC3_RB_WPTR 1893 #define SDMA0_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 1894 #define SDMA0_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1895 //SDMA0_RLC3_RB_WPTR_HI 1896 #define SDMA0_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 1897 #define SDMA0_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1898 //SDMA0_RLC3_RB_WPTR_POLL_CNTL 1899 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1900 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1901 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1902 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1903 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1904 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1905 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1906 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1907 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1908 #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1909 //SDMA0_RLC3_RB_RPTR_ADDR_HI 1910 #define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1911 #define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1912 //SDMA0_RLC3_RB_RPTR_ADDR_LO 1913 #define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1914 #define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1915 #define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1916 #define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1917 //SDMA0_RLC3_IB_CNTL 1918 #define SDMA0_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 1919 #define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1920 #define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1921 #define SDMA0_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 1922 #define SDMA0_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1923 #define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1924 #define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1925 #define SDMA0_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1926 //SDMA0_RLC3_IB_RPTR 1927 #define SDMA0_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 1928 #define SDMA0_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1929 //SDMA0_RLC3_IB_OFFSET 1930 #define SDMA0_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 1931 #define SDMA0_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1932 //SDMA0_RLC3_IB_BASE_LO 1933 #define SDMA0_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 1934 #define SDMA0_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1935 //SDMA0_RLC3_IB_BASE_HI 1936 #define SDMA0_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 1937 #define SDMA0_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1938 //SDMA0_RLC3_IB_SIZE 1939 #define SDMA0_RLC3_IB_SIZE__SIZE__SHIFT 0x0 1940 #define SDMA0_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL 1941 //SDMA0_RLC3_SKIP_CNTL 1942 #define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1943 #define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1944 //SDMA0_RLC3_CONTEXT_STATUS 1945 #define SDMA0_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1946 #define SDMA0_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 1947 #define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1948 #define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1949 #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1950 #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1951 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1952 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1953 #define SDMA0_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1954 #define SDMA0_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1955 #define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1956 #define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1957 #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1958 #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1959 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1960 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1961 //SDMA0_RLC3_DOORBELL 1962 #define SDMA0_RLC3_DOORBELL__ENABLE__SHIFT 0x1c 1963 #define SDMA0_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e 1964 #define SDMA0_RLC3_DOORBELL__ENABLE_MASK 0x10000000L 1965 #define SDMA0_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L 1966 //SDMA0_RLC3_STATUS 1967 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1968 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1969 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1970 #define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1971 //SDMA0_RLC3_DOORBELL_LOG 1972 #define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1973 #define SDMA0_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 1974 #define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1975 #define SDMA0_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1976 //SDMA0_RLC3_WATERMARK 1977 #define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1978 #define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1979 #define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1980 #define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1981 //SDMA0_RLC3_DOORBELL_OFFSET 1982 #define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1983 #define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1984 //SDMA0_RLC3_CSA_ADDR_LO 1985 #define SDMA0_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 1986 #define SDMA0_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1987 //SDMA0_RLC3_CSA_ADDR_HI 1988 #define SDMA0_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 1989 #define SDMA0_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1990 //SDMA0_RLC3_IB_SUB_REMAIN 1991 #define SDMA0_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1992 #define SDMA0_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1993 //SDMA0_RLC3_PREEMPT 1994 #define SDMA0_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 1995 #define SDMA0_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1996 //SDMA0_RLC3_DUMMY_REG 1997 #define SDMA0_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 1998 #define SDMA0_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1999 //SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI 2000 #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2001 #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2002 //SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO 2003 #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2004 #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2005 //SDMA0_RLC3_RB_AQL_CNTL 2006 #define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2007 #define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2008 #define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2009 #define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2010 #define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2011 #define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2012 //SDMA0_RLC3_MINOR_PTR_UPDATE 2013 #define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2014 #define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2015 //SDMA0_RLC3_MIDCMD_DATA0 2016 #define SDMA0_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 2017 #define SDMA0_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2018 //SDMA0_RLC3_MIDCMD_DATA1 2019 #define SDMA0_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 2020 #define SDMA0_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2021 //SDMA0_RLC3_MIDCMD_DATA2 2022 #define SDMA0_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 2023 #define SDMA0_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2024 //SDMA0_RLC3_MIDCMD_DATA3 2025 #define SDMA0_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 2026 #define SDMA0_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2027 //SDMA0_RLC3_MIDCMD_DATA4 2028 #define SDMA0_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 2029 #define SDMA0_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2030 //SDMA0_RLC3_MIDCMD_DATA5 2031 #define SDMA0_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 2032 #define SDMA0_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2033 //SDMA0_RLC3_MIDCMD_DATA6 2034 #define SDMA0_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 2035 #define SDMA0_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2036 //SDMA0_RLC3_MIDCMD_DATA7 2037 #define SDMA0_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 2038 #define SDMA0_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2039 //SDMA0_RLC3_MIDCMD_DATA8 2040 #define SDMA0_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 2041 #define SDMA0_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2042 //SDMA0_RLC3_MIDCMD_DATA9 2043 #define SDMA0_RLC3_MIDCMD_DATA9__DATA9__SHIFT 0x0 2044 #define SDMA0_RLC3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 2045 //SDMA0_RLC3_MIDCMD_DATA10 2046 #define SDMA0_RLC3_MIDCMD_DATA10__DATA10__SHIFT 0x0 2047 #define SDMA0_RLC3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 2048 //SDMA0_RLC3_MIDCMD_CNTL 2049 #define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2050 #define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2051 #define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2052 #define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2053 #define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2054 #define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2055 #define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2056 #define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2057 //SDMA0_RLC4_RB_CNTL 2058 #define SDMA0_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 2059 #define SDMA0_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 2060 #define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2061 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2062 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2063 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2064 #define SDMA0_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 2065 #define SDMA0_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 2066 #define SDMA0_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2067 #define SDMA0_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2068 #define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2069 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2070 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2071 #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2072 #define SDMA0_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L 2073 #define SDMA0_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L 2074 //SDMA0_RLC4_RB_BASE 2075 #define SDMA0_RLC4_RB_BASE__ADDR__SHIFT 0x0 2076 #define SDMA0_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2077 //SDMA0_RLC4_RB_BASE_HI 2078 #define SDMA0_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 2079 #define SDMA0_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2080 //SDMA0_RLC4_RB_RPTR 2081 #define SDMA0_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 2082 #define SDMA0_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2083 //SDMA0_RLC4_RB_RPTR_HI 2084 #define SDMA0_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 2085 #define SDMA0_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2086 //SDMA0_RLC4_RB_WPTR 2087 #define SDMA0_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 2088 #define SDMA0_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2089 //SDMA0_RLC4_RB_WPTR_HI 2090 #define SDMA0_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 2091 #define SDMA0_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2092 //SDMA0_RLC4_RB_WPTR_POLL_CNTL 2093 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2094 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2095 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2096 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2097 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2098 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2099 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2100 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2101 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2102 #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2103 //SDMA0_RLC4_RB_RPTR_ADDR_HI 2104 #define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2105 #define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2106 //SDMA0_RLC4_RB_RPTR_ADDR_LO 2107 #define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2108 #define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2109 #define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2110 #define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2111 //SDMA0_RLC4_IB_CNTL 2112 #define SDMA0_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 2113 #define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2114 #define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2115 #define SDMA0_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 2116 #define SDMA0_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2117 #define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2118 #define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2119 #define SDMA0_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2120 //SDMA0_RLC4_IB_RPTR 2121 #define SDMA0_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 2122 #define SDMA0_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2123 //SDMA0_RLC4_IB_OFFSET 2124 #define SDMA0_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 2125 #define SDMA0_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2126 //SDMA0_RLC4_IB_BASE_LO 2127 #define SDMA0_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 2128 #define SDMA0_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2129 //SDMA0_RLC4_IB_BASE_HI 2130 #define SDMA0_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 2131 #define SDMA0_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2132 //SDMA0_RLC4_IB_SIZE 2133 #define SDMA0_RLC4_IB_SIZE__SIZE__SHIFT 0x0 2134 #define SDMA0_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL 2135 //SDMA0_RLC4_SKIP_CNTL 2136 #define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2137 #define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2138 //SDMA0_RLC4_CONTEXT_STATUS 2139 #define SDMA0_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2140 #define SDMA0_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 2141 #define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2142 #define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2143 #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2144 #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2145 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2146 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2147 #define SDMA0_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2148 #define SDMA0_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2149 #define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2150 #define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2151 #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2152 #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2153 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2154 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2155 //SDMA0_RLC4_DOORBELL 2156 #define SDMA0_RLC4_DOORBELL__ENABLE__SHIFT 0x1c 2157 #define SDMA0_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e 2158 #define SDMA0_RLC4_DOORBELL__ENABLE_MASK 0x10000000L 2159 #define SDMA0_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L 2160 //SDMA0_RLC4_STATUS 2161 #define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2162 #define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2163 #define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2164 #define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2165 //SDMA0_RLC4_DOORBELL_LOG 2166 #define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2167 #define SDMA0_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 2168 #define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2169 #define SDMA0_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2170 //SDMA0_RLC4_WATERMARK 2171 #define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2172 #define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2173 #define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2174 #define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2175 //SDMA0_RLC4_DOORBELL_OFFSET 2176 #define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2177 #define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2178 //SDMA0_RLC4_CSA_ADDR_LO 2179 #define SDMA0_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 2180 #define SDMA0_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2181 //SDMA0_RLC4_CSA_ADDR_HI 2182 #define SDMA0_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 2183 #define SDMA0_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2184 //SDMA0_RLC4_IB_SUB_REMAIN 2185 #define SDMA0_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2186 #define SDMA0_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2187 //SDMA0_RLC4_PREEMPT 2188 #define SDMA0_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 2189 #define SDMA0_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2190 //SDMA0_RLC4_DUMMY_REG 2191 #define SDMA0_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 2192 #define SDMA0_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2193 //SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI 2194 #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2195 #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2196 //SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO 2197 #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2198 #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2199 //SDMA0_RLC4_RB_AQL_CNTL 2200 #define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2201 #define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2202 #define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2203 #define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2204 #define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2205 #define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2206 //SDMA0_RLC4_MINOR_PTR_UPDATE 2207 #define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2208 #define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2209 //SDMA0_RLC4_MIDCMD_DATA0 2210 #define SDMA0_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 2211 #define SDMA0_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2212 //SDMA0_RLC4_MIDCMD_DATA1 2213 #define SDMA0_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 2214 #define SDMA0_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2215 //SDMA0_RLC4_MIDCMD_DATA2 2216 #define SDMA0_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 2217 #define SDMA0_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2218 //SDMA0_RLC4_MIDCMD_DATA3 2219 #define SDMA0_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 2220 #define SDMA0_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2221 //SDMA0_RLC4_MIDCMD_DATA4 2222 #define SDMA0_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 2223 #define SDMA0_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2224 //SDMA0_RLC4_MIDCMD_DATA5 2225 #define SDMA0_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 2226 #define SDMA0_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2227 //SDMA0_RLC4_MIDCMD_DATA6 2228 #define SDMA0_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 2229 #define SDMA0_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2230 //SDMA0_RLC4_MIDCMD_DATA7 2231 #define SDMA0_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 2232 #define SDMA0_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2233 //SDMA0_RLC4_MIDCMD_DATA8 2234 #define SDMA0_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 2235 #define SDMA0_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2236 //SDMA0_RLC4_MIDCMD_DATA9 2237 #define SDMA0_RLC4_MIDCMD_DATA9__DATA9__SHIFT 0x0 2238 #define SDMA0_RLC4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 2239 //SDMA0_RLC4_MIDCMD_DATA10 2240 #define SDMA0_RLC4_MIDCMD_DATA10__DATA10__SHIFT 0x0 2241 #define SDMA0_RLC4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 2242 //SDMA0_RLC4_MIDCMD_CNTL 2243 #define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2244 #define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2245 #define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2246 #define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2247 #define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2248 #define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2249 #define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2250 #define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2251 //SDMA0_RLC5_RB_CNTL 2252 #define SDMA0_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 2253 #define SDMA0_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 2254 #define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2255 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2256 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2257 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2258 #define SDMA0_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 2259 #define SDMA0_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 2260 #define SDMA0_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2261 #define SDMA0_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2262 #define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2263 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2264 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2265 #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2266 #define SDMA0_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L 2267 #define SDMA0_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L 2268 //SDMA0_RLC5_RB_BASE 2269 #define SDMA0_RLC5_RB_BASE__ADDR__SHIFT 0x0 2270 #define SDMA0_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2271 //SDMA0_RLC5_RB_BASE_HI 2272 #define SDMA0_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 2273 #define SDMA0_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2274 //SDMA0_RLC5_RB_RPTR 2275 #define SDMA0_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 2276 #define SDMA0_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2277 //SDMA0_RLC5_RB_RPTR_HI 2278 #define SDMA0_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 2279 #define SDMA0_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2280 //SDMA0_RLC5_RB_WPTR 2281 #define SDMA0_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 2282 #define SDMA0_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2283 //SDMA0_RLC5_RB_WPTR_HI 2284 #define SDMA0_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 2285 #define SDMA0_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2286 //SDMA0_RLC5_RB_WPTR_POLL_CNTL 2287 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2288 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2289 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2290 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2291 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2292 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2293 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2294 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2295 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2296 #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2297 //SDMA0_RLC5_RB_RPTR_ADDR_HI 2298 #define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2299 #define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2300 //SDMA0_RLC5_RB_RPTR_ADDR_LO 2301 #define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2302 #define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2303 #define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2304 #define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2305 //SDMA0_RLC5_IB_CNTL 2306 #define SDMA0_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 2307 #define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2308 #define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2309 #define SDMA0_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 2310 #define SDMA0_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2311 #define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2312 #define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2313 #define SDMA0_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2314 //SDMA0_RLC5_IB_RPTR 2315 #define SDMA0_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 2316 #define SDMA0_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2317 //SDMA0_RLC5_IB_OFFSET 2318 #define SDMA0_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 2319 #define SDMA0_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2320 //SDMA0_RLC5_IB_BASE_LO 2321 #define SDMA0_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 2322 #define SDMA0_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2323 //SDMA0_RLC5_IB_BASE_HI 2324 #define SDMA0_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 2325 #define SDMA0_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2326 //SDMA0_RLC5_IB_SIZE 2327 #define SDMA0_RLC5_IB_SIZE__SIZE__SHIFT 0x0 2328 #define SDMA0_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL 2329 //SDMA0_RLC5_SKIP_CNTL 2330 #define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2331 #define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2332 //SDMA0_RLC5_CONTEXT_STATUS 2333 #define SDMA0_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2334 #define SDMA0_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 2335 #define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2336 #define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2337 #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2338 #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2339 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2340 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2341 #define SDMA0_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2342 #define SDMA0_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2343 #define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2344 #define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2345 #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2346 #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2347 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2348 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2349 //SDMA0_RLC5_DOORBELL 2350 #define SDMA0_RLC5_DOORBELL__ENABLE__SHIFT 0x1c 2351 #define SDMA0_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e 2352 #define SDMA0_RLC5_DOORBELL__ENABLE_MASK 0x10000000L 2353 #define SDMA0_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L 2354 //SDMA0_RLC5_STATUS 2355 #define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2356 #define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2357 #define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2358 #define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2359 //SDMA0_RLC5_DOORBELL_LOG 2360 #define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2361 #define SDMA0_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 2362 #define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2363 #define SDMA0_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2364 //SDMA0_RLC5_WATERMARK 2365 #define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2366 #define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2367 #define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2368 #define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2369 //SDMA0_RLC5_DOORBELL_OFFSET 2370 #define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2371 #define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2372 //SDMA0_RLC5_CSA_ADDR_LO 2373 #define SDMA0_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 2374 #define SDMA0_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2375 //SDMA0_RLC5_CSA_ADDR_HI 2376 #define SDMA0_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 2377 #define SDMA0_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2378 //SDMA0_RLC5_IB_SUB_REMAIN 2379 #define SDMA0_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2380 #define SDMA0_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2381 //SDMA0_RLC5_PREEMPT 2382 #define SDMA0_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 2383 #define SDMA0_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2384 //SDMA0_RLC5_DUMMY_REG 2385 #define SDMA0_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 2386 #define SDMA0_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2387 //SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI 2388 #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2389 #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2390 //SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO 2391 #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2392 #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2393 //SDMA0_RLC5_RB_AQL_CNTL 2394 #define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2395 #define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2396 #define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2397 #define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2398 #define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2399 #define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2400 //SDMA0_RLC5_MINOR_PTR_UPDATE 2401 #define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2402 #define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2403 //SDMA0_RLC5_MIDCMD_DATA0 2404 #define SDMA0_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 2405 #define SDMA0_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2406 //SDMA0_RLC5_MIDCMD_DATA1 2407 #define SDMA0_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 2408 #define SDMA0_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2409 //SDMA0_RLC5_MIDCMD_DATA2 2410 #define SDMA0_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 2411 #define SDMA0_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2412 //SDMA0_RLC5_MIDCMD_DATA3 2413 #define SDMA0_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 2414 #define SDMA0_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2415 //SDMA0_RLC5_MIDCMD_DATA4 2416 #define SDMA0_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 2417 #define SDMA0_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2418 //SDMA0_RLC5_MIDCMD_DATA5 2419 #define SDMA0_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 2420 #define SDMA0_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2421 //SDMA0_RLC5_MIDCMD_DATA6 2422 #define SDMA0_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 2423 #define SDMA0_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2424 //SDMA0_RLC5_MIDCMD_DATA7 2425 #define SDMA0_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 2426 #define SDMA0_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2427 //SDMA0_RLC5_MIDCMD_DATA8 2428 #define SDMA0_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 2429 #define SDMA0_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2430 //SDMA0_RLC5_MIDCMD_DATA9 2431 #define SDMA0_RLC5_MIDCMD_DATA9__DATA9__SHIFT 0x0 2432 #define SDMA0_RLC5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 2433 //SDMA0_RLC5_MIDCMD_DATA10 2434 #define SDMA0_RLC5_MIDCMD_DATA10__DATA10__SHIFT 0x0 2435 #define SDMA0_RLC5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 2436 //SDMA0_RLC5_MIDCMD_CNTL 2437 #define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2438 #define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2439 #define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2440 #define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2441 #define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2442 #define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2443 #define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2444 #define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2445 //SDMA0_RLC6_RB_CNTL 2446 #define SDMA0_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 2447 #define SDMA0_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 2448 #define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2449 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2450 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2451 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2452 #define SDMA0_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 2453 #define SDMA0_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 2454 #define SDMA0_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2455 #define SDMA0_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2456 #define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2457 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2458 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2459 #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2460 #define SDMA0_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L 2461 #define SDMA0_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L 2462 //SDMA0_RLC6_RB_BASE 2463 #define SDMA0_RLC6_RB_BASE__ADDR__SHIFT 0x0 2464 #define SDMA0_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2465 //SDMA0_RLC6_RB_BASE_HI 2466 #define SDMA0_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 2467 #define SDMA0_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2468 //SDMA0_RLC6_RB_RPTR 2469 #define SDMA0_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 2470 #define SDMA0_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2471 //SDMA0_RLC6_RB_RPTR_HI 2472 #define SDMA0_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 2473 #define SDMA0_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2474 //SDMA0_RLC6_RB_WPTR 2475 #define SDMA0_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 2476 #define SDMA0_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2477 //SDMA0_RLC6_RB_WPTR_HI 2478 #define SDMA0_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 2479 #define SDMA0_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2480 //SDMA0_RLC6_RB_WPTR_POLL_CNTL 2481 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2482 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2483 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2484 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2485 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2486 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2487 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2488 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2489 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2490 #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2491 //SDMA0_RLC6_RB_RPTR_ADDR_HI 2492 #define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2493 #define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2494 //SDMA0_RLC6_RB_RPTR_ADDR_LO 2495 #define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2496 #define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2497 #define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2498 #define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2499 //SDMA0_RLC6_IB_CNTL 2500 #define SDMA0_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 2501 #define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2502 #define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2503 #define SDMA0_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 2504 #define SDMA0_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2505 #define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2506 #define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2507 #define SDMA0_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2508 //SDMA0_RLC6_IB_RPTR 2509 #define SDMA0_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 2510 #define SDMA0_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2511 //SDMA0_RLC6_IB_OFFSET 2512 #define SDMA0_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 2513 #define SDMA0_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2514 //SDMA0_RLC6_IB_BASE_LO 2515 #define SDMA0_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 2516 #define SDMA0_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2517 //SDMA0_RLC6_IB_BASE_HI 2518 #define SDMA0_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 2519 #define SDMA0_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2520 //SDMA0_RLC6_IB_SIZE 2521 #define SDMA0_RLC6_IB_SIZE__SIZE__SHIFT 0x0 2522 #define SDMA0_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL 2523 //SDMA0_RLC6_SKIP_CNTL 2524 #define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2525 #define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2526 //SDMA0_RLC6_CONTEXT_STATUS 2527 #define SDMA0_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2528 #define SDMA0_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 2529 #define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2530 #define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2531 #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2532 #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2533 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2534 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2535 #define SDMA0_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2536 #define SDMA0_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2537 #define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2538 #define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2539 #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2540 #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2541 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2542 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2543 //SDMA0_RLC6_DOORBELL 2544 #define SDMA0_RLC6_DOORBELL__ENABLE__SHIFT 0x1c 2545 #define SDMA0_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e 2546 #define SDMA0_RLC6_DOORBELL__ENABLE_MASK 0x10000000L 2547 #define SDMA0_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L 2548 //SDMA0_RLC6_STATUS 2549 #define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2550 #define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2551 #define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2552 #define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2553 //SDMA0_RLC6_DOORBELL_LOG 2554 #define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2555 #define SDMA0_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 2556 #define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2557 #define SDMA0_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2558 //SDMA0_RLC6_WATERMARK 2559 #define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2560 #define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2561 #define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2562 #define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2563 //SDMA0_RLC6_DOORBELL_OFFSET 2564 #define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2565 #define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2566 //SDMA0_RLC6_CSA_ADDR_LO 2567 #define SDMA0_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 2568 #define SDMA0_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2569 //SDMA0_RLC6_CSA_ADDR_HI 2570 #define SDMA0_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 2571 #define SDMA0_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2572 //SDMA0_RLC6_IB_SUB_REMAIN 2573 #define SDMA0_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2574 #define SDMA0_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2575 //SDMA0_RLC6_PREEMPT 2576 #define SDMA0_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 2577 #define SDMA0_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2578 //SDMA0_RLC6_DUMMY_REG 2579 #define SDMA0_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 2580 #define SDMA0_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2581 //SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI 2582 #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2583 #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2584 //SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO 2585 #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2586 #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2587 //SDMA0_RLC6_RB_AQL_CNTL 2588 #define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2589 #define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2590 #define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2591 #define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2592 #define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2593 #define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2594 //SDMA0_RLC6_MINOR_PTR_UPDATE 2595 #define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2596 #define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2597 //SDMA0_RLC6_MIDCMD_DATA0 2598 #define SDMA0_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 2599 #define SDMA0_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2600 //SDMA0_RLC6_MIDCMD_DATA1 2601 #define SDMA0_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 2602 #define SDMA0_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2603 //SDMA0_RLC6_MIDCMD_DATA2 2604 #define SDMA0_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 2605 #define SDMA0_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2606 //SDMA0_RLC6_MIDCMD_DATA3 2607 #define SDMA0_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 2608 #define SDMA0_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2609 //SDMA0_RLC6_MIDCMD_DATA4 2610 #define SDMA0_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 2611 #define SDMA0_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2612 //SDMA0_RLC6_MIDCMD_DATA5 2613 #define SDMA0_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 2614 #define SDMA0_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2615 //SDMA0_RLC6_MIDCMD_DATA6 2616 #define SDMA0_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 2617 #define SDMA0_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2618 //SDMA0_RLC6_MIDCMD_DATA7 2619 #define SDMA0_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 2620 #define SDMA0_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2621 //SDMA0_RLC6_MIDCMD_DATA8 2622 #define SDMA0_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 2623 #define SDMA0_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2624 //SDMA0_RLC6_MIDCMD_DATA9 2625 #define SDMA0_RLC6_MIDCMD_DATA9__DATA9__SHIFT 0x0 2626 #define SDMA0_RLC6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 2627 //SDMA0_RLC6_MIDCMD_DATA10 2628 #define SDMA0_RLC6_MIDCMD_DATA10__DATA10__SHIFT 0x0 2629 #define SDMA0_RLC6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 2630 //SDMA0_RLC6_MIDCMD_CNTL 2631 #define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2632 #define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2633 #define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2634 #define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2635 #define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2636 #define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2637 #define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2638 #define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2639 //SDMA0_RLC7_RB_CNTL 2640 #define SDMA0_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 2641 #define SDMA0_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 2642 #define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2643 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2644 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2645 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2646 #define SDMA0_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 2647 #define SDMA0_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 2648 #define SDMA0_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2649 #define SDMA0_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2650 #define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2651 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2652 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2653 #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2654 #define SDMA0_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L 2655 #define SDMA0_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L 2656 //SDMA0_RLC7_RB_BASE 2657 #define SDMA0_RLC7_RB_BASE__ADDR__SHIFT 0x0 2658 #define SDMA0_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2659 //SDMA0_RLC7_RB_BASE_HI 2660 #define SDMA0_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 2661 #define SDMA0_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2662 //SDMA0_RLC7_RB_RPTR 2663 #define SDMA0_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 2664 #define SDMA0_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2665 //SDMA0_RLC7_RB_RPTR_HI 2666 #define SDMA0_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 2667 #define SDMA0_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2668 //SDMA0_RLC7_RB_WPTR 2669 #define SDMA0_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 2670 #define SDMA0_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2671 //SDMA0_RLC7_RB_WPTR_HI 2672 #define SDMA0_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 2673 #define SDMA0_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2674 //SDMA0_RLC7_RB_WPTR_POLL_CNTL 2675 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2676 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2677 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2678 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2679 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2680 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2681 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2682 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2683 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2684 #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2685 //SDMA0_RLC7_RB_RPTR_ADDR_HI 2686 #define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2687 #define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2688 //SDMA0_RLC7_RB_RPTR_ADDR_LO 2689 #define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2690 #define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2691 #define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2692 #define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2693 //SDMA0_RLC7_IB_CNTL 2694 #define SDMA0_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 2695 #define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2696 #define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2697 #define SDMA0_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 2698 #define SDMA0_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2699 #define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2700 #define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2701 #define SDMA0_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2702 //SDMA0_RLC7_IB_RPTR 2703 #define SDMA0_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 2704 #define SDMA0_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2705 //SDMA0_RLC7_IB_OFFSET 2706 #define SDMA0_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 2707 #define SDMA0_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2708 //SDMA0_RLC7_IB_BASE_LO 2709 #define SDMA0_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 2710 #define SDMA0_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2711 //SDMA0_RLC7_IB_BASE_HI 2712 #define SDMA0_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 2713 #define SDMA0_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2714 //SDMA0_RLC7_IB_SIZE 2715 #define SDMA0_RLC7_IB_SIZE__SIZE__SHIFT 0x0 2716 #define SDMA0_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL 2717 //SDMA0_RLC7_SKIP_CNTL 2718 #define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2719 #define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2720 //SDMA0_RLC7_CONTEXT_STATUS 2721 #define SDMA0_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2722 #define SDMA0_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 2723 #define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2724 #define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2725 #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2726 #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2727 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2728 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2729 #define SDMA0_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2730 #define SDMA0_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2731 #define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2732 #define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2733 #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2734 #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2735 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2736 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2737 //SDMA0_RLC7_DOORBELL 2738 #define SDMA0_RLC7_DOORBELL__ENABLE__SHIFT 0x1c 2739 #define SDMA0_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e 2740 #define SDMA0_RLC7_DOORBELL__ENABLE_MASK 0x10000000L 2741 #define SDMA0_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L 2742 //SDMA0_RLC7_STATUS 2743 #define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2744 #define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2745 #define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2746 #define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2747 //SDMA0_RLC7_DOORBELL_LOG 2748 #define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2749 #define SDMA0_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 2750 #define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2751 #define SDMA0_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2752 //SDMA0_RLC7_WATERMARK 2753 #define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2754 #define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2755 #define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2756 #define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2757 //SDMA0_RLC7_DOORBELL_OFFSET 2758 #define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2759 #define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2760 //SDMA0_RLC7_CSA_ADDR_LO 2761 #define SDMA0_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 2762 #define SDMA0_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2763 //SDMA0_RLC7_CSA_ADDR_HI 2764 #define SDMA0_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 2765 #define SDMA0_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2766 //SDMA0_RLC7_IB_SUB_REMAIN 2767 #define SDMA0_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2768 #define SDMA0_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2769 //SDMA0_RLC7_PREEMPT 2770 #define SDMA0_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 2771 #define SDMA0_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2772 //SDMA0_RLC7_DUMMY_REG 2773 #define SDMA0_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 2774 #define SDMA0_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2775 //SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI 2776 #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2777 #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2778 //SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO 2779 #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2780 #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2781 //SDMA0_RLC7_RB_AQL_CNTL 2782 #define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2783 #define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2784 #define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2785 #define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2786 #define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2787 #define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2788 //SDMA0_RLC7_MINOR_PTR_UPDATE 2789 #define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2790 #define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2791 //SDMA0_RLC7_MIDCMD_DATA0 2792 #define SDMA0_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 2793 #define SDMA0_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2794 //SDMA0_RLC7_MIDCMD_DATA1 2795 #define SDMA0_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 2796 #define SDMA0_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2797 //SDMA0_RLC7_MIDCMD_DATA2 2798 #define SDMA0_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 2799 #define SDMA0_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2800 //SDMA0_RLC7_MIDCMD_DATA3 2801 #define SDMA0_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 2802 #define SDMA0_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2803 //SDMA0_RLC7_MIDCMD_DATA4 2804 #define SDMA0_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 2805 #define SDMA0_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2806 //SDMA0_RLC7_MIDCMD_DATA5 2807 #define SDMA0_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 2808 #define SDMA0_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2809 //SDMA0_RLC7_MIDCMD_DATA6 2810 #define SDMA0_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 2811 #define SDMA0_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2812 //SDMA0_RLC7_MIDCMD_DATA7 2813 #define SDMA0_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 2814 #define SDMA0_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2815 //SDMA0_RLC7_MIDCMD_DATA8 2816 #define SDMA0_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 2817 #define SDMA0_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2818 //SDMA0_RLC7_MIDCMD_DATA9 2819 #define SDMA0_RLC7_MIDCMD_DATA9__DATA9__SHIFT 0x0 2820 #define SDMA0_RLC7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 2821 //SDMA0_RLC7_MIDCMD_DATA10 2822 #define SDMA0_RLC7_MIDCMD_DATA10__DATA10__SHIFT 0x0 2823 #define SDMA0_RLC7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 2824 //SDMA0_RLC7_MIDCMD_CNTL 2825 #define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2826 #define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2827 #define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2828 #define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2829 #define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2830 #define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2831 #define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2832 #define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2833 2834 2835 // addressBlock: sdma0_sdma1dec 2836 //SDMA1_UCODE_ADDR 2837 #define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 2838 #define SDMA1_UCODE_ADDR__VALUE_MASK 0x00003FFFL 2839 //SDMA1_UCODE_DATA 2840 #define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 2841 #define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 2842 //SDMA1_VF_ENABLE 2843 #define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0 2844 #define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 2845 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0 2846 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1 2847 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x00000001L 2848 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x00000002L 2849 //SDMA1_CONTEXT_GROUP_BOUNDARY 2850 #define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 2851 #define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 2852 //SDMA1_POWER_CNTL 2853 #define SDMA1_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 2854 #define SDMA1_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 2855 #define SDMA1_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 2856 #define SDMA1_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 2857 #define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 2858 #define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 2859 #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 2860 #define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 2861 #define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 2862 #define SDMA1_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a 2863 #define SDMA1_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L 2864 #define SDMA1_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L 2865 #define SDMA1_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L 2866 #define SDMA1_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 2867 #define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 2868 #define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 2869 #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 2870 #define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 2871 #define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 2872 #define SDMA1_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 2873 //SDMA1_CLK_CTRL 2874 #define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 2875 #define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2876 #define SDMA1_CLK_CTRL__RESERVED__SHIFT 0xc 2877 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 2878 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 2879 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 2880 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 2881 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 2882 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 2883 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 2884 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 2885 #define SDMA1_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 2886 #define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 2887 #define SDMA1_CLK_CTRL__RESERVED_MASK 0x00FFF000L 2888 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 2889 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 2890 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 2891 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 2892 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 2893 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 2894 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 2895 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 2896 //SDMA1_CNTL 2897 #define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 2898 #define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT 0x1 2899 #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 2900 #define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 2901 #define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 2902 #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 2903 #define SDMA1_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x6 2904 #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 2905 #define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 2906 #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 2907 #define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 2908 #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 2909 #define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L 2910 #define SDMA1_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 2911 #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 2912 #define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 2913 #define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 2914 #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 2915 #define SDMA1_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000040L 2916 #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 2917 #define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 2918 #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 2919 #define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 2920 #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 2921 //SDMA1_CHICKEN_BITS 2922 #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 2923 #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 2924 #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 2925 #define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 2926 #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 2927 #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 2928 #define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 2929 #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 2930 #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 2931 #define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 2932 #define SDMA1_CHICKEN_BITS__SRAM_FGCG_ENABLE__SHIFT 0x1a 2933 #define SDMA1_CHICKEN_BITS__RESERVED__SHIFT 0x1b 2934 #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 2935 #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 2936 #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 2937 #define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 2938 #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 2939 #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 2940 #define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 2941 #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 2942 #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 2943 #define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 2944 #define SDMA1_CHICKEN_BITS__SRAM_FGCG_ENABLE_MASK 0x04000000L 2945 #define SDMA1_CHICKEN_BITS__RESERVED_MASK 0xF8000000L 2946 //SDMA1_GB_ADDR_CONFIG 2947 #define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 2948 #define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 2949 #define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 2950 #define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 2951 #define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 2952 #define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 2953 #define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 2954 #define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 2955 #define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 2956 #define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 2957 //SDMA1_GB_ADDR_CONFIG_READ 2958 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 2959 #define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 2960 #define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 2961 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 2962 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 2963 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 2964 #define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 2965 #define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 2966 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 2967 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 2968 //SDMA1_RB_RPTR_FETCH_HI 2969 #define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 2970 #define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 2971 //SDMA1_SEM_WAIT_FAIL_TIMER_CNTL 2972 #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 2973 #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 2974 //SDMA1_RB_RPTR_FETCH 2975 #define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 2976 #define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 2977 //SDMA1_IB_OFFSET_FETCH 2978 #define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 2979 #define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 2980 //SDMA1_PROGRAM 2981 #define SDMA1_PROGRAM__STREAM__SHIFT 0x0 2982 #define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL 2983 //SDMA1_STATUS_REG 2984 #define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 2985 #define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 2986 #define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 2987 #define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 2988 #define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 2989 #define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 2990 #define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 2991 #define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 2992 #define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 2993 #define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 2994 #define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa 2995 #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 2996 #define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc 2997 #define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 2998 #define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe 2999 #define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 3000 #define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 3001 #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 3002 #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 3003 #define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 3004 #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 3005 #define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 3006 #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 3007 #define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 3008 #define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a 3009 #define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 3010 #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 3011 #define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e 3012 #define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 3013 #define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L 3014 #define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L 3015 #define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L 3016 #define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L 3017 #define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 3018 #define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 3019 #define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 3020 #define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 3021 #define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 3022 #define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L 3023 #define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L 3024 #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 3025 #define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L 3026 #define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 3027 #define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 3028 #define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 3029 #define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 3030 #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 3031 #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 3032 #define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 3033 #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 3034 #define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 3035 #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 3036 #define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 3037 #define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L 3038 #define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 3039 #define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 3040 #define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L 3041 #define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 3042 //SDMA1_STATUS1_REG 3043 #define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 3044 #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 3045 #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 3046 #define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 3047 #define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 3048 #define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 3049 #define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 3050 #define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 3051 #define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 3052 #define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 3053 #define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 3054 #define SDMA1_STATUS1_REG__EX_START__SHIFT 0xf 3055 #define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 3056 #define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 3057 #define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 3058 #define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 3059 #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 3060 #define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 3061 #define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 3062 #define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 3063 #define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 3064 #define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 3065 #define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 3066 #define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 3067 #define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 3068 #define SDMA1_STATUS1_REG__EX_START_MASK 0x00008000L 3069 #define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 3070 #define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 3071 //SDMA1_RD_BURST_CNTL 3072 #define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 3073 #define SDMA1_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 3074 #define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 3075 #define SDMA1_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL 3076 //SDMA1_HBM_PAGE_CONFIG 3077 #define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 3078 #define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L 3079 //SDMA1_UCODE_CHECKSUM 3080 #define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0 3081 #define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 3082 //SDMA1_F32_CNTL 3083 #define SDMA1_F32_CNTL__HALT__SHIFT 0x0 3084 #define SDMA1_F32_CNTL__STEP__SHIFT 0x1 3085 #define SDMA1_F32_CNTL__RESET__SHIFT 0x8 3086 #define SDMA1_F32_CNTL__HALT_MASK 0x00000001L 3087 #define SDMA1_F32_CNTL__STEP_MASK 0x00000002L 3088 #define SDMA1_F32_CNTL__RESET_MASK 0x00000100L 3089 //SDMA1_FREEZE 3090 #define SDMA1_FREEZE__PREEMPT__SHIFT 0x0 3091 #define SDMA1_FREEZE__FREEZE__SHIFT 0x4 3092 #define SDMA1_FREEZE__FROZEN__SHIFT 0x5 3093 #define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 3094 #define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L 3095 #define SDMA1_FREEZE__FREEZE_MASK 0x00000010L 3096 #define SDMA1_FREEZE__FROZEN_MASK 0x00000020L 3097 #define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L 3098 //SDMA1_PHASE0_QUANTUM 3099 #define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 3100 #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 3101 #define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 3102 #define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 3103 #define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 3104 #define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 3105 //SDMA1_PHASE1_QUANTUM 3106 #define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 3107 #define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 3108 #define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 3109 #define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 3110 #define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 3111 #define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 3112 //CC_SDMA1_EDC_CONFIG 3113 #define CC_SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 3114 #define CC_SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 3115 //SDMA1_BA_THRESHOLD 3116 #define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 3117 #define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 3118 #define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 3119 #define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 3120 //SDMA1_ID 3121 #define SDMA1_ID__DEVICE_ID__SHIFT 0x0 3122 #define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL 3123 //SDMA1_VERSION 3124 #define SDMA1_VERSION__MINVER__SHIFT 0x0 3125 #define SDMA1_VERSION__MAJVER__SHIFT 0x8 3126 #define SDMA1_VERSION__REV__SHIFT 0x10 3127 #define SDMA1_VERSION__MINVER_MASK 0x0000007FL 3128 #define SDMA1_VERSION__MAJVER_MASK 0x00007F00L 3129 #define SDMA1_VERSION__REV_MASK 0x003F0000L 3130 //SDMA1_EDC_COUNTER 3131 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x0 3132 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x2 3133 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x4 3134 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0x6 3135 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0x8 3136 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa 3137 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xc 3138 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 3139 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0x10 3140 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x12 3141 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x14 3142 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x16 3143 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x18 3144 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x1a 3145 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x1c 3146 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x1e 3147 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000003L 3148 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x0000000CL 3149 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000030L 3150 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x000000C0L 3151 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000300L 3152 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00000C00L 3153 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00003000L 3154 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x0000C000L 3155 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00030000L 3156 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x000C0000L 3157 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00300000L 3158 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00C00000L 3159 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x03000000L 3160 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x0C000000L 3161 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x30000000L 3162 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0xC0000000L 3163 //SDMA1_EDC_COUNTER2 3164 #define SDMA1_EDC_COUNTER2__SDMA_UCODE_BUF_SED__SHIFT 0x0 3165 #define SDMA1_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 3166 #define SDMA1_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED__SHIFT 0x4 3167 #define SDMA1_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x6 3168 #define SDMA1_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x8 3169 #define SDMA1_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED__SHIFT 0xa 3170 #define SDMA1_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED__SHIFT 0xc 3171 #define SDMA1_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED__SHIFT 0xe 3172 #define SDMA1_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 3173 #define SDMA1_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED__SHIFT 0x12 3174 #define SDMA1_EDC_COUNTER2__SDMA_UCODE_BUF_SED_MASK 0x00000003L 3175 #define SDMA1_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED_MASK 0x0000000CL 3176 #define SDMA1_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED_MASK 0x00000030L 3177 #define SDMA1_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED_MASK 0x000000C0L 3178 #define SDMA1_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000300L 3179 #define SDMA1_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED_MASK 0x00000C00L 3180 #define SDMA1_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED_MASK 0x00003000L 3181 #define SDMA1_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED_MASK 0x0000C000L 3182 #define SDMA1_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00030000L 3183 #define SDMA1_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED_MASK 0x000C0000L 3184 //SDMA1_STATUS2_REG 3185 #define SDMA1_STATUS2_REG__ID__SHIFT 0x0 3186 #define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 3187 #define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 3188 #define SDMA1_STATUS2_REG__ID_MASK 0x00000007L 3189 #define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L 3190 #define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 3191 //SDMA1_ATOMIC_CNTL 3192 #define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 3193 #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 3194 #define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 3195 #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 3196 //SDMA1_ATOMIC_PREOP_LO 3197 #define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 3198 #define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 3199 //SDMA1_ATOMIC_PREOP_HI 3200 #define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 3201 #define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 3202 //SDMA1_UTCL1_CNTL 3203 #define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 3204 #define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 3205 #define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 3206 #define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 3207 #define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 3208 #define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 3209 #define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 3210 #define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 3211 #define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 3212 #define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 3213 #define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 3214 #define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 3215 //SDMA1_UTCL1_WATERMK 3216 #define SDMA1_UTCL1_WATERMK__REQ_WATERMK__SHIFT 0x0 3217 #define SDMA1_UTCL1_WATERMK__REQ_DEPTH__SHIFT 0x3 3218 #define SDMA1_UTCL1_WATERMK__PAGE_WATERMK__SHIFT 0x5 3219 #define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x8 3220 #define SDMA1_UTCL1_WATERMK__RESERVED__SHIFT 0x10 3221 #define SDMA1_UTCL1_WATERMK__REQ_WATERMK_MASK 0x00000007L 3222 #define SDMA1_UTCL1_WATERMK__REQ_DEPTH_MASK 0x00000018L 3223 #define SDMA1_UTCL1_WATERMK__PAGE_WATERMK_MASK 0x000000E0L 3224 #define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x0000FF00L 3225 #define SDMA1_UTCL1_WATERMK__RESERVED_MASK 0xFFFF0000L 3226 //SDMA1_UTCL1_RD_STATUS 3227 #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 3228 #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 3229 #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 3230 #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 3231 #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 3232 #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 3233 #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 3234 #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 3235 #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 3236 #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 3237 #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 3238 #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 3239 #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 3240 #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 3241 #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 3242 #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 3243 #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 3244 #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 3245 #define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 3246 #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 3247 #define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 3248 #define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 3249 #define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 3250 #define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 3251 #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 3252 #define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 3253 #define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 3254 #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 3255 #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 3256 #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 3257 #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 3258 #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 3259 #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 3260 #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 3261 #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 3262 #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 3263 #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 3264 #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 3265 #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 3266 #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 3267 #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 3268 #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 3269 #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 3270 #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 3271 #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 3272 #define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 3273 #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 3274 #define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 3275 #define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 3276 #define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 3277 #define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 3278 #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 3279 #define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 3280 #define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 3281 //SDMA1_UTCL1_WR_STATUS 3282 #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 3283 #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 3284 #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 3285 #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 3286 #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 3287 #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 3288 #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 3289 #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 3290 #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 3291 #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 3292 #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 3293 #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 3294 #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 3295 #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 3296 #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 3297 #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 3298 #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 3299 #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 3300 #define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 3301 #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 3302 #define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 3303 #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 3304 #define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 3305 #define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 3306 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 3307 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 3308 #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 3309 #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 3310 #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 3311 #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 3312 #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 3313 #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 3314 #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 3315 #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 3316 #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 3317 #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 3318 #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 3319 #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 3320 #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 3321 #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 3322 #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 3323 #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 3324 #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 3325 #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 3326 #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 3327 #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 3328 #define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 3329 #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 3330 #define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 3331 #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 3332 #define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 3333 #define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 3334 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 3335 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 3336 #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 3337 #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 3338 //SDMA1_UTCL1_INV0 3339 #define SDMA1_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 3340 #define SDMA1_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 3341 #define SDMA1_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 3342 #define SDMA1_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 3343 #define SDMA1_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 3344 #define SDMA1_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 3345 #define SDMA1_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 3346 #define SDMA1_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 3347 #define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 3348 #define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 3349 #define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 3350 #define SDMA1_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 3351 #define SDMA1_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 3352 #define SDMA1_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 3353 #define SDMA1_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 3354 #define SDMA1_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 3355 #define SDMA1_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 3356 #define SDMA1_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 3357 #define SDMA1_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 3358 #define SDMA1_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 3359 #define SDMA1_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 3360 #define SDMA1_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 3361 #define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 3362 #define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 3363 #define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 3364 #define SDMA1_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 3365 #define SDMA1_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 3366 #define SDMA1_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 3367 //SDMA1_UTCL1_INV1 3368 #define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 3369 #define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 3370 //SDMA1_UTCL1_INV2 3371 #define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 3372 #define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 3373 //SDMA1_UTCL1_RD_XNACK0 3374 #define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 3375 #define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 3376 //SDMA1_UTCL1_RD_XNACK1 3377 #define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 3378 #define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 3379 #define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 3380 #define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 3381 #define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 3382 #define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 3383 #define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 3384 #define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 3385 //SDMA1_UTCL1_WR_XNACK0 3386 #define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 3387 #define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 3388 //SDMA1_UTCL1_WR_XNACK1 3389 #define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 3390 #define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 3391 #define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 3392 #define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 3393 #define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 3394 #define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 3395 #define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 3396 #define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 3397 //SDMA1_UTCL1_TIMEOUT 3398 #define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 3399 #define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 3400 #define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 3401 #define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 3402 //SDMA1_UTCL1_PAGE 3403 #define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 3404 #define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 3405 #define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 3406 #define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 3407 #define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 3408 #define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 3409 #define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 3410 #define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 3411 //SDMA1_POWER_CNTL_IDLE 3412 #define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 3413 #define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 3414 #define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 3415 #define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 3416 #define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 3417 #define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 3418 //SDMA1_RELAX_ORDERING_LUT 3419 #define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 3420 #define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 3421 #define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 3422 #define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 3423 #define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 3424 #define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 3425 #define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 3426 #define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 3427 #define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 3428 #define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 3429 #define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 3430 #define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 3431 #define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 3432 #define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 3433 #define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 3434 #define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 3435 #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 3436 #define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 3437 #define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 3438 #define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 3439 #define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 3440 #define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 3441 #define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 3442 #define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 3443 #define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 3444 #define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 3445 #define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 3446 #define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 3447 #define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 3448 #define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 3449 #define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 3450 #define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 3451 #define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 3452 #define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 3453 #define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 3454 #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 3455 #define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 3456 #define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 3457 //SDMA1_CHICKEN_BITS_2 3458 #define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 3459 #define SDMA1_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x4 3460 #define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 3461 #define SDMA1_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00000010L 3462 //SDMA1_STATUS3_REG 3463 #define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 3464 #define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 3465 #define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 3466 #define SDMA1_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 3467 #define SDMA1_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 3468 #define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 3469 #define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 3470 #define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 3471 #define SDMA1_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L 3472 #define SDMA1_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L 3473 //SDMA1_PHYSICAL_ADDR_LO 3474 #define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 3475 #define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 3476 #define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 3477 #define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 3478 #define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 3479 #define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 3480 #define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 3481 #define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 3482 //SDMA1_PHYSICAL_ADDR_HI 3483 #define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 3484 #define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 3485 //SDMA1_PHASE2_QUANTUM 3486 #define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT 0x0 3487 #define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT 0x8 3488 #define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 3489 #define SDMA1_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 3490 #define SDMA1_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 3491 #define SDMA1_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 3492 //SDMA1_ERROR_LOG 3493 #define SDMA1_ERROR_LOG__OVERRIDE__SHIFT 0x0 3494 #define SDMA1_ERROR_LOG__STATUS__SHIFT 0x10 3495 #define SDMA1_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 3496 #define SDMA1_ERROR_LOG__STATUS_MASK 0xFFFF0000L 3497 //SDMA1_PUB_DUMMY_REG0 3498 #define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 3499 #define SDMA1_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 3500 //SDMA1_PUB_DUMMY_REG1 3501 #define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 3502 #define SDMA1_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 3503 //SDMA1_PUB_DUMMY_REG2 3504 #define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 3505 #define SDMA1_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 3506 //SDMA1_PUB_DUMMY_REG3 3507 #define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 3508 #define SDMA1_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 3509 //SDMA1_F32_COUNTER 3510 #define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0 3511 #define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 3512 //SDMA1_PERFCNT_PERFCOUNTER0_CFG 3513 #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 3514 #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 3515 #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 3516 #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 3517 #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 3518 #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 3519 #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 3520 #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 3521 #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 3522 #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 3523 //SDMA1_PERFCNT_PERFCOUNTER1_CFG 3524 #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 3525 #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 3526 #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 3527 #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 3528 #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 3529 #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 3530 #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 3531 #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 3532 #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 3533 #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 3534 //SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL 3535 #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 3536 #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 3537 #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 3538 #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 3539 #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 3540 #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 3541 #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 3542 #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 3543 #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 3544 #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 3545 #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 3546 #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 3547 //SDMA1_PERFCNT_MISC_CNTL 3548 #define SDMA1_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 3549 #define SDMA1_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL 3550 //SDMA1_PERFCNT_PERFCOUNTER_LO 3551 #define SDMA1_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 3552 #define SDMA1_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 3553 //SDMA1_PERFCNT_PERFCOUNTER_HI 3554 #define SDMA1_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 3555 #define SDMA1_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 3556 #define SDMA1_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 3557 #define SDMA1_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 3558 //SDMA1_CRD_CNTL 3559 #define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 3560 #define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 3561 #define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 3562 #define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 3563 //SDMA1_ULV_CNTL 3564 #define SDMA1_ULV_CNTL__HYSTERESIS__SHIFT 0x0 3565 #define SDMA1_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b 3566 #define SDMA1_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c 3567 #define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 3568 #define SDMA1_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 3569 #define SDMA1_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 3570 #define SDMA1_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 3571 #define SDMA1_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L 3572 #define SDMA1_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L 3573 #define SDMA1_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 3574 #define SDMA1_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 3575 #define SDMA1_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 3576 //SDMA1_EA_DBIT_ADDR_DATA 3577 #define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 3578 #define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 3579 //SDMA1_EA_DBIT_ADDR_INDEX 3580 #define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 3581 #define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 3582 //SDMA1_STATUS4_REG 3583 #define SDMA1_STATUS4_REG__IDLE__SHIFT 0x0 3584 #define SDMA1_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2 3585 #define SDMA1_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3 3586 #define SDMA1_STATUS4_REG__MMHUB_RD_OUTSTANDING__SHIFT 0x4 3587 #define SDMA1_STATUS4_REG__MMHUB_WR_OUTSTANDING__SHIFT 0x5 3588 #define SDMA1_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x6 3589 #define SDMA1_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x7 3590 #define SDMA1_STATUS4_REG__REG_POLLING__SHIFT 0x8 3591 #define SDMA1_STATUS4_REG__MEM_POLLING__SHIFT 0x9 3592 #define SDMA1_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xa 3593 #define SDMA1_STATUS4_REG__UTCL2_WR_XNACK__SHIFT 0xc 3594 #define SDMA1_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0xe 3595 #define SDMA1_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x12 3596 #define SDMA1_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x13 3597 #define SDMA1_STATUS4_REG__IDLE_MASK 0x00000001L 3598 #define SDMA1_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L 3599 #define SDMA1_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L 3600 #define SDMA1_STATUS4_REG__MMHUB_RD_OUTSTANDING_MASK 0x00000010L 3601 #define SDMA1_STATUS4_REG__MMHUB_WR_OUTSTANDING_MASK 0x00000020L 3602 #define SDMA1_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000040L 3603 #define SDMA1_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000080L 3604 #define SDMA1_STATUS4_REG__REG_POLLING_MASK 0x00000100L 3605 #define SDMA1_STATUS4_REG__MEM_POLLING_MASK 0x00000200L 3606 #define SDMA1_STATUS4_REG__UTCL2_RD_XNACK_MASK 0x00000C00L 3607 #define SDMA1_STATUS4_REG__UTCL2_WR_XNACK_MASK 0x00003000L 3608 #define SDMA1_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x0003C000L 3609 #define SDMA1_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00040000L 3610 #define SDMA1_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00080000L 3611 //SDMA1_SCRATCH_RAM_DATA 3612 #define SDMA1_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 3613 #define SDMA1_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL 3614 //SDMA1_SCRATCH_RAM_ADDR 3615 #define SDMA1_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 3616 #define SDMA1_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL 3617 //SDMA1_CE_CTRL 3618 #define SDMA1_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 3619 #define SDMA1_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 3620 #define SDMA1_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5 3621 #define SDMA1_CE_CTRL__RESERVED__SHIFT 0x8 3622 #define SDMA1_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L 3623 #define SDMA1_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L 3624 #define SDMA1_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L 3625 #define SDMA1_CE_CTRL__RESERVED_MASK 0xFFFFFF00L 3626 //SDMA1_RAS_STATUS 3627 #define SDMA1_RAS_STATUS__RB_FETCH_ECC__SHIFT 0x0 3628 #define SDMA1_RAS_STATUS__IB_FETCH_ECC__SHIFT 0x1 3629 #define SDMA1_RAS_STATUS__F32_DATA_ECC__SHIFT 0x2 3630 #define SDMA1_RAS_STATUS__SEM_WPTR_ATOMIC_ECC__SHIFT 0x3 3631 #define SDMA1_RAS_STATUS__COPY_DATA_ECC__SHIFT 0x4 3632 #define SDMA1_RAS_STATUS__SRAM_ECC__SHIFT 0x5 3633 #define SDMA1_RAS_STATUS__RB_FETCH_NACK_GEN_ERR__SHIFT 0x8 3634 #define SDMA1_RAS_STATUS__IB_FETCH_NACK_GEN_ERR__SHIFT 0x9 3635 #define SDMA1_RAS_STATUS__F32_DATA_NACK_GEN_ERR__SHIFT 0xa 3636 #define SDMA1_RAS_STATUS__COPY_DATA_NACK_GEN_ERR__SHIFT 0xb 3637 #define SDMA1_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR__SHIFT 0xc 3638 #define SDMA1_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR__SHIFT 0xd 3639 #define SDMA1_RAS_STATUS__RB_FETCH_ECC_MASK 0x00000001L 3640 #define SDMA1_RAS_STATUS__IB_FETCH_ECC_MASK 0x00000002L 3641 #define SDMA1_RAS_STATUS__F32_DATA_ECC_MASK 0x00000004L 3642 #define SDMA1_RAS_STATUS__SEM_WPTR_ATOMIC_ECC_MASK 0x00000008L 3643 #define SDMA1_RAS_STATUS__COPY_DATA_ECC_MASK 0x00000010L 3644 #define SDMA1_RAS_STATUS__SRAM_ECC_MASK 0x00000020L 3645 #define SDMA1_RAS_STATUS__RB_FETCH_NACK_GEN_ERR_MASK 0x00000100L 3646 #define SDMA1_RAS_STATUS__IB_FETCH_NACK_GEN_ERR_MASK 0x00000200L 3647 #define SDMA1_RAS_STATUS__F32_DATA_NACK_GEN_ERR_MASK 0x00000400L 3648 #define SDMA1_RAS_STATUS__COPY_DATA_NACK_GEN_ERR_MASK 0x00000800L 3649 #define SDMA1_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR_MASK 0x00001000L 3650 #define SDMA1_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR_MASK 0x00002000L 3651 //SDMA1_CLK_STATUS 3652 #define SDMA1_CLK_STATUS__DYN_CLK__SHIFT 0x0 3653 #define SDMA1_CLK_STATUS__PTR_CLK__SHIFT 0x1 3654 #define SDMA1_CLK_STATUS__REG_CLK__SHIFT 0x2 3655 #define SDMA1_CLK_STATUS__F32_CLK__SHIFT 0x3 3656 #define SDMA1_CLK_STATUS__DYN_CLK_MASK 0x00000001L 3657 #define SDMA1_CLK_STATUS__PTR_CLK_MASK 0x00000002L 3658 #define SDMA1_CLK_STATUS__REG_CLK_MASK 0x00000004L 3659 #define SDMA1_CLK_STATUS__F32_CLK_MASK 0x00000008L 3660 //SDMA1_GFX_RB_CNTL 3661 #define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 3662 #define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 3663 #define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 3664 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 3665 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 3666 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 3667 #define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 3668 #define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 3669 #define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 3670 #define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL 3671 #define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 3672 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 3673 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 3674 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 3675 #define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 3676 #define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 3677 //SDMA1_GFX_RB_BASE 3678 #define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 3679 #define SDMA1_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 3680 //SDMA1_GFX_RB_BASE_HI 3681 #define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 3682 #define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 3683 //SDMA1_GFX_RB_RPTR 3684 #define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x0 3685 #define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 3686 //SDMA1_GFX_RB_RPTR_HI 3687 #define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 3688 #define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 3689 //SDMA1_GFX_RB_WPTR 3690 #define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x0 3691 #define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 3692 //SDMA1_GFX_RB_WPTR_HI 3693 #define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 3694 #define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 3695 //SDMA1_GFX_RB_WPTR_POLL_CNTL 3696 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 3697 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 3698 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 3699 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 3700 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 3701 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 3702 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 3703 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 3704 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 3705 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 3706 //SDMA1_GFX_RB_RPTR_ADDR_HI 3707 #define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 3708 #define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 3709 //SDMA1_GFX_RB_RPTR_ADDR_LO 3710 #define SDMA1_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 3711 #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 3712 #define SDMA1_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 3713 #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 3714 //SDMA1_GFX_IB_CNTL 3715 #define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 3716 #define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 3717 #define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 3718 #define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 3719 #define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 3720 #define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 3721 #define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 3722 #define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 3723 //SDMA1_GFX_IB_RPTR 3724 #define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 3725 #define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 3726 //SDMA1_GFX_IB_OFFSET 3727 #define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 3728 #define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 3729 //SDMA1_GFX_IB_BASE_LO 3730 #define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 3731 #define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 3732 //SDMA1_GFX_IB_BASE_HI 3733 #define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 3734 #define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 3735 //SDMA1_GFX_IB_SIZE 3736 #define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 3737 #define SDMA1_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 3738 //SDMA1_GFX_SKIP_CNTL 3739 #define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 3740 #define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 3741 //SDMA1_GFX_CONTEXT_STATUS 3742 #define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 3743 #define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 3744 #define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 3745 #define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 3746 #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 3747 #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 3748 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 3749 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 3750 #define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 3751 #define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 3752 #define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 3753 #define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 3754 #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 3755 #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 3756 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 3757 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 3758 //SDMA1_GFX_DOORBELL 3759 #define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c 3760 #define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 3761 #define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000L 3762 #define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 3763 //SDMA1_GFX_CONTEXT_CNTL 3764 #define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 3765 #define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 3766 #define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 3767 #define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0x0F000000L 3768 //SDMA1_GFX_STATUS 3769 #define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 3770 #define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 3771 #define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 3772 #define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 3773 //SDMA1_GFX_DOORBELL_LOG 3774 #define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 3775 #define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 3776 #define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 3777 #define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 3778 //SDMA1_GFX_WATERMARK 3779 #define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 3780 #define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 3781 #define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 3782 #define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 3783 //SDMA1_GFX_DOORBELL_OFFSET 3784 #define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 3785 #define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 3786 //SDMA1_GFX_CSA_ADDR_LO 3787 #define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 3788 #define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 3789 //SDMA1_GFX_CSA_ADDR_HI 3790 #define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 3791 #define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 3792 //SDMA1_GFX_IB_SUB_REMAIN 3793 #define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 3794 #define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 3795 //SDMA1_GFX_PREEMPT 3796 #define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 3797 #define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 3798 //SDMA1_GFX_DUMMY_REG 3799 #define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 3800 #define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 3801 //SDMA1_GFX_RB_WPTR_POLL_ADDR_HI 3802 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 3803 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 3804 //SDMA1_GFX_RB_WPTR_POLL_ADDR_LO 3805 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 3806 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 3807 //SDMA1_GFX_RB_AQL_CNTL 3808 #define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 3809 #define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 3810 #define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 3811 #define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 3812 #define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 3813 #define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 3814 //SDMA1_GFX_MINOR_PTR_UPDATE 3815 #define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 3816 #define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 3817 //SDMA1_GFX_MIDCMD_DATA0 3818 #define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 3819 #define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 3820 //SDMA1_GFX_MIDCMD_DATA1 3821 #define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 3822 #define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 3823 //SDMA1_GFX_MIDCMD_DATA2 3824 #define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 3825 #define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 3826 //SDMA1_GFX_MIDCMD_DATA3 3827 #define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 3828 #define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 3829 //SDMA1_GFX_MIDCMD_DATA4 3830 #define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 3831 #define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 3832 //SDMA1_GFX_MIDCMD_DATA5 3833 #define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 3834 #define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 3835 //SDMA1_GFX_MIDCMD_DATA6 3836 #define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 3837 #define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 3838 //SDMA1_GFX_MIDCMD_DATA7 3839 #define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 3840 #define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 3841 //SDMA1_GFX_MIDCMD_DATA8 3842 #define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 3843 #define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 3844 //SDMA1_GFX_MIDCMD_DATA9 3845 #define SDMA1_GFX_MIDCMD_DATA9__DATA9__SHIFT 0x0 3846 #define SDMA1_GFX_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 3847 //SDMA1_GFX_MIDCMD_DATA10 3848 #define SDMA1_GFX_MIDCMD_DATA10__DATA10__SHIFT 0x0 3849 #define SDMA1_GFX_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 3850 //SDMA1_GFX_MIDCMD_CNTL 3851 #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 3852 #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 3853 #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 3854 #define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 3855 #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 3856 #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 3857 #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 3858 #define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 3859 //SDMA1_PAGE_RB_CNTL 3860 #define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 3861 #define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 3862 #define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 3863 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 3864 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 3865 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 3866 #define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 3867 #define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 3868 #define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 3869 #define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL 3870 #define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 3871 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 3872 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 3873 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 3874 #define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 3875 #define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 3876 //SDMA1_PAGE_RB_BASE 3877 #define SDMA1_PAGE_RB_BASE__ADDR__SHIFT 0x0 3878 #define SDMA1_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 3879 //SDMA1_PAGE_RB_BASE_HI 3880 #define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 3881 #define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 3882 //SDMA1_PAGE_RB_RPTR 3883 #define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 3884 #define SDMA1_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 3885 //SDMA1_PAGE_RB_RPTR_HI 3886 #define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 3887 #define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 3888 //SDMA1_PAGE_RB_WPTR 3889 #define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 3890 #define SDMA1_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 3891 //SDMA1_PAGE_RB_WPTR_HI 3892 #define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 3893 #define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 3894 //SDMA1_PAGE_RB_WPTR_POLL_CNTL 3895 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 3896 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 3897 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 3898 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 3899 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 3900 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 3901 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 3902 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 3903 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 3904 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 3905 //SDMA1_PAGE_RB_RPTR_ADDR_HI 3906 #define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 3907 #define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 3908 //SDMA1_PAGE_RB_RPTR_ADDR_LO 3909 #define SDMA1_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 3910 #define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 3911 #define SDMA1_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 3912 #define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 3913 //SDMA1_PAGE_IB_CNTL 3914 #define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 3915 #define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 3916 #define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 3917 #define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 3918 #define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 3919 #define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 3920 #define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 3921 #define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 3922 //SDMA1_PAGE_IB_RPTR 3923 #define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 3924 #define SDMA1_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 3925 //SDMA1_PAGE_IB_OFFSET 3926 #define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 3927 #define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 3928 //SDMA1_PAGE_IB_BASE_LO 3929 #define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 3930 #define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 3931 //SDMA1_PAGE_IB_BASE_HI 3932 #define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 3933 #define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 3934 //SDMA1_PAGE_IB_SIZE 3935 #define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT 0x0 3936 #define SDMA1_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 3937 //SDMA1_PAGE_SKIP_CNTL 3938 #define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 3939 #define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 3940 //SDMA1_PAGE_CONTEXT_STATUS 3941 #define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 3942 #define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 3943 #define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 3944 #define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 3945 #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 3946 #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 3947 #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 3948 #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 3949 #define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 3950 #define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 3951 #define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 3952 #define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 3953 #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 3954 #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 3955 #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 3956 #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 3957 //SDMA1_PAGE_DOORBELL 3958 #define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 3959 #define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 3960 #define SDMA1_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 3961 #define SDMA1_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 3962 //SDMA1_PAGE_STATUS 3963 #define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 3964 #define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 3965 #define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 3966 #define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 3967 //SDMA1_PAGE_DOORBELL_LOG 3968 #define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 3969 #define SDMA1_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 3970 #define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 3971 #define SDMA1_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 3972 //SDMA1_PAGE_WATERMARK 3973 #define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 3974 #define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 3975 #define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 3976 #define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 3977 //SDMA1_PAGE_DOORBELL_OFFSET 3978 #define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 3979 #define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 3980 //SDMA1_PAGE_CSA_ADDR_LO 3981 #define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 3982 #define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 3983 //SDMA1_PAGE_CSA_ADDR_HI 3984 #define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 3985 #define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 3986 //SDMA1_PAGE_IB_SUB_REMAIN 3987 #define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 3988 #define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 3989 //SDMA1_PAGE_PREEMPT 3990 #define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 3991 #define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 3992 //SDMA1_PAGE_DUMMY_REG 3993 #define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 3994 #define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 3995 //SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 3996 #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 3997 #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 3998 //SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 3999 #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 4000 #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 4001 //SDMA1_PAGE_RB_AQL_CNTL 4002 #define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 4003 #define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 4004 #define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 4005 #define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 4006 #define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 4007 #define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 4008 //SDMA1_PAGE_MINOR_PTR_UPDATE 4009 #define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 4010 #define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 4011 //SDMA1_PAGE_MIDCMD_DATA0 4012 #define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 4013 #define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 4014 //SDMA1_PAGE_MIDCMD_DATA1 4015 #define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 4016 #define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 4017 //SDMA1_PAGE_MIDCMD_DATA2 4018 #define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 4019 #define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 4020 //SDMA1_PAGE_MIDCMD_DATA3 4021 #define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 4022 #define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 4023 //SDMA1_PAGE_MIDCMD_DATA4 4024 #define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 4025 #define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 4026 //SDMA1_PAGE_MIDCMD_DATA5 4027 #define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 4028 #define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 4029 //SDMA1_PAGE_MIDCMD_DATA6 4030 #define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 4031 #define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 4032 //SDMA1_PAGE_MIDCMD_DATA7 4033 #define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 4034 #define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 4035 //SDMA1_PAGE_MIDCMD_DATA8 4036 #define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 4037 #define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 4038 //SDMA1_PAGE_MIDCMD_DATA9 4039 #define SDMA1_PAGE_MIDCMD_DATA9__DATA9__SHIFT 0x0 4040 #define SDMA1_PAGE_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 4041 //SDMA1_PAGE_MIDCMD_DATA10 4042 #define SDMA1_PAGE_MIDCMD_DATA10__DATA10__SHIFT 0x0 4043 #define SDMA1_PAGE_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 4044 //SDMA1_PAGE_MIDCMD_CNTL 4045 #define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 4046 #define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 4047 #define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 4048 #define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 4049 #define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 4050 #define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 4051 #define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 4052 #define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 4053 //SDMA1_RLC0_RB_CNTL 4054 #define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 4055 #define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 4056 #define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 4057 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 4058 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 4059 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 4060 #define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 4061 #define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 4062 #define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 4063 #define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL 4064 #define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 4065 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 4066 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 4067 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 4068 #define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 4069 #define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 4070 //SDMA1_RLC0_RB_BASE 4071 #define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 4072 #define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 4073 //SDMA1_RLC0_RB_BASE_HI 4074 #define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 4075 #define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 4076 //SDMA1_RLC0_RB_RPTR 4077 #define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 4078 #define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 4079 //SDMA1_RLC0_RB_RPTR_HI 4080 #define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 4081 #define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 4082 //SDMA1_RLC0_RB_WPTR 4083 #define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 4084 #define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 4085 //SDMA1_RLC0_RB_WPTR_HI 4086 #define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 4087 #define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 4088 //SDMA1_RLC0_RB_WPTR_POLL_CNTL 4089 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 4090 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 4091 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 4092 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 4093 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 4094 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 4095 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 4096 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 4097 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 4098 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 4099 //SDMA1_RLC0_RB_RPTR_ADDR_HI 4100 #define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 4101 #define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 4102 //SDMA1_RLC0_RB_RPTR_ADDR_LO 4103 #define SDMA1_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 4104 #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 4105 #define SDMA1_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 4106 #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 4107 //SDMA1_RLC0_IB_CNTL 4108 #define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 4109 #define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 4110 #define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 4111 #define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 4112 #define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 4113 #define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 4114 #define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 4115 #define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 4116 //SDMA1_RLC0_IB_RPTR 4117 #define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 4118 #define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 4119 //SDMA1_RLC0_IB_OFFSET 4120 #define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 4121 #define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 4122 //SDMA1_RLC0_IB_BASE_LO 4123 #define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 4124 #define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 4125 //SDMA1_RLC0_IB_BASE_HI 4126 #define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 4127 #define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 4128 //SDMA1_RLC0_IB_SIZE 4129 #define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 4130 #define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 4131 //SDMA1_RLC0_SKIP_CNTL 4132 #define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 4133 #define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 4134 //SDMA1_RLC0_CONTEXT_STATUS 4135 #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 4136 #define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 4137 #define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 4138 #define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 4139 #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 4140 #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 4141 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 4142 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 4143 #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 4144 #define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 4145 #define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 4146 #define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 4147 #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 4148 #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 4149 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 4150 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 4151 //SDMA1_RLC0_DOORBELL 4152 #define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 4153 #define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 4154 #define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 4155 #define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 4156 //SDMA1_RLC0_STATUS 4157 #define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 4158 #define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 4159 #define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 4160 #define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 4161 //SDMA1_RLC0_DOORBELL_LOG 4162 #define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 4163 #define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 4164 #define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 4165 #define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 4166 //SDMA1_RLC0_WATERMARK 4167 #define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 4168 #define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 4169 #define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 4170 #define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 4171 //SDMA1_RLC0_DOORBELL_OFFSET 4172 #define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 4173 #define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 4174 //SDMA1_RLC0_CSA_ADDR_LO 4175 #define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 4176 #define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 4177 //SDMA1_RLC0_CSA_ADDR_HI 4178 #define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 4179 #define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 4180 //SDMA1_RLC0_IB_SUB_REMAIN 4181 #define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 4182 #define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 4183 //SDMA1_RLC0_PREEMPT 4184 #define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 4185 #define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 4186 //SDMA1_RLC0_DUMMY_REG 4187 #define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 4188 #define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 4189 //SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 4190 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 4191 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 4192 //SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 4193 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 4194 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 4195 //SDMA1_RLC0_RB_AQL_CNTL 4196 #define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 4197 #define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 4198 #define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 4199 #define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 4200 #define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 4201 #define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 4202 //SDMA1_RLC0_MINOR_PTR_UPDATE 4203 #define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 4204 #define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 4205 //SDMA1_RLC0_MIDCMD_DATA0 4206 #define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 4207 #define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 4208 //SDMA1_RLC0_MIDCMD_DATA1 4209 #define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 4210 #define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 4211 //SDMA1_RLC0_MIDCMD_DATA2 4212 #define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 4213 #define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 4214 //SDMA1_RLC0_MIDCMD_DATA3 4215 #define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 4216 #define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 4217 //SDMA1_RLC0_MIDCMD_DATA4 4218 #define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 4219 #define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 4220 //SDMA1_RLC0_MIDCMD_DATA5 4221 #define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 4222 #define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 4223 //SDMA1_RLC0_MIDCMD_DATA6 4224 #define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 4225 #define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 4226 //SDMA1_RLC0_MIDCMD_DATA7 4227 #define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 4228 #define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 4229 //SDMA1_RLC0_MIDCMD_DATA8 4230 #define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 4231 #define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 4232 //SDMA1_RLC0_MIDCMD_DATA9 4233 #define SDMA1_RLC0_MIDCMD_DATA9__DATA9__SHIFT 0x0 4234 #define SDMA1_RLC0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 4235 //SDMA1_RLC0_MIDCMD_DATA10 4236 #define SDMA1_RLC0_MIDCMD_DATA10__DATA10__SHIFT 0x0 4237 #define SDMA1_RLC0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 4238 //SDMA1_RLC0_MIDCMD_CNTL 4239 #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 4240 #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 4241 #define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 4242 #define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 4243 #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 4244 #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 4245 #define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 4246 #define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 4247 //SDMA1_RLC1_RB_CNTL 4248 #define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 4249 #define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 4250 #define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 4251 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 4252 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 4253 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 4254 #define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 4255 #define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 4256 #define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 4257 #define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL 4258 #define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 4259 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 4260 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 4261 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 4262 #define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 4263 #define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 4264 //SDMA1_RLC1_RB_BASE 4265 #define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 4266 #define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 4267 //SDMA1_RLC1_RB_BASE_HI 4268 #define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 4269 #define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 4270 //SDMA1_RLC1_RB_RPTR 4271 #define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 4272 #define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 4273 //SDMA1_RLC1_RB_RPTR_HI 4274 #define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 4275 #define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 4276 //SDMA1_RLC1_RB_WPTR 4277 #define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 4278 #define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 4279 //SDMA1_RLC1_RB_WPTR_HI 4280 #define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 4281 #define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 4282 //SDMA1_RLC1_RB_WPTR_POLL_CNTL 4283 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 4284 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 4285 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 4286 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 4287 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 4288 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 4289 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 4290 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 4291 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 4292 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 4293 //SDMA1_RLC1_RB_RPTR_ADDR_HI 4294 #define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 4295 #define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 4296 //SDMA1_RLC1_RB_RPTR_ADDR_LO 4297 #define SDMA1_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 4298 #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 4299 #define SDMA1_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 4300 #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 4301 //SDMA1_RLC1_IB_CNTL 4302 #define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 4303 #define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 4304 #define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 4305 #define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 4306 #define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 4307 #define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 4308 #define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 4309 #define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 4310 //SDMA1_RLC1_IB_RPTR 4311 #define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 4312 #define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 4313 //SDMA1_RLC1_IB_OFFSET 4314 #define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 4315 #define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 4316 //SDMA1_RLC1_IB_BASE_LO 4317 #define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 4318 #define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 4319 //SDMA1_RLC1_IB_BASE_HI 4320 #define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 4321 #define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 4322 //SDMA1_RLC1_IB_SIZE 4323 #define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 4324 #define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 4325 //SDMA1_RLC1_SKIP_CNTL 4326 #define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 4327 #define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 4328 //SDMA1_RLC1_CONTEXT_STATUS 4329 #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 4330 #define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 4331 #define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 4332 #define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 4333 #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 4334 #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 4335 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 4336 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 4337 #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 4338 #define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 4339 #define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 4340 #define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 4341 #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 4342 #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 4343 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 4344 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 4345 //SDMA1_RLC1_DOORBELL 4346 #define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 4347 #define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 4348 #define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 4349 #define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 4350 //SDMA1_RLC1_STATUS 4351 #define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 4352 #define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 4353 #define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 4354 #define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 4355 //SDMA1_RLC1_DOORBELL_LOG 4356 #define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 4357 #define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 4358 #define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 4359 #define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 4360 //SDMA1_RLC1_WATERMARK 4361 #define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 4362 #define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 4363 #define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 4364 #define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 4365 //SDMA1_RLC1_DOORBELL_OFFSET 4366 #define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 4367 #define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 4368 //SDMA1_RLC1_CSA_ADDR_LO 4369 #define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 4370 #define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 4371 //SDMA1_RLC1_CSA_ADDR_HI 4372 #define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 4373 #define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 4374 //SDMA1_RLC1_IB_SUB_REMAIN 4375 #define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 4376 #define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 4377 //SDMA1_RLC1_PREEMPT 4378 #define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 4379 #define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 4380 //SDMA1_RLC1_DUMMY_REG 4381 #define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 4382 #define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 4383 //SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 4384 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 4385 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 4386 //SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 4387 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 4388 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 4389 //SDMA1_RLC1_RB_AQL_CNTL 4390 #define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 4391 #define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 4392 #define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 4393 #define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 4394 #define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 4395 #define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 4396 //SDMA1_RLC1_MINOR_PTR_UPDATE 4397 #define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 4398 #define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 4399 //SDMA1_RLC1_MIDCMD_DATA0 4400 #define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 4401 #define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 4402 //SDMA1_RLC1_MIDCMD_DATA1 4403 #define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 4404 #define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 4405 //SDMA1_RLC1_MIDCMD_DATA2 4406 #define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 4407 #define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 4408 //SDMA1_RLC1_MIDCMD_DATA3 4409 #define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 4410 #define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 4411 //SDMA1_RLC1_MIDCMD_DATA4 4412 #define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 4413 #define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 4414 //SDMA1_RLC1_MIDCMD_DATA5 4415 #define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 4416 #define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 4417 //SDMA1_RLC1_MIDCMD_DATA6 4418 #define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 4419 #define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 4420 //SDMA1_RLC1_MIDCMD_DATA7 4421 #define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 4422 #define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 4423 //SDMA1_RLC1_MIDCMD_DATA8 4424 #define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 4425 #define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 4426 //SDMA1_RLC1_MIDCMD_DATA9 4427 #define SDMA1_RLC1_MIDCMD_DATA9__DATA9__SHIFT 0x0 4428 #define SDMA1_RLC1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 4429 //SDMA1_RLC1_MIDCMD_DATA10 4430 #define SDMA1_RLC1_MIDCMD_DATA10__DATA10__SHIFT 0x0 4431 #define SDMA1_RLC1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 4432 //SDMA1_RLC1_MIDCMD_CNTL 4433 #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 4434 #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 4435 #define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 4436 #define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 4437 #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 4438 #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 4439 #define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 4440 #define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 4441 //SDMA1_RLC2_RB_CNTL 4442 #define SDMA1_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 4443 #define SDMA1_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 4444 #define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 4445 #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 4446 #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 4447 #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 4448 #define SDMA1_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 4449 #define SDMA1_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 4450 #define SDMA1_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L 4451 #define SDMA1_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL 4452 #define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 4453 #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 4454 #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 4455 #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 4456 #define SDMA1_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L 4457 #define SDMA1_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L 4458 //SDMA1_RLC2_RB_BASE 4459 #define SDMA1_RLC2_RB_BASE__ADDR__SHIFT 0x0 4460 #define SDMA1_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL 4461 //SDMA1_RLC2_RB_BASE_HI 4462 #define SDMA1_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 4463 #define SDMA1_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 4464 //SDMA1_RLC2_RB_RPTR 4465 #define SDMA1_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 4466 #define SDMA1_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 4467 //SDMA1_RLC2_RB_RPTR_HI 4468 #define SDMA1_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 4469 #define SDMA1_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 4470 //SDMA1_RLC2_RB_WPTR 4471 #define SDMA1_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 4472 #define SDMA1_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 4473 //SDMA1_RLC2_RB_WPTR_HI 4474 #define SDMA1_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 4475 #define SDMA1_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 4476 //SDMA1_RLC2_RB_WPTR_POLL_CNTL 4477 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 4478 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 4479 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 4480 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 4481 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 4482 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 4483 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 4484 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 4485 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 4486 #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 4487 //SDMA1_RLC2_RB_RPTR_ADDR_HI 4488 #define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 4489 #define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 4490 //SDMA1_RLC2_RB_RPTR_ADDR_LO 4491 #define SDMA1_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 4492 #define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 4493 #define SDMA1_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 4494 #define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 4495 //SDMA1_RLC2_IB_CNTL 4496 #define SDMA1_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 4497 #define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 4498 #define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 4499 #define SDMA1_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 4500 #define SDMA1_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L 4501 #define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 4502 #define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 4503 #define SDMA1_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L 4504 //SDMA1_RLC2_IB_RPTR 4505 #define SDMA1_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 4506 #define SDMA1_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL 4507 //SDMA1_RLC2_IB_OFFSET 4508 #define SDMA1_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 4509 #define SDMA1_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 4510 //SDMA1_RLC2_IB_BASE_LO 4511 #define SDMA1_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 4512 #define SDMA1_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 4513 //SDMA1_RLC2_IB_BASE_HI 4514 #define SDMA1_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 4515 #define SDMA1_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 4516 //SDMA1_RLC2_IB_SIZE 4517 #define SDMA1_RLC2_IB_SIZE__SIZE__SHIFT 0x0 4518 #define SDMA1_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL 4519 //SDMA1_RLC2_SKIP_CNTL 4520 #define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 4521 #define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 4522 //SDMA1_RLC2_CONTEXT_STATUS 4523 #define SDMA1_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 4524 #define SDMA1_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 4525 #define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 4526 #define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 4527 #define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 4528 #define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 4529 #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 4530 #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 4531 #define SDMA1_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 4532 #define SDMA1_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L 4533 #define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 4534 #define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 4535 #define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 4536 #define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 4537 #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 4538 #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 4539 //SDMA1_RLC2_DOORBELL 4540 #define SDMA1_RLC2_DOORBELL__ENABLE__SHIFT 0x1c 4541 #define SDMA1_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e 4542 #define SDMA1_RLC2_DOORBELL__ENABLE_MASK 0x10000000L 4543 #define SDMA1_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L 4544 //SDMA1_RLC2_STATUS 4545 #define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 4546 #define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 4547 #define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 4548 #define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 4549 //SDMA1_RLC2_DOORBELL_LOG 4550 #define SDMA1_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 4551 #define SDMA1_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 4552 #define SDMA1_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 4553 #define SDMA1_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 4554 //SDMA1_RLC2_WATERMARK 4555 #define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 4556 #define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 4557 #define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 4558 #define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 4559 //SDMA1_RLC2_DOORBELL_OFFSET 4560 #define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 4561 #define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 4562 //SDMA1_RLC2_CSA_ADDR_LO 4563 #define SDMA1_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 4564 #define SDMA1_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 4565 //SDMA1_RLC2_CSA_ADDR_HI 4566 #define SDMA1_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 4567 #define SDMA1_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 4568 //SDMA1_RLC2_IB_SUB_REMAIN 4569 #define SDMA1_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 4570 #define SDMA1_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 4571 //SDMA1_RLC2_PREEMPT 4572 #define SDMA1_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 4573 #define SDMA1_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L 4574 //SDMA1_RLC2_DUMMY_REG 4575 #define SDMA1_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 4576 #define SDMA1_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 4577 //SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI 4578 #define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 4579 #define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 4580 //SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO 4581 #define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 4582 #define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 4583 //SDMA1_RLC2_RB_AQL_CNTL 4584 #define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 4585 #define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 4586 #define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 4587 #define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 4588 #define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 4589 #define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 4590 //SDMA1_RLC2_MINOR_PTR_UPDATE 4591 #define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 4592 #define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 4593 //SDMA1_RLC2_MIDCMD_DATA0 4594 #define SDMA1_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 4595 #define SDMA1_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 4596 //SDMA1_RLC2_MIDCMD_DATA1 4597 #define SDMA1_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 4598 #define SDMA1_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 4599 //SDMA1_RLC2_MIDCMD_DATA2 4600 #define SDMA1_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 4601 #define SDMA1_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 4602 //SDMA1_RLC2_MIDCMD_DATA3 4603 #define SDMA1_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 4604 #define SDMA1_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 4605 //SDMA1_RLC2_MIDCMD_DATA4 4606 #define SDMA1_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 4607 #define SDMA1_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 4608 //SDMA1_RLC2_MIDCMD_DATA5 4609 #define SDMA1_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 4610 #define SDMA1_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 4611 //SDMA1_RLC2_MIDCMD_DATA6 4612 #define SDMA1_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 4613 #define SDMA1_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 4614 //SDMA1_RLC2_MIDCMD_DATA7 4615 #define SDMA1_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 4616 #define SDMA1_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 4617 //SDMA1_RLC2_MIDCMD_DATA8 4618 #define SDMA1_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 4619 #define SDMA1_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 4620 //SDMA1_RLC2_MIDCMD_DATA9 4621 #define SDMA1_RLC2_MIDCMD_DATA9__DATA9__SHIFT 0x0 4622 #define SDMA1_RLC2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 4623 //SDMA1_RLC2_MIDCMD_DATA10 4624 #define SDMA1_RLC2_MIDCMD_DATA10__DATA10__SHIFT 0x0 4625 #define SDMA1_RLC2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 4626 //SDMA1_RLC2_MIDCMD_CNTL 4627 #define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 4628 #define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 4629 #define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 4630 #define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 4631 #define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 4632 #define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 4633 #define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 4634 #define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 4635 //SDMA1_RLC3_RB_CNTL 4636 #define SDMA1_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 4637 #define SDMA1_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 4638 #define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 4639 #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 4640 #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 4641 #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 4642 #define SDMA1_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 4643 #define SDMA1_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 4644 #define SDMA1_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L 4645 #define SDMA1_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL 4646 #define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 4647 #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 4648 #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 4649 #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 4650 #define SDMA1_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L 4651 #define SDMA1_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L 4652 //SDMA1_RLC3_RB_BASE 4653 #define SDMA1_RLC3_RB_BASE__ADDR__SHIFT 0x0 4654 #define SDMA1_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL 4655 //SDMA1_RLC3_RB_BASE_HI 4656 #define SDMA1_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 4657 #define SDMA1_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 4658 //SDMA1_RLC3_RB_RPTR 4659 #define SDMA1_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 4660 #define SDMA1_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 4661 //SDMA1_RLC3_RB_RPTR_HI 4662 #define SDMA1_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 4663 #define SDMA1_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 4664 //SDMA1_RLC3_RB_WPTR 4665 #define SDMA1_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 4666 #define SDMA1_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 4667 //SDMA1_RLC3_RB_WPTR_HI 4668 #define SDMA1_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 4669 #define SDMA1_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 4670 //SDMA1_RLC3_RB_WPTR_POLL_CNTL 4671 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 4672 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 4673 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 4674 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 4675 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 4676 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 4677 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 4678 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 4679 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 4680 #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 4681 //SDMA1_RLC3_RB_RPTR_ADDR_HI 4682 #define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 4683 #define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 4684 //SDMA1_RLC3_RB_RPTR_ADDR_LO 4685 #define SDMA1_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 4686 #define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 4687 #define SDMA1_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 4688 #define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 4689 //SDMA1_RLC3_IB_CNTL 4690 #define SDMA1_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 4691 #define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 4692 #define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 4693 #define SDMA1_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 4694 #define SDMA1_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L 4695 #define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 4696 #define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 4697 #define SDMA1_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L 4698 //SDMA1_RLC3_IB_RPTR 4699 #define SDMA1_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 4700 #define SDMA1_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL 4701 //SDMA1_RLC3_IB_OFFSET 4702 #define SDMA1_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 4703 #define SDMA1_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 4704 //SDMA1_RLC3_IB_BASE_LO 4705 #define SDMA1_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 4706 #define SDMA1_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 4707 //SDMA1_RLC3_IB_BASE_HI 4708 #define SDMA1_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 4709 #define SDMA1_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 4710 //SDMA1_RLC3_IB_SIZE 4711 #define SDMA1_RLC3_IB_SIZE__SIZE__SHIFT 0x0 4712 #define SDMA1_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL 4713 //SDMA1_RLC3_SKIP_CNTL 4714 #define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 4715 #define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 4716 //SDMA1_RLC3_CONTEXT_STATUS 4717 #define SDMA1_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 4718 #define SDMA1_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 4719 #define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 4720 #define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 4721 #define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 4722 #define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 4723 #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 4724 #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 4725 #define SDMA1_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 4726 #define SDMA1_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L 4727 #define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 4728 #define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 4729 #define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 4730 #define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 4731 #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 4732 #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 4733 //SDMA1_RLC3_DOORBELL 4734 #define SDMA1_RLC3_DOORBELL__ENABLE__SHIFT 0x1c 4735 #define SDMA1_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e 4736 #define SDMA1_RLC3_DOORBELL__ENABLE_MASK 0x10000000L 4737 #define SDMA1_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L 4738 //SDMA1_RLC3_STATUS 4739 #define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 4740 #define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 4741 #define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 4742 #define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 4743 //SDMA1_RLC3_DOORBELL_LOG 4744 #define SDMA1_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 4745 #define SDMA1_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 4746 #define SDMA1_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 4747 #define SDMA1_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 4748 //SDMA1_RLC3_WATERMARK 4749 #define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 4750 #define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 4751 #define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 4752 #define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 4753 //SDMA1_RLC3_DOORBELL_OFFSET 4754 #define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 4755 #define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 4756 //SDMA1_RLC3_CSA_ADDR_LO 4757 #define SDMA1_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 4758 #define SDMA1_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 4759 //SDMA1_RLC3_CSA_ADDR_HI 4760 #define SDMA1_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 4761 #define SDMA1_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 4762 //SDMA1_RLC3_IB_SUB_REMAIN 4763 #define SDMA1_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 4764 #define SDMA1_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 4765 //SDMA1_RLC3_PREEMPT 4766 #define SDMA1_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 4767 #define SDMA1_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L 4768 //SDMA1_RLC3_DUMMY_REG 4769 #define SDMA1_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 4770 #define SDMA1_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 4771 //SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI 4772 #define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 4773 #define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 4774 //SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO 4775 #define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 4776 #define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 4777 //SDMA1_RLC3_RB_AQL_CNTL 4778 #define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 4779 #define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 4780 #define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 4781 #define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 4782 #define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 4783 #define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 4784 //SDMA1_RLC3_MINOR_PTR_UPDATE 4785 #define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 4786 #define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 4787 //SDMA1_RLC3_MIDCMD_DATA0 4788 #define SDMA1_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 4789 #define SDMA1_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 4790 //SDMA1_RLC3_MIDCMD_DATA1 4791 #define SDMA1_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 4792 #define SDMA1_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 4793 //SDMA1_RLC3_MIDCMD_DATA2 4794 #define SDMA1_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 4795 #define SDMA1_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 4796 //SDMA1_RLC3_MIDCMD_DATA3 4797 #define SDMA1_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 4798 #define SDMA1_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 4799 //SDMA1_RLC3_MIDCMD_DATA4 4800 #define SDMA1_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 4801 #define SDMA1_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 4802 //SDMA1_RLC3_MIDCMD_DATA5 4803 #define SDMA1_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 4804 #define SDMA1_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 4805 //SDMA1_RLC3_MIDCMD_DATA6 4806 #define SDMA1_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 4807 #define SDMA1_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 4808 //SDMA1_RLC3_MIDCMD_DATA7 4809 #define SDMA1_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 4810 #define SDMA1_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 4811 //SDMA1_RLC3_MIDCMD_DATA8 4812 #define SDMA1_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 4813 #define SDMA1_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 4814 //SDMA1_RLC3_MIDCMD_DATA9 4815 #define SDMA1_RLC3_MIDCMD_DATA9__DATA9__SHIFT 0x0 4816 #define SDMA1_RLC3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 4817 //SDMA1_RLC3_MIDCMD_DATA10 4818 #define SDMA1_RLC3_MIDCMD_DATA10__DATA10__SHIFT 0x0 4819 #define SDMA1_RLC3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 4820 //SDMA1_RLC3_MIDCMD_CNTL 4821 #define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 4822 #define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 4823 #define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 4824 #define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 4825 #define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 4826 #define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 4827 #define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 4828 #define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 4829 //SDMA1_RLC4_RB_CNTL 4830 #define SDMA1_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 4831 #define SDMA1_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 4832 #define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 4833 #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 4834 #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 4835 #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 4836 #define SDMA1_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 4837 #define SDMA1_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 4838 #define SDMA1_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L 4839 #define SDMA1_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL 4840 #define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 4841 #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 4842 #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 4843 #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 4844 #define SDMA1_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L 4845 #define SDMA1_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L 4846 //SDMA1_RLC4_RB_BASE 4847 #define SDMA1_RLC4_RB_BASE__ADDR__SHIFT 0x0 4848 #define SDMA1_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL 4849 //SDMA1_RLC4_RB_BASE_HI 4850 #define SDMA1_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 4851 #define SDMA1_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 4852 //SDMA1_RLC4_RB_RPTR 4853 #define SDMA1_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 4854 #define SDMA1_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 4855 //SDMA1_RLC4_RB_RPTR_HI 4856 #define SDMA1_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 4857 #define SDMA1_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 4858 //SDMA1_RLC4_RB_WPTR 4859 #define SDMA1_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 4860 #define SDMA1_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 4861 //SDMA1_RLC4_RB_WPTR_HI 4862 #define SDMA1_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 4863 #define SDMA1_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 4864 //SDMA1_RLC4_RB_WPTR_POLL_CNTL 4865 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 4866 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 4867 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 4868 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 4869 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 4870 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 4871 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 4872 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 4873 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 4874 #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 4875 //SDMA1_RLC4_RB_RPTR_ADDR_HI 4876 #define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 4877 #define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 4878 //SDMA1_RLC4_RB_RPTR_ADDR_LO 4879 #define SDMA1_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 4880 #define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 4881 #define SDMA1_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 4882 #define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 4883 //SDMA1_RLC4_IB_CNTL 4884 #define SDMA1_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 4885 #define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 4886 #define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 4887 #define SDMA1_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 4888 #define SDMA1_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L 4889 #define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 4890 #define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 4891 #define SDMA1_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L 4892 //SDMA1_RLC4_IB_RPTR 4893 #define SDMA1_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 4894 #define SDMA1_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL 4895 //SDMA1_RLC4_IB_OFFSET 4896 #define SDMA1_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 4897 #define SDMA1_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 4898 //SDMA1_RLC4_IB_BASE_LO 4899 #define SDMA1_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 4900 #define SDMA1_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 4901 //SDMA1_RLC4_IB_BASE_HI 4902 #define SDMA1_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 4903 #define SDMA1_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 4904 //SDMA1_RLC4_IB_SIZE 4905 #define SDMA1_RLC4_IB_SIZE__SIZE__SHIFT 0x0 4906 #define SDMA1_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL 4907 //SDMA1_RLC4_SKIP_CNTL 4908 #define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 4909 #define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 4910 //SDMA1_RLC4_CONTEXT_STATUS 4911 #define SDMA1_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 4912 #define SDMA1_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 4913 #define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 4914 #define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 4915 #define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 4916 #define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 4917 #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 4918 #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 4919 #define SDMA1_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 4920 #define SDMA1_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L 4921 #define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 4922 #define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 4923 #define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 4924 #define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 4925 #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 4926 #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 4927 //SDMA1_RLC4_DOORBELL 4928 #define SDMA1_RLC4_DOORBELL__ENABLE__SHIFT 0x1c 4929 #define SDMA1_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e 4930 #define SDMA1_RLC4_DOORBELL__ENABLE_MASK 0x10000000L 4931 #define SDMA1_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L 4932 //SDMA1_RLC4_STATUS 4933 #define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 4934 #define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 4935 #define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 4936 #define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 4937 //SDMA1_RLC4_DOORBELL_LOG 4938 #define SDMA1_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 4939 #define SDMA1_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 4940 #define SDMA1_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 4941 #define SDMA1_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 4942 //SDMA1_RLC4_WATERMARK 4943 #define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 4944 #define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 4945 #define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 4946 #define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 4947 //SDMA1_RLC4_DOORBELL_OFFSET 4948 #define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 4949 #define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 4950 //SDMA1_RLC4_CSA_ADDR_LO 4951 #define SDMA1_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 4952 #define SDMA1_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 4953 //SDMA1_RLC4_CSA_ADDR_HI 4954 #define SDMA1_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 4955 #define SDMA1_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 4956 //SDMA1_RLC4_IB_SUB_REMAIN 4957 #define SDMA1_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 4958 #define SDMA1_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 4959 //SDMA1_RLC4_PREEMPT 4960 #define SDMA1_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 4961 #define SDMA1_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L 4962 //SDMA1_RLC4_DUMMY_REG 4963 #define SDMA1_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 4964 #define SDMA1_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 4965 //SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI 4966 #define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 4967 #define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 4968 //SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO 4969 #define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 4970 #define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 4971 //SDMA1_RLC4_RB_AQL_CNTL 4972 #define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 4973 #define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 4974 #define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 4975 #define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 4976 #define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 4977 #define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 4978 //SDMA1_RLC4_MINOR_PTR_UPDATE 4979 #define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 4980 #define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 4981 //SDMA1_RLC4_MIDCMD_DATA0 4982 #define SDMA1_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 4983 #define SDMA1_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 4984 //SDMA1_RLC4_MIDCMD_DATA1 4985 #define SDMA1_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 4986 #define SDMA1_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 4987 //SDMA1_RLC4_MIDCMD_DATA2 4988 #define SDMA1_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 4989 #define SDMA1_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 4990 //SDMA1_RLC4_MIDCMD_DATA3 4991 #define SDMA1_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 4992 #define SDMA1_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 4993 //SDMA1_RLC4_MIDCMD_DATA4 4994 #define SDMA1_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 4995 #define SDMA1_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 4996 //SDMA1_RLC4_MIDCMD_DATA5 4997 #define SDMA1_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 4998 #define SDMA1_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 4999 //SDMA1_RLC4_MIDCMD_DATA6 5000 #define SDMA1_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 5001 #define SDMA1_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 5002 //SDMA1_RLC4_MIDCMD_DATA7 5003 #define SDMA1_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 5004 #define SDMA1_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 5005 //SDMA1_RLC4_MIDCMD_DATA8 5006 #define SDMA1_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 5007 #define SDMA1_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 5008 //SDMA1_RLC4_MIDCMD_DATA9 5009 #define SDMA1_RLC4_MIDCMD_DATA9__DATA9__SHIFT 0x0 5010 #define SDMA1_RLC4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 5011 //SDMA1_RLC4_MIDCMD_DATA10 5012 #define SDMA1_RLC4_MIDCMD_DATA10__DATA10__SHIFT 0x0 5013 #define SDMA1_RLC4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 5014 //SDMA1_RLC4_MIDCMD_CNTL 5015 #define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 5016 #define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 5017 #define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 5018 #define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 5019 #define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 5020 #define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 5021 #define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 5022 #define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 5023 //SDMA1_RLC5_RB_CNTL 5024 #define SDMA1_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 5025 #define SDMA1_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 5026 #define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 5027 #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 5028 #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 5029 #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 5030 #define SDMA1_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 5031 #define SDMA1_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 5032 #define SDMA1_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L 5033 #define SDMA1_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL 5034 #define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 5035 #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 5036 #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 5037 #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 5038 #define SDMA1_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L 5039 #define SDMA1_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L 5040 //SDMA1_RLC5_RB_BASE 5041 #define SDMA1_RLC5_RB_BASE__ADDR__SHIFT 0x0 5042 #define SDMA1_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL 5043 //SDMA1_RLC5_RB_BASE_HI 5044 #define SDMA1_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 5045 #define SDMA1_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 5046 //SDMA1_RLC5_RB_RPTR 5047 #define SDMA1_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 5048 #define SDMA1_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 5049 //SDMA1_RLC5_RB_RPTR_HI 5050 #define SDMA1_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 5051 #define SDMA1_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 5052 //SDMA1_RLC5_RB_WPTR 5053 #define SDMA1_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 5054 #define SDMA1_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 5055 //SDMA1_RLC5_RB_WPTR_HI 5056 #define SDMA1_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 5057 #define SDMA1_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 5058 //SDMA1_RLC5_RB_WPTR_POLL_CNTL 5059 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 5060 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 5061 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 5062 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 5063 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 5064 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 5065 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 5066 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 5067 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 5068 #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 5069 //SDMA1_RLC5_RB_RPTR_ADDR_HI 5070 #define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 5071 #define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 5072 //SDMA1_RLC5_RB_RPTR_ADDR_LO 5073 #define SDMA1_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 5074 #define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 5075 #define SDMA1_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 5076 #define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 5077 //SDMA1_RLC5_IB_CNTL 5078 #define SDMA1_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 5079 #define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 5080 #define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 5081 #define SDMA1_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 5082 #define SDMA1_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L 5083 #define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 5084 #define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 5085 #define SDMA1_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L 5086 //SDMA1_RLC5_IB_RPTR 5087 #define SDMA1_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 5088 #define SDMA1_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL 5089 //SDMA1_RLC5_IB_OFFSET 5090 #define SDMA1_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 5091 #define SDMA1_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 5092 //SDMA1_RLC5_IB_BASE_LO 5093 #define SDMA1_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 5094 #define SDMA1_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 5095 //SDMA1_RLC5_IB_BASE_HI 5096 #define SDMA1_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 5097 #define SDMA1_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 5098 //SDMA1_RLC5_IB_SIZE 5099 #define SDMA1_RLC5_IB_SIZE__SIZE__SHIFT 0x0 5100 #define SDMA1_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL 5101 //SDMA1_RLC5_SKIP_CNTL 5102 #define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 5103 #define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 5104 //SDMA1_RLC5_CONTEXT_STATUS 5105 #define SDMA1_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 5106 #define SDMA1_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 5107 #define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 5108 #define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 5109 #define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 5110 #define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 5111 #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 5112 #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 5113 #define SDMA1_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 5114 #define SDMA1_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L 5115 #define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 5116 #define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 5117 #define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 5118 #define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 5119 #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 5120 #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 5121 //SDMA1_RLC5_DOORBELL 5122 #define SDMA1_RLC5_DOORBELL__ENABLE__SHIFT 0x1c 5123 #define SDMA1_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e 5124 #define SDMA1_RLC5_DOORBELL__ENABLE_MASK 0x10000000L 5125 #define SDMA1_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L 5126 //SDMA1_RLC5_STATUS 5127 #define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 5128 #define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 5129 #define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 5130 #define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 5131 //SDMA1_RLC5_DOORBELL_LOG 5132 #define SDMA1_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 5133 #define SDMA1_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 5134 #define SDMA1_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 5135 #define SDMA1_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 5136 //SDMA1_RLC5_WATERMARK 5137 #define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 5138 #define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 5139 #define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 5140 #define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 5141 //SDMA1_RLC5_DOORBELL_OFFSET 5142 #define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 5143 #define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 5144 //SDMA1_RLC5_CSA_ADDR_LO 5145 #define SDMA1_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 5146 #define SDMA1_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 5147 //SDMA1_RLC5_CSA_ADDR_HI 5148 #define SDMA1_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 5149 #define SDMA1_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 5150 //SDMA1_RLC5_IB_SUB_REMAIN 5151 #define SDMA1_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 5152 #define SDMA1_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 5153 //SDMA1_RLC5_PREEMPT 5154 #define SDMA1_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 5155 #define SDMA1_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L 5156 //SDMA1_RLC5_DUMMY_REG 5157 #define SDMA1_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 5158 #define SDMA1_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 5159 //SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI 5160 #define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 5161 #define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 5162 //SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO 5163 #define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 5164 #define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 5165 //SDMA1_RLC5_RB_AQL_CNTL 5166 #define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 5167 #define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 5168 #define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 5169 #define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 5170 #define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 5171 #define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 5172 //SDMA1_RLC5_MINOR_PTR_UPDATE 5173 #define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 5174 #define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 5175 //SDMA1_RLC5_MIDCMD_DATA0 5176 #define SDMA1_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 5177 #define SDMA1_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 5178 //SDMA1_RLC5_MIDCMD_DATA1 5179 #define SDMA1_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 5180 #define SDMA1_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 5181 //SDMA1_RLC5_MIDCMD_DATA2 5182 #define SDMA1_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 5183 #define SDMA1_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 5184 //SDMA1_RLC5_MIDCMD_DATA3 5185 #define SDMA1_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 5186 #define SDMA1_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 5187 //SDMA1_RLC5_MIDCMD_DATA4 5188 #define SDMA1_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 5189 #define SDMA1_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 5190 //SDMA1_RLC5_MIDCMD_DATA5 5191 #define SDMA1_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 5192 #define SDMA1_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 5193 //SDMA1_RLC5_MIDCMD_DATA6 5194 #define SDMA1_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 5195 #define SDMA1_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 5196 //SDMA1_RLC5_MIDCMD_DATA7 5197 #define SDMA1_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 5198 #define SDMA1_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 5199 //SDMA1_RLC5_MIDCMD_DATA8 5200 #define SDMA1_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 5201 #define SDMA1_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 5202 //SDMA1_RLC5_MIDCMD_DATA9 5203 #define SDMA1_RLC5_MIDCMD_DATA9__DATA9__SHIFT 0x0 5204 #define SDMA1_RLC5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 5205 //SDMA1_RLC5_MIDCMD_DATA10 5206 #define SDMA1_RLC5_MIDCMD_DATA10__DATA10__SHIFT 0x0 5207 #define SDMA1_RLC5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 5208 //SDMA1_RLC5_MIDCMD_CNTL 5209 #define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 5210 #define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 5211 #define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 5212 #define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 5213 #define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 5214 #define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 5215 #define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 5216 #define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 5217 //SDMA1_RLC6_RB_CNTL 5218 #define SDMA1_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 5219 #define SDMA1_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 5220 #define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 5221 #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 5222 #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 5223 #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 5224 #define SDMA1_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 5225 #define SDMA1_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 5226 #define SDMA1_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L 5227 #define SDMA1_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL 5228 #define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 5229 #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 5230 #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 5231 #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 5232 #define SDMA1_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L 5233 #define SDMA1_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L 5234 //SDMA1_RLC6_RB_BASE 5235 #define SDMA1_RLC6_RB_BASE__ADDR__SHIFT 0x0 5236 #define SDMA1_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL 5237 //SDMA1_RLC6_RB_BASE_HI 5238 #define SDMA1_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 5239 #define SDMA1_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 5240 //SDMA1_RLC6_RB_RPTR 5241 #define SDMA1_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 5242 #define SDMA1_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 5243 //SDMA1_RLC6_RB_RPTR_HI 5244 #define SDMA1_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 5245 #define SDMA1_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 5246 //SDMA1_RLC6_RB_WPTR 5247 #define SDMA1_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 5248 #define SDMA1_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 5249 //SDMA1_RLC6_RB_WPTR_HI 5250 #define SDMA1_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 5251 #define SDMA1_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 5252 //SDMA1_RLC6_RB_WPTR_POLL_CNTL 5253 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 5254 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 5255 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 5256 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 5257 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 5258 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 5259 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 5260 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 5261 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 5262 #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 5263 //SDMA1_RLC6_RB_RPTR_ADDR_HI 5264 #define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 5265 #define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 5266 //SDMA1_RLC6_RB_RPTR_ADDR_LO 5267 #define SDMA1_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 5268 #define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 5269 #define SDMA1_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 5270 #define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 5271 //SDMA1_RLC6_IB_CNTL 5272 #define SDMA1_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 5273 #define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 5274 #define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 5275 #define SDMA1_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 5276 #define SDMA1_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L 5277 #define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 5278 #define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 5279 #define SDMA1_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L 5280 //SDMA1_RLC6_IB_RPTR 5281 #define SDMA1_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 5282 #define SDMA1_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL 5283 //SDMA1_RLC6_IB_OFFSET 5284 #define SDMA1_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 5285 #define SDMA1_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 5286 //SDMA1_RLC6_IB_BASE_LO 5287 #define SDMA1_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 5288 #define SDMA1_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 5289 //SDMA1_RLC6_IB_BASE_HI 5290 #define SDMA1_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 5291 #define SDMA1_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 5292 //SDMA1_RLC6_IB_SIZE 5293 #define SDMA1_RLC6_IB_SIZE__SIZE__SHIFT 0x0 5294 #define SDMA1_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL 5295 //SDMA1_RLC6_SKIP_CNTL 5296 #define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 5297 #define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 5298 //SDMA1_RLC6_CONTEXT_STATUS 5299 #define SDMA1_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 5300 #define SDMA1_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 5301 #define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 5302 #define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 5303 #define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 5304 #define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 5305 #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 5306 #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 5307 #define SDMA1_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 5308 #define SDMA1_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L 5309 #define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 5310 #define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 5311 #define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 5312 #define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 5313 #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 5314 #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 5315 //SDMA1_RLC6_DOORBELL 5316 #define SDMA1_RLC6_DOORBELL__ENABLE__SHIFT 0x1c 5317 #define SDMA1_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e 5318 #define SDMA1_RLC6_DOORBELL__ENABLE_MASK 0x10000000L 5319 #define SDMA1_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L 5320 //SDMA1_RLC6_STATUS 5321 #define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 5322 #define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 5323 #define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 5324 #define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 5325 //SDMA1_RLC6_DOORBELL_LOG 5326 #define SDMA1_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 5327 #define SDMA1_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 5328 #define SDMA1_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 5329 #define SDMA1_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 5330 //SDMA1_RLC6_WATERMARK 5331 #define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 5332 #define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 5333 #define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 5334 #define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 5335 //SDMA1_RLC6_DOORBELL_OFFSET 5336 #define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 5337 #define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 5338 //SDMA1_RLC6_CSA_ADDR_LO 5339 #define SDMA1_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 5340 #define SDMA1_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 5341 //SDMA1_RLC6_CSA_ADDR_HI 5342 #define SDMA1_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 5343 #define SDMA1_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 5344 //SDMA1_RLC6_IB_SUB_REMAIN 5345 #define SDMA1_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 5346 #define SDMA1_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 5347 //SDMA1_RLC6_PREEMPT 5348 #define SDMA1_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 5349 #define SDMA1_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L 5350 //SDMA1_RLC6_DUMMY_REG 5351 #define SDMA1_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 5352 #define SDMA1_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 5353 //SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI 5354 #define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 5355 #define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 5356 //SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO 5357 #define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 5358 #define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 5359 //SDMA1_RLC6_RB_AQL_CNTL 5360 #define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 5361 #define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 5362 #define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 5363 #define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 5364 #define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 5365 #define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 5366 //SDMA1_RLC6_MINOR_PTR_UPDATE 5367 #define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 5368 #define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 5369 //SDMA1_RLC6_MIDCMD_DATA0 5370 #define SDMA1_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 5371 #define SDMA1_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 5372 //SDMA1_RLC6_MIDCMD_DATA1 5373 #define SDMA1_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 5374 #define SDMA1_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 5375 //SDMA1_RLC6_MIDCMD_DATA2 5376 #define SDMA1_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 5377 #define SDMA1_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 5378 //SDMA1_RLC6_MIDCMD_DATA3 5379 #define SDMA1_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 5380 #define SDMA1_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 5381 //SDMA1_RLC6_MIDCMD_DATA4 5382 #define SDMA1_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 5383 #define SDMA1_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 5384 //SDMA1_RLC6_MIDCMD_DATA5 5385 #define SDMA1_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 5386 #define SDMA1_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 5387 //SDMA1_RLC6_MIDCMD_DATA6 5388 #define SDMA1_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 5389 #define SDMA1_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 5390 //SDMA1_RLC6_MIDCMD_DATA7 5391 #define SDMA1_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 5392 #define SDMA1_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 5393 //SDMA1_RLC6_MIDCMD_DATA8 5394 #define SDMA1_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 5395 #define SDMA1_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 5396 //SDMA1_RLC6_MIDCMD_DATA9 5397 #define SDMA1_RLC6_MIDCMD_DATA9__DATA9__SHIFT 0x0 5398 #define SDMA1_RLC6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 5399 //SDMA1_RLC6_MIDCMD_DATA10 5400 #define SDMA1_RLC6_MIDCMD_DATA10__DATA10__SHIFT 0x0 5401 #define SDMA1_RLC6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 5402 //SDMA1_RLC6_MIDCMD_CNTL 5403 #define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 5404 #define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 5405 #define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 5406 #define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 5407 #define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 5408 #define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 5409 #define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 5410 #define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 5411 //SDMA1_RLC7_RB_CNTL 5412 #define SDMA1_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 5413 #define SDMA1_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 5414 #define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 5415 #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 5416 #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 5417 #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 5418 #define SDMA1_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 5419 #define SDMA1_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 5420 #define SDMA1_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L 5421 #define SDMA1_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL 5422 #define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 5423 #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 5424 #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 5425 #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 5426 #define SDMA1_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L 5427 #define SDMA1_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L 5428 //SDMA1_RLC7_RB_BASE 5429 #define SDMA1_RLC7_RB_BASE__ADDR__SHIFT 0x0 5430 #define SDMA1_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL 5431 //SDMA1_RLC7_RB_BASE_HI 5432 #define SDMA1_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 5433 #define SDMA1_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 5434 //SDMA1_RLC7_RB_RPTR 5435 #define SDMA1_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 5436 #define SDMA1_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 5437 //SDMA1_RLC7_RB_RPTR_HI 5438 #define SDMA1_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 5439 #define SDMA1_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 5440 //SDMA1_RLC7_RB_WPTR 5441 #define SDMA1_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 5442 #define SDMA1_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 5443 //SDMA1_RLC7_RB_WPTR_HI 5444 #define SDMA1_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 5445 #define SDMA1_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 5446 //SDMA1_RLC7_RB_WPTR_POLL_CNTL 5447 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 5448 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 5449 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 5450 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 5451 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 5452 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 5453 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 5454 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 5455 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 5456 #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 5457 //SDMA1_RLC7_RB_RPTR_ADDR_HI 5458 #define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 5459 #define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 5460 //SDMA1_RLC7_RB_RPTR_ADDR_LO 5461 #define SDMA1_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 5462 #define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 5463 #define SDMA1_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 5464 #define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 5465 //SDMA1_RLC7_IB_CNTL 5466 #define SDMA1_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 5467 #define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 5468 #define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 5469 #define SDMA1_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 5470 #define SDMA1_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L 5471 #define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 5472 #define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 5473 #define SDMA1_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L 5474 //SDMA1_RLC7_IB_RPTR 5475 #define SDMA1_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 5476 #define SDMA1_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL 5477 //SDMA1_RLC7_IB_OFFSET 5478 #define SDMA1_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 5479 #define SDMA1_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 5480 //SDMA1_RLC7_IB_BASE_LO 5481 #define SDMA1_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 5482 #define SDMA1_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 5483 //SDMA1_RLC7_IB_BASE_HI 5484 #define SDMA1_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 5485 #define SDMA1_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 5486 //SDMA1_RLC7_IB_SIZE 5487 #define SDMA1_RLC7_IB_SIZE__SIZE__SHIFT 0x0 5488 #define SDMA1_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL 5489 //SDMA1_RLC7_SKIP_CNTL 5490 #define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 5491 #define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 5492 //SDMA1_RLC7_CONTEXT_STATUS 5493 #define SDMA1_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 5494 #define SDMA1_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 5495 #define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 5496 #define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 5497 #define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 5498 #define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 5499 #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 5500 #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 5501 #define SDMA1_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 5502 #define SDMA1_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L 5503 #define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 5504 #define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 5505 #define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 5506 #define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 5507 #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 5508 #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 5509 //SDMA1_RLC7_DOORBELL 5510 #define SDMA1_RLC7_DOORBELL__ENABLE__SHIFT 0x1c 5511 #define SDMA1_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e 5512 #define SDMA1_RLC7_DOORBELL__ENABLE_MASK 0x10000000L 5513 #define SDMA1_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L 5514 //SDMA1_RLC7_STATUS 5515 #define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 5516 #define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 5517 #define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 5518 #define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 5519 //SDMA1_RLC7_DOORBELL_LOG 5520 #define SDMA1_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 5521 #define SDMA1_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 5522 #define SDMA1_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 5523 #define SDMA1_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 5524 //SDMA1_RLC7_WATERMARK 5525 #define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 5526 #define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 5527 #define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 5528 #define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 5529 //SDMA1_RLC7_DOORBELL_OFFSET 5530 #define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 5531 #define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 5532 //SDMA1_RLC7_CSA_ADDR_LO 5533 #define SDMA1_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 5534 #define SDMA1_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 5535 //SDMA1_RLC7_CSA_ADDR_HI 5536 #define SDMA1_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 5537 #define SDMA1_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 5538 //SDMA1_RLC7_IB_SUB_REMAIN 5539 #define SDMA1_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 5540 #define SDMA1_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 5541 //SDMA1_RLC7_PREEMPT 5542 #define SDMA1_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 5543 #define SDMA1_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L 5544 //SDMA1_RLC7_DUMMY_REG 5545 #define SDMA1_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 5546 #define SDMA1_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 5547 //SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI 5548 #define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 5549 #define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 5550 //SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO 5551 #define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 5552 #define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 5553 //SDMA1_RLC7_RB_AQL_CNTL 5554 #define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 5555 #define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 5556 #define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 5557 #define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 5558 #define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 5559 #define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 5560 //SDMA1_RLC7_MINOR_PTR_UPDATE 5561 #define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 5562 #define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 5563 //SDMA1_RLC7_MIDCMD_DATA0 5564 #define SDMA1_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 5565 #define SDMA1_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 5566 //SDMA1_RLC7_MIDCMD_DATA1 5567 #define SDMA1_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 5568 #define SDMA1_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 5569 //SDMA1_RLC7_MIDCMD_DATA2 5570 #define SDMA1_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 5571 #define SDMA1_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 5572 //SDMA1_RLC7_MIDCMD_DATA3 5573 #define SDMA1_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 5574 #define SDMA1_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 5575 //SDMA1_RLC7_MIDCMD_DATA4 5576 #define SDMA1_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 5577 #define SDMA1_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 5578 //SDMA1_RLC7_MIDCMD_DATA5 5579 #define SDMA1_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 5580 #define SDMA1_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 5581 //SDMA1_RLC7_MIDCMD_DATA6 5582 #define SDMA1_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 5583 #define SDMA1_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 5584 //SDMA1_RLC7_MIDCMD_DATA7 5585 #define SDMA1_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 5586 #define SDMA1_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 5587 //SDMA1_RLC7_MIDCMD_DATA8 5588 #define SDMA1_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 5589 #define SDMA1_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 5590 //SDMA1_RLC7_MIDCMD_DATA9 5591 #define SDMA1_RLC7_MIDCMD_DATA9__DATA9__SHIFT 0x0 5592 #define SDMA1_RLC7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 5593 //SDMA1_RLC7_MIDCMD_DATA10 5594 #define SDMA1_RLC7_MIDCMD_DATA10__DATA10__SHIFT 0x0 5595 #define SDMA1_RLC7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 5596 //SDMA1_RLC7_MIDCMD_CNTL 5597 #define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 5598 #define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 5599 #define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 5600 #define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 5601 #define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 5602 #define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 5603 #define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 5604 #define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 5605 5606 5607 // addressBlock: sdma0_sdma2dec 5608 //SDMA2_UCODE_ADDR 5609 #define SDMA2_UCODE_ADDR__VALUE__SHIFT 0x0 5610 #define SDMA2_UCODE_ADDR__VALUE_MASK 0x00003FFFL 5611 //SDMA2_UCODE_DATA 5612 #define SDMA2_UCODE_DATA__VALUE__SHIFT 0x0 5613 #define SDMA2_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 5614 //SDMA2_VF_ENABLE 5615 #define SDMA2_VF_ENABLE__VF_ENABLE__SHIFT 0x0 5616 #define SDMA2_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 5617 #define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_ADDR__SHIFT 0x0 5618 #define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_DATA__SHIFT 0x1 5619 #define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_ADDR_MASK 0x00000001L 5620 #define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_DATA_MASK 0x00000002L 5621 //SDMA2_CONTEXT_GROUP_BOUNDARY 5622 #define SDMA2_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 5623 #define SDMA2_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 5624 //SDMA2_POWER_CNTL 5625 #define SDMA2_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 5626 #define SDMA2_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 5627 #define SDMA2_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 5628 #define SDMA2_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 5629 #define SDMA2_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 5630 #define SDMA2_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 5631 #define SDMA2_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 5632 #define SDMA2_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 5633 #define SDMA2_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 5634 #define SDMA2_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a 5635 #define SDMA2_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L 5636 #define SDMA2_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L 5637 #define SDMA2_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L 5638 #define SDMA2_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 5639 #define SDMA2_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 5640 #define SDMA2_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 5641 #define SDMA2_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 5642 #define SDMA2_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 5643 #define SDMA2_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 5644 #define SDMA2_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 5645 //SDMA2_CLK_CTRL 5646 #define SDMA2_CLK_CTRL__ON_DELAY__SHIFT 0x0 5647 #define SDMA2_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 5648 #define SDMA2_CLK_CTRL__RESERVED__SHIFT 0xc 5649 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 5650 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 5651 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 5652 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 5653 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 5654 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 5655 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 5656 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 5657 #define SDMA2_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 5658 #define SDMA2_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 5659 #define SDMA2_CLK_CTRL__RESERVED_MASK 0x00FFF000L 5660 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 5661 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 5662 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 5663 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 5664 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 5665 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 5666 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 5667 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 5668 //SDMA2_CNTL 5669 #define SDMA2_CNTL__TRAP_ENABLE__SHIFT 0x0 5670 #define SDMA2_CNTL__UTC_L1_ENABLE__SHIFT 0x1 5671 #define SDMA2_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 5672 #define SDMA2_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 5673 #define SDMA2_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 5674 #define SDMA2_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 5675 #define SDMA2_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x6 5676 #define SDMA2_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 5677 #define SDMA2_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 5678 #define SDMA2_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 5679 #define SDMA2_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 5680 #define SDMA2_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 5681 #define SDMA2_CNTL__TRAP_ENABLE_MASK 0x00000001L 5682 #define SDMA2_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 5683 #define SDMA2_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 5684 #define SDMA2_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 5685 #define SDMA2_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 5686 #define SDMA2_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 5687 #define SDMA2_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000040L 5688 #define SDMA2_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 5689 #define SDMA2_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 5690 #define SDMA2_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 5691 #define SDMA2_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 5692 #define SDMA2_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 5693 //SDMA2_CHICKEN_BITS 5694 #define SDMA2_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 5695 #define SDMA2_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 5696 #define SDMA2_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 5697 #define SDMA2_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 5698 #define SDMA2_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 5699 #define SDMA2_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 5700 #define SDMA2_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 5701 #define SDMA2_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 5702 #define SDMA2_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 5703 #define SDMA2_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 5704 #define SDMA2_CHICKEN_BITS__SRAM_FGCG_ENABLE__SHIFT 0x1a 5705 #define SDMA2_CHICKEN_BITS__RESERVED__SHIFT 0x1b 5706 #define SDMA2_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 5707 #define SDMA2_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 5708 #define SDMA2_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 5709 #define SDMA2_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 5710 #define SDMA2_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 5711 #define SDMA2_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 5712 #define SDMA2_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 5713 #define SDMA2_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 5714 #define SDMA2_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 5715 #define SDMA2_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 5716 #define SDMA2_CHICKEN_BITS__SRAM_FGCG_ENABLE_MASK 0x04000000L 5717 #define SDMA2_CHICKEN_BITS__RESERVED_MASK 0xF8000000L 5718 //SDMA2_GB_ADDR_CONFIG 5719 #define SDMA2_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 5720 #define SDMA2_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 5721 #define SDMA2_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 5722 #define SDMA2_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 5723 #define SDMA2_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 5724 #define SDMA2_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 5725 #define SDMA2_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 5726 #define SDMA2_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 5727 #define SDMA2_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 5728 #define SDMA2_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 5729 //SDMA2_GB_ADDR_CONFIG_READ 5730 #define SDMA2_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 5731 #define SDMA2_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 5732 #define SDMA2_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 5733 #define SDMA2_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 5734 #define SDMA2_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 5735 #define SDMA2_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 5736 #define SDMA2_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 5737 #define SDMA2_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 5738 #define SDMA2_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 5739 #define SDMA2_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 5740 //SDMA2_RB_RPTR_FETCH_HI 5741 #define SDMA2_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 5742 #define SDMA2_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 5743 //SDMA2_SEM_WAIT_FAIL_TIMER_CNTL 5744 #define SDMA2_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 5745 #define SDMA2_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 5746 //SDMA2_RB_RPTR_FETCH 5747 #define SDMA2_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 5748 #define SDMA2_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 5749 //SDMA2_IB_OFFSET_FETCH 5750 #define SDMA2_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 5751 #define SDMA2_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 5752 //SDMA2_PROGRAM 5753 #define SDMA2_PROGRAM__STREAM__SHIFT 0x0 5754 #define SDMA2_PROGRAM__STREAM_MASK 0xFFFFFFFFL 5755 //SDMA2_STATUS_REG 5756 #define SDMA2_STATUS_REG__IDLE__SHIFT 0x0 5757 #define SDMA2_STATUS_REG__REG_IDLE__SHIFT 0x1 5758 #define SDMA2_STATUS_REG__RB_EMPTY__SHIFT 0x2 5759 #define SDMA2_STATUS_REG__RB_FULL__SHIFT 0x3 5760 #define SDMA2_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 5761 #define SDMA2_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 5762 #define SDMA2_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 5763 #define SDMA2_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 5764 #define SDMA2_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 5765 #define SDMA2_STATUS_REG__INSIDE_IB__SHIFT 0x9 5766 #define SDMA2_STATUS_REG__EX_IDLE__SHIFT 0xa 5767 #define SDMA2_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 5768 #define SDMA2_STATUS_REG__PACKET_READY__SHIFT 0xc 5769 #define SDMA2_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 5770 #define SDMA2_STATUS_REG__SRBM_IDLE__SHIFT 0xe 5771 #define SDMA2_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 5772 #define SDMA2_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 5773 #define SDMA2_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 5774 #define SDMA2_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 5775 #define SDMA2_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 5776 #define SDMA2_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 5777 #define SDMA2_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 5778 #define SDMA2_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 5779 #define SDMA2_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 5780 #define SDMA2_STATUS_REG__SEM_IDLE__SHIFT 0x1a 5781 #define SDMA2_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 5782 #define SDMA2_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 5783 #define SDMA2_STATUS_REG__INT_IDLE__SHIFT 0x1e 5784 #define SDMA2_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 5785 #define SDMA2_STATUS_REG__IDLE_MASK 0x00000001L 5786 #define SDMA2_STATUS_REG__REG_IDLE_MASK 0x00000002L 5787 #define SDMA2_STATUS_REG__RB_EMPTY_MASK 0x00000004L 5788 #define SDMA2_STATUS_REG__RB_FULL_MASK 0x00000008L 5789 #define SDMA2_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 5790 #define SDMA2_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 5791 #define SDMA2_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 5792 #define SDMA2_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 5793 #define SDMA2_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 5794 #define SDMA2_STATUS_REG__INSIDE_IB_MASK 0x00000200L 5795 #define SDMA2_STATUS_REG__EX_IDLE_MASK 0x00000400L 5796 #define SDMA2_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 5797 #define SDMA2_STATUS_REG__PACKET_READY_MASK 0x00001000L 5798 #define SDMA2_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 5799 #define SDMA2_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 5800 #define SDMA2_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 5801 #define SDMA2_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 5802 #define SDMA2_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 5803 #define SDMA2_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 5804 #define SDMA2_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 5805 #define SDMA2_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 5806 #define SDMA2_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 5807 #define SDMA2_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 5808 #define SDMA2_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 5809 #define SDMA2_STATUS_REG__SEM_IDLE_MASK 0x04000000L 5810 #define SDMA2_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 5811 #define SDMA2_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 5812 #define SDMA2_STATUS_REG__INT_IDLE_MASK 0x40000000L 5813 #define SDMA2_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 5814 //SDMA2_STATUS1_REG 5815 #define SDMA2_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 5816 #define SDMA2_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 5817 #define SDMA2_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 5818 #define SDMA2_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 5819 #define SDMA2_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 5820 #define SDMA2_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 5821 #define SDMA2_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 5822 #define SDMA2_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 5823 #define SDMA2_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 5824 #define SDMA2_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 5825 #define SDMA2_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 5826 #define SDMA2_STATUS1_REG__EX_START__SHIFT 0xf 5827 #define SDMA2_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 5828 #define SDMA2_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 5829 #define SDMA2_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 5830 #define SDMA2_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 5831 #define SDMA2_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 5832 #define SDMA2_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 5833 #define SDMA2_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 5834 #define SDMA2_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 5835 #define SDMA2_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 5836 #define SDMA2_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 5837 #define SDMA2_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 5838 #define SDMA2_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 5839 #define SDMA2_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 5840 #define SDMA2_STATUS1_REG__EX_START_MASK 0x00008000L 5841 #define SDMA2_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 5842 #define SDMA2_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 5843 //SDMA2_RD_BURST_CNTL 5844 #define SDMA2_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 5845 #define SDMA2_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 5846 #define SDMA2_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 5847 #define SDMA2_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL 5848 //SDMA2_HBM_PAGE_CONFIG 5849 #define SDMA2_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 5850 #define SDMA2_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L 5851 //SDMA2_UCODE_CHECKSUM 5852 #define SDMA2_UCODE_CHECKSUM__DATA__SHIFT 0x0 5853 #define SDMA2_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 5854 //SDMA2_F32_CNTL 5855 #define SDMA2_F32_CNTL__HALT__SHIFT 0x0 5856 #define SDMA2_F32_CNTL__STEP__SHIFT 0x1 5857 #define SDMA2_F32_CNTL__RESET__SHIFT 0x8 5858 #define SDMA2_F32_CNTL__HALT_MASK 0x00000001L 5859 #define SDMA2_F32_CNTL__STEP_MASK 0x00000002L 5860 #define SDMA2_F32_CNTL__RESET_MASK 0x00000100L 5861 //SDMA2_FREEZE 5862 #define SDMA2_FREEZE__PREEMPT__SHIFT 0x0 5863 #define SDMA2_FREEZE__FREEZE__SHIFT 0x4 5864 #define SDMA2_FREEZE__FROZEN__SHIFT 0x5 5865 #define SDMA2_FREEZE__F32_FREEZE__SHIFT 0x6 5866 #define SDMA2_FREEZE__PREEMPT_MASK 0x00000001L 5867 #define SDMA2_FREEZE__FREEZE_MASK 0x00000010L 5868 #define SDMA2_FREEZE__FROZEN_MASK 0x00000020L 5869 #define SDMA2_FREEZE__F32_FREEZE_MASK 0x00000040L 5870 //SDMA2_PHASE0_QUANTUM 5871 #define SDMA2_PHASE0_QUANTUM__UNIT__SHIFT 0x0 5872 #define SDMA2_PHASE0_QUANTUM__VALUE__SHIFT 0x8 5873 #define SDMA2_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 5874 #define SDMA2_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 5875 #define SDMA2_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 5876 #define SDMA2_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 5877 //SDMA2_PHASE1_QUANTUM 5878 #define SDMA2_PHASE1_QUANTUM__UNIT__SHIFT 0x0 5879 #define SDMA2_PHASE1_QUANTUM__VALUE__SHIFT 0x8 5880 #define SDMA2_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 5881 #define SDMA2_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 5882 #define SDMA2_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 5883 #define SDMA2_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 5884 //CC_SDMA2_EDC_CONFIG 5885 #define CC_SDMA2_EDC_CONFIG__DIS_EDC__SHIFT 0x1 5886 #define CC_SDMA2_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 5887 //SDMA2_BA_THRESHOLD 5888 #define SDMA2_BA_THRESHOLD__READ_THRES__SHIFT 0x0 5889 #define SDMA2_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 5890 #define SDMA2_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 5891 #define SDMA2_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 5892 //SDMA2_ID 5893 #define SDMA2_ID__DEVICE_ID__SHIFT 0x0 5894 #define SDMA2_ID__DEVICE_ID_MASK 0x000000FFL 5895 //SDMA2_VERSION 5896 #define SDMA2_VERSION__MINVER__SHIFT 0x0 5897 #define SDMA2_VERSION__MAJVER__SHIFT 0x8 5898 #define SDMA2_VERSION__REV__SHIFT 0x10 5899 #define SDMA2_VERSION__MINVER_MASK 0x0000007FL 5900 #define SDMA2_VERSION__MAJVER_MASK 0x00007F00L 5901 #define SDMA2_VERSION__REV_MASK 0x003F0000L 5902 //SDMA2_EDC_COUNTER 5903 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x0 5904 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x2 5905 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x4 5906 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0x6 5907 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0x8 5908 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa 5909 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xc 5910 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 5911 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0x10 5912 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x12 5913 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x14 5914 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x16 5915 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x18 5916 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x1a 5917 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x1c 5918 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x1e 5919 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000003L 5920 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x0000000CL 5921 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000030L 5922 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x000000C0L 5923 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000300L 5924 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00000C00L 5925 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00003000L 5926 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x0000C000L 5927 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00030000L 5928 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x000C0000L 5929 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00300000L 5930 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00C00000L 5931 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x03000000L 5932 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x0C000000L 5933 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x30000000L 5934 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0xC0000000L 5935 //SDMA2_EDC_COUNTER2 5936 #define SDMA2_EDC_COUNTER2__SDMA_UCODE_BUF_SED__SHIFT 0x0 5937 #define SDMA2_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 5938 #define SDMA2_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED__SHIFT 0x4 5939 #define SDMA2_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x6 5940 #define SDMA2_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x8 5941 #define SDMA2_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED__SHIFT 0xa 5942 #define SDMA2_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED__SHIFT 0xc 5943 #define SDMA2_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED__SHIFT 0xe 5944 #define SDMA2_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 5945 #define SDMA2_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED__SHIFT 0x12 5946 #define SDMA2_EDC_COUNTER2__SDMA_UCODE_BUF_SED_MASK 0x00000003L 5947 #define SDMA2_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED_MASK 0x0000000CL 5948 #define SDMA2_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED_MASK 0x00000030L 5949 #define SDMA2_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED_MASK 0x000000C0L 5950 #define SDMA2_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000300L 5951 #define SDMA2_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED_MASK 0x00000C00L 5952 #define SDMA2_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED_MASK 0x00003000L 5953 #define SDMA2_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED_MASK 0x0000C000L 5954 #define SDMA2_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00030000L 5955 #define SDMA2_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED_MASK 0x000C0000L 5956 //SDMA2_STATUS2_REG 5957 #define SDMA2_STATUS2_REG__ID__SHIFT 0x0 5958 #define SDMA2_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 5959 #define SDMA2_STATUS2_REG__CMD_OP__SHIFT 0x10 5960 #define SDMA2_STATUS2_REG__ID_MASK 0x00000007L 5961 #define SDMA2_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L 5962 #define SDMA2_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 5963 //SDMA2_ATOMIC_CNTL 5964 #define SDMA2_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 5965 #define SDMA2_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 5966 #define SDMA2_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 5967 #define SDMA2_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 5968 //SDMA2_ATOMIC_PREOP_LO 5969 #define SDMA2_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 5970 #define SDMA2_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 5971 //SDMA2_ATOMIC_PREOP_HI 5972 #define SDMA2_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 5973 #define SDMA2_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 5974 //SDMA2_UTCL1_CNTL 5975 #define SDMA2_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 5976 #define SDMA2_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 5977 #define SDMA2_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 5978 #define SDMA2_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 5979 #define SDMA2_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 5980 #define SDMA2_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 5981 #define SDMA2_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 5982 #define SDMA2_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 5983 #define SDMA2_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 5984 #define SDMA2_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 5985 #define SDMA2_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 5986 #define SDMA2_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 5987 //SDMA2_UTCL1_WATERMK 5988 #define SDMA2_UTCL1_WATERMK__REQ_WATERMK__SHIFT 0x0 5989 #define SDMA2_UTCL1_WATERMK__REQ_DEPTH__SHIFT 0x3 5990 #define SDMA2_UTCL1_WATERMK__PAGE_WATERMK__SHIFT 0x5 5991 #define SDMA2_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x8 5992 #define SDMA2_UTCL1_WATERMK__RESERVED__SHIFT 0x10 5993 #define SDMA2_UTCL1_WATERMK__REQ_WATERMK_MASK 0x00000007L 5994 #define SDMA2_UTCL1_WATERMK__REQ_DEPTH_MASK 0x00000018L 5995 #define SDMA2_UTCL1_WATERMK__PAGE_WATERMK_MASK 0x000000E0L 5996 #define SDMA2_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x0000FF00L 5997 #define SDMA2_UTCL1_WATERMK__RESERVED_MASK 0xFFFF0000L 5998 //SDMA2_UTCL1_RD_STATUS 5999 #define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 6000 #define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 6001 #define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 6002 #define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 6003 #define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 6004 #define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 6005 #define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 6006 #define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 6007 #define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 6008 #define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 6009 #define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 6010 #define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 6011 #define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 6012 #define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 6013 #define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 6014 #define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 6015 #define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 6016 #define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 6017 #define SDMA2_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 6018 #define SDMA2_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 6019 #define SDMA2_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 6020 #define SDMA2_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 6021 #define SDMA2_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 6022 #define SDMA2_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 6023 #define SDMA2_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 6024 #define SDMA2_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 6025 #define SDMA2_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 6026 #define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 6027 #define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 6028 #define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 6029 #define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 6030 #define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 6031 #define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 6032 #define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 6033 #define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 6034 #define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 6035 #define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 6036 #define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 6037 #define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 6038 #define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 6039 #define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 6040 #define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 6041 #define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 6042 #define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 6043 #define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 6044 #define SDMA2_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 6045 #define SDMA2_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 6046 #define SDMA2_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 6047 #define SDMA2_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 6048 #define SDMA2_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 6049 #define SDMA2_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 6050 #define SDMA2_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 6051 #define SDMA2_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 6052 #define SDMA2_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 6053 //SDMA2_UTCL1_WR_STATUS 6054 #define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 6055 #define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 6056 #define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 6057 #define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 6058 #define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 6059 #define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 6060 #define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 6061 #define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 6062 #define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 6063 #define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 6064 #define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 6065 #define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 6066 #define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 6067 #define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 6068 #define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 6069 #define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 6070 #define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 6071 #define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 6072 #define SDMA2_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 6073 #define SDMA2_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 6074 #define SDMA2_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 6075 #define SDMA2_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 6076 #define SDMA2_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 6077 #define SDMA2_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 6078 #define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 6079 #define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 6080 #define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 6081 #define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 6082 #define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 6083 #define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 6084 #define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 6085 #define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 6086 #define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 6087 #define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 6088 #define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 6089 #define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 6090 #define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 6091 #define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 6092 #define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 6093 #define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 6094 #define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 6095 #define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 6096 #define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 6097 #define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 6098 #define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 6099 #define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 6100 #define SDMA2_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 6101 #define SDMA2_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 6102 #define SDMA2_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 6103 #define SDMA2_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 6104 #define SDMA2_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 6105 #define SDMA2_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 6106 #define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 6107 #define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 6108 #define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 6109 #define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 6110 //SDMA2_UTCL1_INV0 6111 #define SDMA2_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 6112 #define SDMA2_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 6113 #define SDMA2_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 6114 #define SDMA2_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 6115 #define SDMA2_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 6116 #define SDMA2_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 6117 #define SDMA2_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 6118 #define SDMA2_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 6119 #define SDMA2_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 6120 #define SDMA2_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 6121 #define SDMA2_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 6122 #define SDMA2_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 6123 #define SDMA2_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 6124 #define SDMA2_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 6125 #define SDMA2_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 6126 #define SDMA2_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 6127 #define SDMA2_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 6128 #define SDMA2_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 6129 #define SDMA2_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 6130 #define SDMA2_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 6131 #define SDMA2_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 6132 #define SDMA2_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 6133 #define SDMA2_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 6134 #define SDMA2_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 6135 #define SDMA2_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 6136 #define SDMA2_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 6137 #define SDMA2_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 6138 #define SDMA2_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 6139 //SDMA2_UTCL1_INV1 6140 #define SDMA2_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 6141 #define SDMA2_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 6142 //SDMA2_UTCL1_INV2 6143 #define SDMA2_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 6144 #define SDMA2_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 6145 //SDMA2_UTCL1_RD_XNACK0 6146 #define SDMA2_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 6147 #define SDMA2_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 6148 //SDMA2_UTCL1_RD_XNACK1 6149 #define SDMA2_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 6150 #define SDMA2_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 6151 #define SDMA2_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 6152 #define SDMA2_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 6153 #define SDMA2_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 6154 #define SDMA2_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 6155 #define SDMA2_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 6156 #define SDMA2_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 6157 //SDMA2_UTCL1_WR_XNACK0 6158 #define SDMA2_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 6159 #define SDMA2_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 6160 //SDMA2_UTCL1_WR_XNACK1 6161 #define SDMA2_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 6162 #define SDMA2_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 6163 #define SDMA2_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 6164 #define SDMA2_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 6165 #define SDMA2_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 6166 #define SDMA2_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 6167 #define SDMA2_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 6168 #define SDMA2_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 6169 //SDMA2_UTCL1_TIMEOUT 6170 #define SDMA2_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 6171 #define SDMA2_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 6172 #define SDMA2_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 6173 #define SDMA2_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 6174 //SDMA2_UTCL1_PAGE 6175 #define SDMA2_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 6176 #define SDMA2_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 6177 #define SDMA2_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 6178 #define SDMA2_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 6179 #define SDMA2_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 6180 #define SDMA2_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 6181 #define SDMA2_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 6182 #define SDMA2_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 6183 //SDMA2_POWER_CNTL_IDLE 6184 #define SDMA2_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 6185 #define SDMA2_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 6186 #define SDMA2_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 6187 #define SDMA2_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 6188 #define SDMA2_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 6189 #define SDMA2_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 6190 //SDMA2_RELAX_ORDERING_LUT 6191 #define SDMA2_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 6192 #define SDMA2_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 6193 #define SDMA2_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 6194 #define SDMA2_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 6195 #define SDMA2_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 6196 #define SDMA2_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 6197 #define SDMA2_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 6198 #define SDMA2_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 6199 #define SDMA2_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 6200 #define SDMA2_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 6201 #define SDMA2_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 6202 #define SDMA2_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 6203 #define SDMA2_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 6204 #define SDMA2_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 6205 #define SDMA2_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 6206 #define SDMA2_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 6207 #define SDMA2_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 6208 #define SDMA2_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 6209 #define SDMA2_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 6210 #define SDMA2_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 6211 #define SDMA2_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 6212 #define SDMA2_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 6213 #define SDMA2_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 6214 #define SDMA2_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 6215 #define SDMA2_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 6216 #define SDMA2_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 6217 #define SDMA2_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 6218 #define SDMA2_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 6219 #define SDMA2_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 6220 #define SDMA2_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 6221 #define SDMA2_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 6222 #define SDMA2_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 6223 #define SDMA2_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 6224 #define SDMA2_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 6225 #define SDMA2_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 6226 #define SDMA2_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 6227 #define SDMA2_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 6228 #define SDMA2_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 6229 //SDMA2_CHICKEN_BITS_2 6230 #define SDMA2_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 6231 #define SDMA2_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x4 6232 #define SDMA2_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 6233 #define SDMA2_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00000010L 6234 //SDMA2_STATUS3_REG 6235 #define SDMA2_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 6236 #define SDMA2_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 6237 #define SDMA2_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 6238 #define SDMA2_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 6239 #define SDMA2_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 6240 #define SDMA2_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 6241 #define SDMA2_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 6242 #define SDMA2_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 6243 #define SDMA2_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L 6244 #define SDMA2_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L 6245 //SDMA2_PHYSICAL_ADDR_LO 6246 #define SDMA2_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 6247 #define SDMA2_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 6248 #define SDMA2_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 6249 #define SDMA2_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 6250 #define SDMA2_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 6251 #define SDMA2_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 6252 #define SDMA2_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 6253 #define SDMA2_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 6254 //SDMA2_PHYSICAL_ADDR_HI 6255 #define SDMA2_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 6256 #define SDMA2_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 6257 //SDMA2_PHASE2_QUANTUM 6258 #define SDMA2_PHASE2_QUANTUM__UNIT__SHIFT 0x0 6259 #define SDMA2_PHASE2_QUANTUM__VALUE__SHIFT 0x8 6260 #define SDMA2_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 6261 #define SDMA2_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 6262 #define SDMA2_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 6263 #define SDMA2_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 6264 //SDMA2_ERROR_LOG 6265 #define SDMA2_ERROR_LOG__OVERRIDE__SHIFT 0x0 6266 #define SDMA2_ERROR_LOG__STATUS__SHIFT 0x10 6267 #define SDMA2_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 6268 #define SDMA2_ERROR_LOG__STATUS_MASK 0xFFFF0000L 6269 //SDMA2_PUB_DUMMY_REG0 6270 #define SDMA2_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 6271 #define SDMA2_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 6272 //SDMA2_PUB_DUMMY_REG1 6273 #define SDMA2_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 6274 #define SDMA2_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 6275 //SDMA2_PUB_DUMMY_REG2 6276 #define SDMA2_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 6277 #define SDMA2_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 6278 //SDMA2_PUB_DUMMY_REG3 6279 #define SDMA2_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 6280 #define SDMA2_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 6281 //SDMA2_F32_COUNTER 6282 #define SDMA2_F32_COUNTER__VALUE__SHIFT 0x0 6283 #define SDMA2_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 6284 //SDMA2_PERFCNT_PERFCOUNTER0_CFG 6285 #define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 6286 #define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 6287 #define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 6288 #define SDMA2_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 6289 #define SDMA2_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 6290 #define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 6291 #define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 6292 #define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 6293 #define SDMA2_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 6294 #define SDMA2_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 6295 //SDMA2_PERFCNT_PERFCOUNTER1_CFG 6296 #define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 6297 #define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 6298 #define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 6299 #define SDMA2_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 6300 #define SDMA2_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 6301 #define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 6302 #define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 6303 #define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 6304 #define SDMA2_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 6305 #define SDMA2_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 6306 //SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL 6307 #define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 6308 #define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 6309 #define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 6310 #define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 6311 #define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 6312 #define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 6313 #define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 6314 #define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 6315 #define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 6316 #define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 6317 #define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 6318 #define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 6319 //SDMA2_PERFCNT_MISC_CNTL 6320 #define SDMA2_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 6321 #define SDMA2_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL 6322 //SDMA2_PERFCNT_PERFCOUNTER_LO 6323 #define SDMA2_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 6324 #define SDMA2_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 6325 //SDMA2_PERFCNT_PERFCOUNTER_HI 6326 #define SDMA2_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 6327 #define SDMA2_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 6328 #define SDMA2_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 6329 #define SDMA2_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 6330 //SDMA2_CRD_CNTL 6331 #define SDMA2_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 6332 #define SDMA2_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 6333 #define SDMA2_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 6334 #define SDMA2_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 6335 //SDMA2_ULV_CNTL 6336 #define SDMA2_ULV_CNTL__HYSTERESIS__SHIFT 0x0 6337 #define SDMA2_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b 6338 #define SDMA2_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c 6339 #define SDMA2_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 6340 #define SDMA2_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 6341 #define SDMA2_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 6342 #define SDMA2_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 6343 #define SDMA2_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L 6344 #define SDMA2_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L 6345 #define SDMA2_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 6346 #define SDMA2_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 6347 #define SDMA2_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 6348 //SDMA2_EA_DBIT_ADDR_DATA 6349 #define SDMA2_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 6350 #define SDMA2_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 6351 //SDMA2_EA_DBIT_ADDR_INDEX 6352 #define SDMA2_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 6353 #define SDMA2_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 6354 //SDMA2_STATUS4_REG 6355 #define SDMA2_STATUS4_REG__IDLE__SHIFT 0x0 6356 #define SDMA2_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2 6357 #define SDMA2_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3 6358 #define SDMA2_STATUS4_REG__MMHUB_RD_OUTSTANDING__SHIFT 0x4 6359 #define SDMA2_STATUS4_REG__MMHUB_WR_OUTSTANDING__SHIFT 0x5 6360 #define SDMA2_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x6 6361 #define SDMA2_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x7 6362 #define SDMA2_STATUS4_REG__REG_POLLING__SHIFT 0x8 6363 #define SDMA2_STATUS4_REG__MEM_POLLING__SHIFT 0x9 6364 #define SDMA2_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xa 6365 #define SDMA2_STATUS4_REG__UTCL2_WR_XNACK__SHIFT 0xc 6366 #define SDMA2_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0xe 6367 #define SDMA2_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x12 6368 #define SDMA2_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x13 6369 #define SDMA2_STATUS4_REG__IDLE_MASK 0x00000001L 6370 #define SDMA2_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L 6371 #define SDMA2_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L 6372 #define SDMA2_STATUS4_REG__MMHUB_RD_OUTSTANDING_MASK 0x00000010L 6373 #define SDMA2_STATUS4_REG__MMHUB_WR_OUTSTANDING_MASK 0x00000020L 6374 #define SDMA2_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000040L 6375 #define SDMA2_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000080L 6376 #define SDMA2_STATUS4_REG__REG_POLLING_MASK 0x00000100L 6377 #define SDMA2_STATUS4_REG__MEM_POLLING_MASK 0x00000200L 6378 #define SDMA2_STATUS4_REG__UTCL2_RD_XNACK_MASK 0x00000C00L 6379 #define SDMA2_STATUS4_REG__UTCL2_WR_XNACK_MASK 0x00003000L 6380 #define SDMA2_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x0003C000L 6381 #define SDMA2_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00040000L 6382 #define SDMA2_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00080000L 6383 //SDMA2_SCRATCH_RAM_DATA 6384 #define SDMA2_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 6385 #define SDMA2_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL 6386 //SDMA2_SCRATCH_RAM_ADDR 6387 #define SDMA2_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 6388 #define SDMA2_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL 6389 //SDMA2_CE_CTRL 6390 #define SDMA2_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 6391 #define SDMA2_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 6392 #define SDMA2_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5 6393 #define SDMA2_CE_CTRL__RESERVED__SHIFT 0x8 6394 #define SDMA2_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L 6395 #define SDMA2_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L 6396 #define SDMA2_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L 6397 #define SDMA2_CE_CTRL__RESERVED_MASK 0xFFFFFF00L 6398 //SDMA2_RAS_STATUS 6399 #define SDMA2_RAS_STATUS__RB_FETCH_ECC__SHIFT 0x0 6400 #define SDMA2_RAS_STATUS__IB_FETCH_ECC__SHIFT 0x1 6401 #define SDMA2_RAS_STATUS__F32_DATA_ECC__SHIFT 0x2 6402 #define SDMA2_RAS_STATUS__SEM_WPTR_ATOMIC_ECC__SHIFT 0x3 6403 #define SDMA2_RAS_STATUS__COPY_DATA_ECC__SHIFT 0x4 6404 #define SDMA2_RAS_STATUS__SRAM_ECC__SHIFT 0x5 6405 #define SDMA2_RAS_STATUS__RB_FETCH_NACK_GEN_ERR__SHIFT 0x8 6406 #define SDMA2_RAS_STATUS__IB_FETCH_NACK_GEN_ERR__SHIFT 0x9 6407 #define SDMA2_RAS_STATUS__F32_DATA_NACK_GEN_ERR__SHIFT 0xa 6408 #define SDMA2_RAS_STATUS__COPY_DATA_NACK_GEN_ERR__SHIFT 0xb 6409 #define SDMA2_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR__SHIFT 0xc 6410 #define SDMA2_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR__SHIFT 0xd 6411 #define SDMA2_RAS_STATUS__RB_FETCH_ECC_MASK 0x00000001L 6412 #define SDMA2_RAS_STATUS__IB_FETCH_ECC_MASK 0x00000002L 6413 #define SDMA2_RAS_STATUS__F32_DATA_ECC_MASK 0x00000004L 6414 #define SDMA2_RAS_STATUS__SEM_WPTR_ATOMIC_ECC_MASK 0x00000008L 6415 #define SDMA2_RAS_STATUS__COPY_DATA_ECC_MASK 0x00000010L 6416 #define SDMA2_RAS_STATUS__SRAM_ECC_MASK 0x00000020L 6417 #define SDMA2_RAS_STATUS__RB_FETCH_NACK_GEN_ERR_MASK 0x00000100L 6418 #define SDMA2_RAS_STATUS__IB_FETCH_NACK_GEN_ERR_MASK 0x00000200L 6419 #define SDMA2_RAS_STATUS__F32_DATA_NACK_GEN_ERR_MASK 0x00000400L 6420 #define SDMA2_RAS_STATUS__COPY_DATA_NACK_GEN_ERR_MASK 0x00000800L 6421 #define SDMA2_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR_MASK 0x00001000L 6422 #define SDMA2_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR_MASK 0x00002000L 6423 //SDMA2_CLK_STATUS 6424 #define SDMA2_CLK_STATUS__DYN_CLK__SHIFT 0x0 6425 #define SDMA2_CLK_STATUS__PTR_CLK__SHIFT 0x1 6426 #define SDMA2_CLK_STATUS__REG_CLK__SHIFT 0x2 6427 #define SDMA2_CLK_STATUS__F32_CLK__SHIFT 0x3 6428 #define SDMA2_CLK_STATUS__DYN_CLK_MASK 0x00000001L 6429 #define SDMA2_CLK_STATUS__PTR_CLK_MASK 0x00000002L 6430 #define SDMA2_CLK_STATUS__REG_CLK_MASK 0x00000004L 6431 #define SDMA2_CLK_STATUS__F32_CLK_MASK 0x00000008L 6432 //SDMA2_GFX_RB_CNTL 6433 #define SDMA2_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 6434 #define SDMA2_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 6435 #define SDMA2_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 6436 #define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 6437 #define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 6438 #define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 6439 #define SDMA2_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 6440 #define SDMA2_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 6441 #define SDMA2_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 6442 #define SDMA2_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL 6443 #define SDMA2_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 6444 #define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 6445 #define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 6446 #define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 6447 #define SDMA2_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 6448 #define SDMA2_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 6449 //SDMA2_GFX_RB_BASE 6450 #define SDMA2_GFX_RB_BASE__ADDR__SHIFT 0x0 6451 #define SDMA2_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 6452 //SDMA2_GFX_RB_BASE_HI 6453 #define SDMA2_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 6454 #define SDMA2_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 6455 //SDMA2_GFX_RB_RPTR 6456 #define SDMA2_GFX_RB_RPTR__OFFSET__SHIFT 0x0 6457 #define SDMA2_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 6458 //SDMA2_GFX_RB_RPTR_HI 6459 #define SDMA2_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 6460 #define SDMA2_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 6461 //SDMA2_GFX_RB_WPTR 6462 #define SDMA2_GFX_RB_WPTR__OFFSET__SHIFT 0x0 6463 #define SDMA2_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 6464 //SDMA2_GFX_RB_WPTR_HI 6465 #define SDMA2_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 6466 #define SDMA2_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 6467 //SDMA2_GFX_RB_WPTR_POLL_CNTL 6468 #define SDMA2_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 6469 #define SDMA2_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 6470 #define SDMA2_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 6471 #define SDMA2_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 6472 #define SDMA2_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 6473 #define SDMA2_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 6474 #define SDMA2_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 6475 #define SDMA2_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 6476 #define SDMA2_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 6477 #define SDMA2_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 6478 //SDMA2_GFX_RB_RPTR_ADDR_HI 6479 #define SDMA2_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 6480 #define SDMA2_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 6481 //SDMA2_GFX_RB_RPTR_ADDR_LO 6482 #define SDMA2_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 6483 #define SDMA2_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 6484 #define SDMA2_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 6485 #define SDMA2_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 6486 //SDMA2_GFX_IB_CNTL 6487 #define SDMA2_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 6488 #define SDMA2_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 6489 #define SDMA2_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 6490 #define SDMA2_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 6491 #define SDMA2_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 6492 #define SDMA2_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 6493 #define SDMA2_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 6494 #define SDMA2_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 6495 //SDMA2_GFX_IB_RPTR 6496 #define SDMA2_GFX_IB_RPTR__OFFSET__SHIFT 0x2 6497 #define SDMA2_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 6498 //SDMA2_GFX_IB_OFFSET 6499 #define SDMA2_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 6500 #define SDMA2_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 6501 //SDMA2_GFX_IB_BASE_LO 6502 #define SDMA2_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 6503 #define SDMA2_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 6504 //SDMA2_GFX_IB_BASE_HI 6505 #define SDMA2_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 6506 #define SDMA2_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 6507 //SDMA2_GFX_IB_SIZE 6508 #define SDMA2_GFX_IB_SIZE__SIZE__SHIFT 0x0 6509 #define SDMA2_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 6510 //SDMA2_GFX_SKIP_CNTL 6511 #define SDMA2_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 6512 #define SDMA2_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 6513 //SDMA2_GFX_CONTEXT_STATUS 6514 #define SDMA2_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 6515 #define SDMA2_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 6516 #define SDMA2_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 6517 #define SDMA2_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 6518 #define SDMA2_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 6519 #define SDMA2_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 6520 #define SDMA2_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 6521 #define SDMA2_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 6522 #define SDMA2_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 6523 #define SDMA2_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 6524 #define SDMA2_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 6525 #define SDMA2_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 6526 #define SDMA2_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 6527 #define SDMA2_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 6528 #define SDMA2_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 6529 #define SDMA2_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 6530 //SDMA2_GFX_DOORBELL 6531 #define SDMA2_GFX_DOORBELL__ENABLE__SHIFT 0x1c 6532 #define SDMA2_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 6533 #define SDMA2_GFX_DOORBELL__ENABLE_MASK 0x10000000L 6534 #define SDMA2_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 6535 //SDMA2_GFX_CONTEXT_CNTL 6536 #define SDMA2_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 6537 #define SDMA2_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 6538 #define SDMA2_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 6539 #define SDMA2_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0x0F000000L 6540 //SDMA2_GFX_STATUS 6541 #define SDMA2_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 6542 #define SDMA2_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 6543 #define SDMA2_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 6544 #define SDMA2_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 6545 //SDMA2_GFX_DOORBELL_LOG 6546 #define SDMA2_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 6547 #define SDMA2_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 6548 #define SDMA2_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 6549 #define SDMA2_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 6550 //SDMA2_GFX_WATERMARK 6551 #define SDMA2_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 6552 #define SDMA2_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 6553 #define SDMA2_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 6554 #define SDMA2_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 6555 //SDMA2_GFX_DOORBELL_OFFSET 6556 #define SDMA2_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 6557 #define SDMA2_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 6558 //SDMA2_GFX_CSA_ADDR_LO 6559 #define SDMA2_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 6560 #define SDMA2_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 6561 //SDMA2_GFX_CSA_ADDR_HI 6562 #define SDMA2_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 6563 #define SDMA2_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 6564 //SDMA2_GFX_IB_SUB_REMAIN 6565 #define SDMA2_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 6566 #define SDMA2_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 6567 //SDMA2_GFX_PREEMPT 6568 #define SDMA2_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 6569 #define SDMA2_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 6570 //SDMA2_GFX_DUMMY_REG 6571 #define SDMA2_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 6572 #define SDMA2_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 6573 //SDMA2_GFX_RB_WPTR_POLL_ADDR_HI 6574 #define SDMA2_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 6575 #define SDMA2_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 6576 //SDMA2_GFX_RB_WPTR_POLL_ADDR_LO 6577 #define SDMA2_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 6578 #define SDMA2_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 6579 //SDMA2_GFX_RB_AQL_CNTL 6580 #define SDMA2_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 6581 #define SDMA2_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 6582 #define SDMA2_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 6583 #define SDMA2_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 6584 #define SDMA2_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 6585 #define SDMA2_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 6586 //SDMA2_GFX_MINOR_PTR_UPDATE 6587 #define SDMA2_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 6588 #define SDMA2_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 6589 //SDMA2_GFX_MIDCMD_DATA0 6590 #define SDMA2_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 6591 #define SDMA2_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 6592 //SDMA2_GFX_MIDCMD_DATA1 6593 #define SDMA2_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 6594 #define SDMA2_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 6595 //SDMA2_GFX_MIDCMD_DATA2 6596 #define SDMA2_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 6597 #define SDMA2_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 6598 //SDMA2_GFX_MIDCMD_DATA3 6599 #define SDMA2_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 6600 #define SDMA2_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 6601 //SDMA2_GFX_MIDCMD_DATA4 6602 #define SDMA2_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 6603 #define SDMA2_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 6604 //SDMA2_GFX_MIDCMD_DATA5 6605 #define SDMA2_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 6606 #define SDMA2_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 6607 //SDMA2_GFX_MIDCMD_DATA6 6608 #define SDMA2_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 6609 #define SDMA2_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 6610 //SDMA2_GFX_MIDCMD_DATA7 6611 #define SDMA2_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 6612 #define SDMA2_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 6613 //SDMA2_GFX_MIDCMD_DATA8 6614 #define SDMA2_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 6615 #define SDMA2_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 6616 //SDMA2_GFX_MIDCMD_DATA9 6617 #define SDMA2_GFX_MIDCMD_DATA9__DATA9__SHIFT 0x0 6618 #define SDMA2_GFX_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 6619 //SDMA2_GFX_MIDCMD_DATA10 6620 #define SDMA2_GFX_MIDCMD_DATA10__DATA10__SHIFT 0x0 6621 #define SDMA2_GFX_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 6622 //SDMA2_GFX_MIDCMD_CNTL 6623 #define SDMA2_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 6624 #define SDMA2_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 6625 #define SDMA2_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 6626 #define SDMA2_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 6627 #define SDMA2_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 6628 #define SDMA2_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 6629 #define SDMA2_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 6630 #define SDMA2_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 6631 //SDMA2_PAGE_RB_CNTL 6632 #define SDMA2_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 6633 #define SDMA2_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 6634 #define SDMA2_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 6635 #define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 6636 #define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 6637 #define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 6638 #define SDMA2_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 6639 #define SDMA2_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 6640 #define SDMA2_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 6641 #define SDMA2_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL 6642 #define SDMA2_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 6643 #define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 6644 #define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 6645 #define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 6646 #define SDMA2_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 6647 #define SDMA2_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 6648 //SDMA2_PAGE_RB_BASE 6649 #define SDMA2_PAGE_RB_BASE__ADDR__SHIFT 0x0 6650 #define SDMA2_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 6651 //SDMA2_PAGE_RB_BASE_HI 6652 #define SDMA2_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 6653 #define SDMA2_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 6654 //SDMA2_PAGE_RB_RPTR 6655 #define SDMA2_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 6656 #define SDMA2_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 6657 //SDMA2_PAGE_RB_RPTR_HI 6658 #define SDMA2_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 6659 #define SDMA2_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 6660 //SDMA2_PAGE_RB_WPTR 6661 #define SDMA2_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 6662 #define SDMA2_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 6663 //SDMA2_PAGE_RB_WPTR_HI 6664 #define SDMA2_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 6665 #define SDMA2_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 6666 //SDMA2_PAGE_RB_WPTR_POLL_CNTL 6667 #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 6668 #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 6669 #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 6670 #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 6671 #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 6672 #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 6673 #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 6674 #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 6675 #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 6676 #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 6677 //SDMA2_PAGE_RB_RPTR_ADDR_HI 6678 #define SDMA2_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 6679 #define SDMA2_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 6680 //SDMA2_PAGE_RB_RPTR_ADDR_LO 6681 #define SDMA2_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 6682 #define SDMA2_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 6683 #define SDMA2_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 6684 #define SDMA2_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 6685 //SDMA2_PAGE_IB_CNTL 6686 #define SDMA2_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 6687 #define SDMA2_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 6688 #define SDMA2_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 6689 #define SDMA2_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 6690 #define SDMA2_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 6691 #define SDMA2_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 6692 #define SDMA2_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 6693 #define SDMA2_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 6694 //SDMA2_PAGE_IB_RPTR 6695 #define SDMA2_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 6696 #define SDMA2_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 6697 //SDMA2_PAGE_IB_OFFSET 6698 #define SDMA2_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 6699 #define SDMA2_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 6700 //SDMA2_PAGE_IB_BASE_LO 6701 #define SDMA2_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 6702 #define SDMA2_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 6703 //SDMA2_PAGE_IB_BASE_HI 6704 #define SDMA2_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 6705 #define SDMA2_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 6706 //SDMA2_PAGE_IB_SIZE 6707 #define SDMA2_PAGE_IB_SIZE__SIZE__SHIFT 0x0 6708 #define SDMA2_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 6709 //SDMA2_PAGE_SKIP_CNTL 6710 #define SDMA2_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 6711 #define SDMA2_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 6712 //SDMA2_PAGE_CONTEXT_STATUS 6713 #define SDMA2_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 6714 #define SDMA2_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 6715 #define SDMA2_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 6716 #define SDMA2_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 6717 #define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 6718 #define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 6719 #define SDMA2_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 6720 #define SDMA2_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 6721 #define SDMA2_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 6722 #define SDMA2_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 6723 #define SDMA2_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 6724 #define SDMA2_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 6725 #define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 6726 #define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 6727 #define SDMA2_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 6728 #define SDMA2_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 6729 //SDMA2_PAGE_DOORBELL 6730 #define SDMA2_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 6731 #define SDMA2_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 6732 #define SDMA2_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 6733 #define SDMA2_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 6734 //SDMA2_PAGE_STATUS 6735 #define SDMA2_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 6736 #define SDMA2_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 6737 #define SDMA2_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 6738 #define SDMA2_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 6739 //SDMA2_PAGE_DOORBELL_LOG 6740 #define SDMA2_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 6741 #define SDMA2_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 6742 #define SDMA2_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 6743 #define SDMA2_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 6744 //SDMA2_PAGE_WATERMARK 6745 #define SDMA2_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 6746 #define SDMA2_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 6747 #define SDMA2_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 6748 #define SDMA2_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 6749 //SDMA2_PAGE_DOORBELL_OFFSET 6750 #define SDMA2_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 6751 #define SDMA2_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 6752 //SDMA2_PAGE_CSA_ADDR_LO 6753 #define SDMA2_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 6754 #define SDMA2_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 6755 //SDMA2_PAGE_CSA_ADDR_HI 6756 #define SDMA2_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 6757 #define SDMA2_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 6758 //SDMA2_PAGE_IB_SUB_REMAIN 6759 #define SDMA2_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 6760 #define SDMA2_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 6761 //SDMA2_PAGE_PREEMPT 6762 #define SDMA2_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 6763 #define SDMA2_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 6764 //SDMA2_PAGE_DUMMY_REG 6765 #define SDMA2_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 6766 #define SDMA2_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 6767 //SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI 6768 #define SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 6769 #define SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 6770 //SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO 6771 #define SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 6772 #define SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 6773 //SDMA2_PAGE_RB_AQL_CNTL 6774 #define SDMA2_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 6775 #define SDMA2_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 6776 #define SDMA2_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 6777 #define SDMA2_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 6778 #define SDMA2_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 6779 #define SDMA2_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 6780 //SDMA2_PAGE_MINOR_PTR_UPDATE 6781 #define SDMA2_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 6782 #define SDMA2_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 6783 //SDMA2_PAGE_MIDCMD_DATA0 6784 #define SDMA2_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 6785 #define SDMA2_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 6786 //SDMA2_PAGE_MIDCMD_DATA1 6787 #define SDMA2_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 6788 #define SDMA2_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 6789 //SDMA2_PAGE_MIDCMD_DATA2 6790 #define SDMA2_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 6791 #define SDMA2_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 6792 //SDMA2_PAGE_MIDCMD_DATA3 6793 #define SDMA2_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 6794 #define SDMA2_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 6795 //SDMA2_PAGE_MIDCMD_DATA4 6796 #define SDMA2_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 6797 #define SDMA2_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 6798 //SDMA2_PAGE_MIDCMD_DATA5 6799 #define SDMA2_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 6800 #define SDMA2_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 6801 //SDMA2_PAGE_MIDCMD_DATA6 6802 #define SDMA2_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 6803 #define SDMA2_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 6804 //SDMA2_PAGE_MIDCMD_DATA7 6805 #define SDMA2_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 6806 #define SDMA2_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 6807 //SDMA2_PAGE_MIDCMD_DATA8 6808 #define SDMA2_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 6809 #define SDMA2_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 6810 //SDMA2_PAGE_MIDCMD_DATA9 6811 #define SDMA2_PAGE_MIDCMD_DATA9__DATA9__SHIFT 0x0 6812 #define SDMA2_PAGE_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 6813 //SDMA2_PAGE_MIDCMD_DATA10 6814 #define SDMA2_PAGE_MIDCMD_DATA10__DATA10__SHIFT 0x0 6815 #define SDMA2_PAGE_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 6816 //SDMA2_PAGE_MIDCMD_CNTL 6817 #define SDMA2_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 6818 #define SDMA2_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 6819 #define SDMA2_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 6820 #define SDMA2_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 6821 #define SDMA2_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 6822 #define SDMA2_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 6823 #define SDMA2_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 6824 #define SDMA2_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 6825 //SDMA2_RLC0_RB_CNTL 6826 #define SDMA2_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 6827 #define SDMA2_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 6828 #define SDMA2_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 6829 #define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 6830 #define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 6831 #define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 6832 #define SDMA2_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 6833 #define SDMA2_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 6834 #define SDMA2_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 6835 #define SDMA2_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL 6836 #define SDMA2_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 6837 #define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 6838 #define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 6839 #define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 6840 #define SDMA2_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 6841 #define SDMA2_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 6842 //SDMA2_RLC0_RB_BASE 6843 #define SDMA2_RLC0_RB_BASE__ADDR__SHIFT 0x0 6844 #define SDMA2_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 6845 //SDMA2_RLC0_RB_BASE_HI 6846 #define SDMA2_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 6847 #define SDMA2_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 6848 //SDMA2_RLC0_RB_RPTR 6849 #define SDMA2_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 6850 #define SDMA2_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 6851 //SDMA2_RLC0_RB_RPTR_HI 6852 #define SDMA2_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 6853 #define SDMA2_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 6854 //SDMA2_RLC0_RB_WPTR 6855 #define SDMA2_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 6856 #define SDMA2_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 6857 //SDMA2_RLC0_RB_WPTR_HI 6858 #define SDMA2_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 6859 #define SDMA2_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 6860 //SDMA2_RLC0_RB_WPTR_POLL_CNTL 6861 #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 6862 #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 6863 #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 6864 #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 6865 #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 6866 #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 6867 #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 6868 #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 6869 #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 6870 #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 6871 //SDMA2_RLC0_RB_RPTR_ADDR_HI 6872 #define SDMA2_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 6873 #define SDMA2_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 6874 //SDMA2_RLC0_RB_RPTR_ADDR_LO 6875 #define SDMA2_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 6876 #define SDMA2_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 6877 #define SDMA2_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 6878 #define SDMA2_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 6879 //SDMA2_RLC0_IB_CNTL 6880 #define SDMA2_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 6881 #define SDMA2_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 6882 #define SDMA2_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 6883 #define SDMA2_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 6884 #define SDMA2_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 6885 #define SDMA2_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 6886 #define SDMA2_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 6887 #define SDMA2_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 6888 //SDMA2_RLC0_IB_RPTR 6889 #define SDMA2_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 6890 #define SDMA2_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 6891 //SDMA2_RLC0_IB_OFFSET 6892 #define SDMA2_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 6893 #define SDMA2_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 6894 //SDMA2_RLC0_IB_BASE_LO 6895 #define SDMA2_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 6896 #define SDMA2_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 6897 //SDMA2_RLC0_IB_BASE_HI 6898 #define SDMA2_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 6899 #define SDMA2_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 6900 //SDMA2_RLC0_IB_SIZE 6901 #define SDMA2_RLC0_IB_SIZE__SIZE__SHIFT 0x0 6902 #define SDMA2_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 6903 //SDMA2_RLC0_SKIP_CNTL 6904 #define SDMA2_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 6905 #define SDMA2_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 6906 //SDMA2_RLC0_CONTEXT_STATUS 6907 #define SDMA2_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 6908 #define SDMA2_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 6909 #define SDMA2_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 6910 #define SDMA2_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 6911 #define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 6912 #define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 6913 #define SDMA2_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 6914 #define SDMA2_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 6915 #define SDMA2_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 6916 #define SDMA2_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 6917 #define SDMA2_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 6918 #define SDMA2_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 6919 #define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 6920 #define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 6921 #define SDMA2_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 6922 #define SDMA2_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 6923 //SDMA2_RLC0_DOORBELL 6924 #define SDMA2_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 6925 #define SDMA2_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 6926 #define SDMA2_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 6927 #define SDMA2_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 6928 //SDMA2_RLC0_STATUS 6929 #define SDMA2_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 6930 #define SDMA2_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 6931 #define SDMA2_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 6932 #define SDMA2_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 6933 //SDMA2_RLC0_DOORBELL_LOG 6934 #define SDMA2_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 6935 #define SDMA2_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 6936 #define SDMA2_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 6937 #define SDMA2_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 6938 //SDMA2_RLC0_WATERMARK 6939 #define SDMA2_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 6940 #define SDMA2_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 6941 #define SDMA2_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 6942 #define SDMA2_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 6943 //SDMA2_RLC0_DOORBELL_OFFSET 6944 #define SDMA2_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 6945 #define SDMA2_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 6946 //SDMA2_RLC0_CSA_ADDR_LO 6947 #define SDMA2_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 6948 #define SDMA2_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 6949 //SDMA2_RLC0_CSA_ADDR_HI 6950 #define SDMA2_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 6951 #define SDMA2_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 6952 //SDMA2_RLC0_IB_SUB_REMAIN 6953 #define SDMA2_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 6954 #define SDMA2_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 6955 //SDMA2_RLC0_PREEMPT 6956 #define SDMA2_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 6957 #define SDMA2_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 6958 //SDMA2_RLC0_DUMMY_REG 6959 #define SDMA2_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 6960 #define SDMA2_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 6961 //SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI 6962 #define SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 6963 #define SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 6964 //SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO 6965 #define SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 6966 #define SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 6967 //SDMA2_RLC0_RB_AQL_CNTL 6968 #define SDMA2_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 6969 #define SDMA2_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 6970 #define SDMA2_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 6971 #define SDMA2_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 6972 #define SDMA2_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 6973 #define SDMA2_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 6974 //SDMA2_RLC0_MINOR_PTR_UPDATE 6975 #define SDMA2_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 6976 #define SDMA2_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 6977 //SDMA2_RLC0_MIDCMD_DATA0 6978 #define SDMA2_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 6979 #define SDMA2_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 6980 //SDMA2_RLC0_MIDCMD_DATA1 6981 #define SDMA2_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 6982 #define SDMA2_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 6983 //SDMA2_RLC0_MIDCMD_DATA2 6984 #define SDMA2_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 6985 #define SDMA2_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 6986 //SDMA2_RLC0_MIDCMD_DATA3 6987 #define SDMA2_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 6988 #define SDMA2_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 6989 //SDMA2_RLC0_MIDCMD_DATA4 6990 #define SDMA2_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 6991 #define SDMA2_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 6992 //SDMA2_RLC0_MIDCMD_DATA5 6993 #define SDMA2_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 6994 #define SDMA2_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 6995 //SDMA2_RLC0_MIDCMD_DATA6 6996 #define SDMA2_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 6997 #define SDMA2_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 6998 //SDMA2_RLC0_MIDCMD_DATA7 6999 #define SDMA2_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 7000 #define SDMA2_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 7001 //SDMA2_RLC0_MIDCMD_DATA8 7002 #define SDMA2_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 7003 #define SDMA2_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 7004 //SDMA2_RLC0_MIDCMD_DATA9 7005 #define SDMA2_RLC0_MIDCMD_DATA9__DATA9__SHIFT 0x0 7006 #define SDMA2_RLC0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 7007 //SDMA2_RLC0_MIDCMD_DATA10 7008 #define SDMA2_RLC0_MIDCMD_DATA10__DATA10__SHIFT 0x0 7009 #define SDMA2_RLC0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 7010 //SDMA2_RLC0_MIDCMD_CNTL 7011 #define SDMA2_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 7012 #define SDMA2_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 7013 #define SDMA2_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 7014 #define SDMA2_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 7015 #define SDMA2_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 7016 #define SDMA2_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 7017 #define SDMA2_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 7018 #define SDMA2_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 7019 //SDMA2_RLC1_RB_CNTL 7020 #define SDMA2_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 7021 #define SDMA2_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 7022 #define SDMA2_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 7023 #define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 7024 #define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 7025 #define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 7026 #define SDMA2_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 7027 #define SDMA2_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 7028 #define SDMA2_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 7029 #define SDMA2_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL 7030 #define SDMA2_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 7031 #define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 7032 #define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 7033 #define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 7034 #define SDMA2_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 7035 #define SDMA2_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 7036 //SDMA2_RLC1_RB_BASE 7037 #define SDMA2_RLC1_RB_BASE__ADDR__SHIFT 0x0 7038 #define SDMA2_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 7039 //SDMA2_RLC1_RB_BASE_HI 7040 #define SDMA2_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 7041 #define SDMA2_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 7042 //SDMA2_RLC1_RB_RPTR 7043 #define SDMA2_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 7044 #define SDMA2_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 7045 //SDMA2_RLC1_RB_RPTR_HI 7046 #define SDMA2_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 7047 #define SDMA2_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 7048 //SDMA2_RLC1_RB_WPTR 7049 #define SDMA2_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 7050 #define SDMA2_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 7051 //SDMA2_RLC1_RB_WPTR_HI 7052 #define SDMA2_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 7053 #define SDMA2_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 7054 //SDMA2_RLC1_RB_WPTR_POLL_CNTL 7055 #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 7056 #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 7057 #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 7058 #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 7059 #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 7060 #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 7061 #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 7062 #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 7063 #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 7064 #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 7065 //SDMA2_RLC1_RB_RPTR_ADDR_HI 7066 #define SDMA2_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 7067 #define SDMA2_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 7068 //SDMA2_RLC1_RB_RPTR_ADDR_LO 7069 #define SDMA2_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 7070 #define SDMA2_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 7071 #define SDMA2_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 7072 #define SDMA2_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 7073 //SDMA2_RLC1_IB_CNTL 7074 #define SDMA2_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 7075 #define SDMA2_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 7076 #define SDMA2_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 7077 #define SDMA2_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 7078 #define SDMA2_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 7079 #define SDMA2_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 7080 #define SDMA2_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 7081 #define SDMA2_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 7082 //SDMA2_RLC1_IB_RPTR 7083 #define SDMA2_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 7084 #define SDMA2_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 7085 //SDMA2_RLC1_IB_OFFSET 7086 #define SDMA2_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 7087 #define SDMA2_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 7088 //SDMA2_RLC1_IB_BASE_LO 7089 #define SDMA2_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 7090 #define SDMA2_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 7091 //SDMA2_RLC1_IB_BASE_HI 7092 #define SDMA2_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 7093 #define SDMA2_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 7094 //SDMA2_RLC1_IB_SIZE 7095 #define SDMA2_RLC1_IB_SIZE__SIZE__SHIFT 0x0 7096 #define SDMA2_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 7097 //SDMA2_RLC1_SKIP_CNTL 7098 #define SDMA2_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 7099 #define SDMA2_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 7100 //SDMA2_RLC1_CONTEXT_STATUS 7101 #define SDMA2_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 7102 #define SDMA2_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 7103 #define SDMA2_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 7104 #define SDMA2_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 7105 #define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 7106 #define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 7107 #define SDMA2_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 7108 #define SDMA2_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 7109 #define SDMA2_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 7110 #define SDMA2_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 7111 #define SDMA2_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 7112 #define SDMA2_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 7113 #define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 7114 #define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 7115 #define SDMA2_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 7116 #define SDMA2_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 7117 //SDMA2_RLC1_DOORBELL 7118 #define SDMA2_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 7119 #define SDMA2_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 7120 #define SDMA2_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 7121 #define SDMA2_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 7122 //SDMA2_RLC1_STATUS 7123 #define SDMA2_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 7124 #define SDMA2_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 7125 #define SDMA2_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 7126 #define SDMA2_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 7127 //SDMA2_RLC1_DOORBELL_LOG 7128 #define SDMA2_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 7129 #define SDMA2_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 7130 #define SDMA2_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 7131 #define SDMA2_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 7132 //SDMA2_RLC1_WATERMARK 7133 #define SDMA2_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 7134 #define SDMA2_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 7135 #define SDMA2_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 7136 #define SDMA2_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 7137 //SDMA2_RLC1_DOORBELL_OFFSET 7138 #define SDMA2_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 7139 #define SDMA2_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 7140 //SDMA2_RLC1_CSA_ADDR_LO 7141 #define SDMA2_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 7142 #define SDMA2_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 7143 //SDMA2_RLC1_CSA_ADDR_HI 7144 #define SDMA2_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 7145 #define SDMA2_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 7146 //SDMA2_RLC1_IB_SUB_REMAIN 7147 #define SDMA2_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 7148 #define SDMA2_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 7149 //SDMA2_RLC1_PREEMPT 7150 #define SDMA2_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 7151 #define SDMA2_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 7152 //SDMA2_RLC1_DUMMY_REG 7153 #define SDMA2_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 7154 #define SDMA2_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 7155 //SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI 7156 #define SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 7157 #define SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 7158 //SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO 7159 #define SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 7160 #define SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 7161 //SDMA2_RLC1_RB_AQL_CNTL 7162 #define SDMA2_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 7163 #define SDMA2_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 7164 #define SDMA2_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 7165 #define SDMA2_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 7166 #define SDMA2_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 7167 #define SDMA2_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 7168 //SDMA2_RLC1_MINOR_PTR_UPDATE 7169 #define SDMA2_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 7170 #define SDMA2_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 7171 //SDMA2_RLC1_MIDCMD_DATA0 7172 #define SDMA2_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 7173 #define SDMA2_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 7174 //SDMA2_RLC1_MIDCMD_DATA1 7175 #define SDMA2_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 7176 #define SDMA2_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 7177 //SDMA2_RLC1_MIDCMD_DATA2 7178 #define SDMA2_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 7179 #define SDMA2_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 7180 //SDMA2_RLC1_MIDCMD_DATA3 7181 #define SDMA2_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 7182 #define SDMA2_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 7183 //SDMA2_RLC1_MIDCMD_DATA4 7184 #define SDMA2_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 7185 #define SDMA2_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 7186 //SDMA2_RLC1_MIDCMD_DATA5 7187 #define SDMA2_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 7188 #define SDMA2_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 7189 //SDMA2_RLC1_MIDCMD_DATA6 7190 #define SDMA2_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 7191 #define SDMA2_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 7192 //SDMA2_RLC1_MIDCMD_DATA7 7193 #define SDMA2_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 7194 #define SDMA2_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 7195 //SDMA2_RLC1_MIDCMD_DATA8 7196 #define SDMA2_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 7197 #define SDMA2_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 7198 //SDMA2_RLC1_MIDCMD_DATA9 7199 #define SDMA2_RLC1_MIDCMD_DATA9__DATA9__SHIFT 0x0 7200 #define SDMA2_RLC1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 7201 //SDMA2_RLC1_MIDCMD_DATA10 7202 #define SDMA2_RLC1_MIDCMD_DATA10__DATA10__SHIFT 0x0 7203 #define SDMA2_RLC1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 7204 //SDMA2_RLC1_MIDCMD_CNTL 7205 #define SDMA2_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 7206 #define SDMA2_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 7207 #define SDMA2_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 7208 #define SDMA2_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 7209 #define SDMA2_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 7210 #define SDMA2_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 7211 #define SDMA2_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 7212 #define SDMA2_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 7213 //SDMA2_RLC2_RB_CNTL 7214 #define SDMA2_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 7215 #define SDMA2_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 7216 #define SDMA2_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 7217 #define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 7218 #define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 7219 #define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 7220 #define SDMA2_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 7221 #define SDMA2_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 7222 #define SDMA2_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L 7223 #define SDMA2_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL 7224 #define SDMA2_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 7225 #define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 7226 #define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 7227 #define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 7228 #define SDMA2_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L 7229 #define SDMA2_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L 7230 //SDMA2_RLC2_RB_BASE 7231 #define SDMA2_RLC2_RB_BASE__ADDR__SHIFT 0x0 7232 #define SDMA2_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL 7233 //SDMA2_RLC2_RB_BASE_HI 7234 #define SDMA2_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 7235 #define SDMA2_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 7236 //SDMA2_RLC2_RB_RPTR 7237 #define SDMA2_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 7238 #define SDMA2_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 7239 //SDMA2_RLC2_RB_RPTR_HI 7240 #define SDMA2_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 7241 #define SDMA2_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 7242 //SDMA2_RLC2_RB_WPTR 7243 #define SDMA2_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 7244 #define SDMA2_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 7245 //SDMA2_RLC2_RB_WPTR_HI 7246 #define SDMA2_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 7247 #define SDMA2_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 7248 //SDMA2_RLC2_RB_WPTR_POLL_CNTL 7249 #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 7250 #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 7251 #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 7252 #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 7253 #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 7254 #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 7255 #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 7256 #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 7257 #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 7258 #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 7259 //SDMA2_RLC2_RB_RPTR_ADDR_HI 7260 #define SDMA2_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 7261 #define SDMA2_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 7262 //SDMA2_RLC2_RB_RPTR_ADDR_LO 7263 #define SDMA2_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 7264 #define SDMA2_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 7265 #define SDMA2_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 7266 #define SDMA2_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 7267 //SDMA2_RLC2_IB_CNTL 7268 #define SDMA2_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 7269 #define SDMA2_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 7270 #define SDMA2_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 7271 #define SDMA2_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 7272 #define SDMA2_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L 7273 #define SDMA2_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 7274 #define SDMA2_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 7275 #define SDMA2_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L 7276 //SDMA2_RLC2_IB_RPTR 7277 #define SDMA2_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 7278 #define SDMA2_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL 7279 //SDMA2_RLC2_IB_OFFSET 7280 #define SDMA2_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 7281 #define SDMA2_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 7282 //SDMA2_RLC2_IB_BASE_LO 7283 #define SDMA2_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 7284 #define SDMA2_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 7285 //SDMA2_RLC2_IB_BASE_HI 7286 #define SDMA2_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 7287 #define SDMA2_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 7288 //SDMA2_RLC2_IB_SIZE 7289 #define SDMA2_RLC2_IB_SIZE__SIZE__SHIFT 0x0 7290 #define SDMA2_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL 7291 //SDMA2_RLC2_SKIP_CNTL 7292 #define SDMA2_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 7293 #define SDMA2_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 7294 //SDMA2_RLC2_CONTEXT_STATUS 7295 #define SDMA2_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 7296 #define SDMA2_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 7297 #define SDMA2_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 7298 #define SDMA2_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 7299 #define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 7300 #define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 7301 #define SDMA2_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 7302 #define SDMA2_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 7303 #define SDMA2_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 7304 #define SDMA2_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L 7305 #define SDMA2_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 7306 #define SDMA2_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 7307 #define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 7308 #define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 7309 #define SDMA2_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 7310 #define SDMA2_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 7311 //SDMA2_RLC2_DOORBELL 7312 #define SDMA2_RLC2_DOORBELL__ENABLE__SHIFT 0x1c 7313 #define SDMA2_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e 7314 #define SDMA2_RLC2_DOORBELL__ENABLE_MASK 0x10000000L 7315 #define SDMA2_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L 7316 //SDMA2_RLC2_STATUS 7317 #define SDMA2_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 7318 #define SDMA2_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 7319 #define SDMA2_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 7320 #define SDMA2_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 7321 //SDMA2_RLC2_DOORBELL_LOG 7322 #define SDMA2_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 7323 #define SDMA2_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 7324 #define SDMA2_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 7325 #define SDMA2_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 7326 //SDMA2_RLC2_WATERMARK 7327 #define SDMA2_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 7328 #define SDMA2_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 7329 #define SDMA2_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 7330 #define SDMA2_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 7331 //SDMA2_RLC2_DOORBELL_OFFSET 7332 #define SDMA2_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 7333 #define SDMA2_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 7334 //SDMA2_RLC2_CSA_ADDR_LO 7335 #define SDMA2_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 7336 #define SDMA2_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 7337 //SDMA2_RLC2_CSA_ADDR_HI 7338 #define SDMA2_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 7339 #define SDMA2_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 7340 //SDMA2_RLC2_IB_SUB_REMAIN 7341 #define SDMA2_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 7342 #define SDMA2_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 7343 //SDMA2_RLC2_PREEMPT 7344 #define SDMA2_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 7345 #define SDMA2_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L 7346 //SDMA2_RLC2_DUMMY_REG 7347 #define SDMA2_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 7348 #define SDMA2_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 7349 //SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI 7350 #define SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 7351 #define SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 7352 //SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO 7353 #define SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 7354 #define SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 7355 //SDMA2_RLC2_RB_AQL_CNTL 7356 #define SDMA2_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 7357 #define SDMA2_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 7358 #define SDMA2_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 7359 #define SDMA2_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 7360 #define SDMA2_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 7361 #define SDMA2_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 7362 //SDMA2_RLC2_MINOR_PTR_UPDATE 7363 #define SDMA2_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 7364 #define SDMA2_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 7365 //SDMA2_RLC2_MIDCMD_DATA0 7366 #define SDMA2_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 7367 #define SDMA2_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 7368 //SDMA2_RLC2_MIDCMD_DATA1 7369 #define SDMA2_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 7370 #define SDMA2_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 7371 //SDMA2_RLC2_MIDCMD_DATA2 7372 #define SDMA2_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 7373 #define SDMA2_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 7374 //SDMA2_RLC2_MIDCMD_DATA3 7375 #define SDMA2_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 7376 #define SDMA2_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 7377 //SDMA2_RLC2_MIDCMD_DATA4 7378 #define SDMA2_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 7379 #define SDMA2_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 7380 //SDMA2_RLC2_MIDCMD_DATA5 7381 #define SDMA2_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 7382 #define SDMA2_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 7383 //SDMA2_RLC2_MIDCMD_DATA6 7384 #define SDMA2_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 7385 #define SDMA2_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 7386 //SDMA2_RLC2_MIDCMD_DATA7 7387 #define SDMA2_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 7388 #define SDMA2_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 7389 //SDMA2_RLC2_MIDCMD_DATA8 7390 #define SDMA2_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 7391 #define SDMA2_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 7392 //SDMA2_RLC2_MIDCMD_DATA9 7393 #define SDMA2_RLC2_MIDCMD_DATA9__DATA9__SHIFT 0x0 7394 #define SDMA2_RLC2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 7395 //SDMA2_RLC2_MIDCMD_DATA10 7396 #define SDMA2_RLC2_MIDCMD_DATA10__DATA10__SHIFT 0x0 7397 #define SDMA2_RLC2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 7398 //SDMA2_RLC2_MIDCMD_CNTL 7399 #define SDMA2_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 7400 #define SDMA2_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 7401 #define SDMA2_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 7402 #define SDMA2_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 7403 #define SDMA2_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 7404 #define SDMA2_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 7405 #define SDMA2_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 7406 #define SDMA2_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 7407 //SDMA2_RLC3_RB_CNTL 7408 #define SDMA2_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 7409 #define SDMA2_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 7410 #define SDMA2_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 7411 #define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 7412 #define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 7413 #define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 7414 #define SDMA2_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 7415 #define SDMA2_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 7416 #define SDMA2_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L 7417 #define SDMA2_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL 7418 #define SDMA2_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 7419 #define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 7420 #define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 7421 #define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 7422 #define SDMA2_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L 7423 #define SDMA2_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L 7424 //SDMA2_RLC3_RB_BASE 7425 #define SDMA2_RLC3_RB_BASE__ADDR__SHIFT 0x0 7426 #define SDMA2_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL 7427 //SDMA2_RLC3_RB_BASE_HI 7428 #define SDMA2_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 7429 #define SDMA2_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 7430 //SDMA2_RLC3_RB_RPTR 7431 #define SDMA2_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 7432 #define SDMA2_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 7433 //SDMA2_RLC3_RB_RPTR_HI 7434 #define SDMA2_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 7435 #define SDMA2_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 7436 //SDMA2_RLC3_RB_WPTR 7437 #define SDMA2_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 7438 #define SDMA2_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 7439 //SDMA2_RLC3_RB_WPTR_HI 7440 #define SDMA2_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 7441 #define SDMA2_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 7442 //SDMA2_RLC3_RB_WPTR_POLL_CNTL 7443 #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 7444 #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 7445 #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 7446 #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 7447 #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 7448 #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 7449 #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 7450 #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 7451 #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 7452 #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 7453 //SDMA2_RLC3_RB_RPTR_ADDR_HI 7454 #define SDMA2_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 7455 #define SDMA2_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 7456 //SDMA2_RLC3_RB_RPTR_ADDR_LO 7457 #define SDMA2_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 7458 #define SDMA2_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 7459 #define SDMA2_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 7460 #define SDMA2_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 7461 //SDMA2_RLC3_IB_CNTL 7462 #define SDMA2_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 7463 #define SDMA2_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 7464 #define SDMA2_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 7465 #define SDMA2_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 7466 #define SDMA2_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L 7467 #define SDMA2_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 7468 #define SDMA2_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 7469 #define SDMA2_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L 7470 //SDMA2_RLC3_IB_RPTR 7471 #define SDMA2_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 7472 #define SDMA2_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL 7473 //SDMA2_RLC3_IB_OFFSET 7474 #define SDMA2_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 7475 #define SDMA2_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 7476 //SDMA2_RLC3_IB_BASE_LO 7477 #define SDMA2_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 7478 #define SDMA2_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 7479 //SDMA2_RLC3_IB_BASE_HI 7480 #define SDMA2_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 7481 #define SDMA2_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 7482 //SDMA2_RLC3_IB_SIZE 7483 #define SDMA2_RLC3_IB_SIZE__SIZE__SHIFT 0x0 7484 #define SDMA2_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL 7485 //SDMA2_RLC3_SKIP_CNTL 7486 #define SDMA2_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 7487 #define SDMA2_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 7488 //SDMA2_RLC3_CONTEXT_STATUS 7489 #define SDMA2_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 7490 #define SDMA2_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 7491 #define SDMA2_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 7492 #define SDMA2_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 7493 #define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 7494 #define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 7495 #define SDMA2_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 7496 #define SDMA2_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 7497 #define SDMA2_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 7498 #define SDMA2_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L 7499 #define SDMA2_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 7500 #define SDMA2_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 7501 #define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 7502 #define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 7503 #define SDMA2_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 7504 #define SDMA2_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 7505 //SDMA2_RLC3_DOORBELL 7506 #define SDMA2_RLC3_DOORBELL__ENABLE__SHIFT 0x1c 7507 #define SDMA2_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e 7508 #define SDMA2_RLC3_DOORBELL__ENABLE_MASK 0x10000000L 7509 #define SDMA2_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L 7510 //SDMA2_RLC3_STATUS 7511 #define SDMA2_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 7512 #define SDMA2_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 7513 #define SDMA2_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 7514 #define SDMA2_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 7515 //SDMA2_RLC3_DOORBELL_LOG 7516 #define SDMA2_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 7517 #define SDMA2_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 7518 #define SDMA2_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 7519 #define SDMA2_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 7520 //SDMA2_RLC3_WATERMARK 7521 #define SDMA2_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 7522 #define SDMA2_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 7523 #define SDMA2_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 7524 #define SDMA2_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 7525 //SDMA2_RLC3_DOORBELL_OFFSET 7526 #define SDMA2_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 7527 #define SDMA2_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 7528 //SDMA2_RLC3_CSA_ADDR_LO 7529 #define SDMA2_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 7530 #define SDMA2_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 7531 //SDMA2_RLC3_CSA_ADDR_HI 7532 #define SDMA2_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 7533 #define SDMA2_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 7534 //SDMA2_RLC3_IB_SUB_REMAIN 7535 #define SDMA2_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 7536 #define SDMA2_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 7537 //SDMA2_RLC3_PREEMPT 7538 #define SDMA2_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 7539 #define SDMA2_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L 7540 //SDMA2_RLC3_DUMMY_REG 7541 #define SDMA2_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 7542 #define SDMA2_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 7543 //SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI 7544 #define SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 7545 #define SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 7546 //SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO 7547 #define SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 7548 #define SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 7549 //SDMA2_RLC3_RB_AQL_CNTL 7550 #define SDMA2_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 7551 #define SDMA2_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 7552 #define SDMA2_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 7553 #define SDMA2_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 7554 #define SDMA2_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 7555 #define SDMA2_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 7556 //SDMA2_RLC3_MINOR_PTR_UPDATE 7557 #define SDMA2_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 7558 #define SDMA2_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 7559 //SDMA2_RLC3_MIDCMD_DATA0 7560 #define SDMA2_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 7561 #define SDMA2_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 7562 //SDMA2_RLC3_MIDCMD_DATA1 7563 #define SDMA2_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 7564 #define SDMA2_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 7565 //SDMA2_RLC3_MIDCMD_DATA2 7566 #define SDMA2_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 7567 #define SDMA2_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 7568 //SDMA2_RLC3_MIDCMD_DATA3 7569 #define SDMA2_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 7570 #define SDMA2_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 7571 //SDMA2_RLC3_MIDCMD_DATA4 7572 #define SDMA2_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 7573 #define SDMA2_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 7574 //SDMA2_RLC3_MIDCMD_DATA5 7575 #define SDMA2_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 7576 #define SDMA2_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 7577 //SDMA2_RLC3_MIDCMD_DATA6 7578 #define SDMA2_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 7579 #define SDMA2_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 7580 //SDMA2_RLC3_MIDCMD_DATA7 7581 #define SDMA2_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 7582 #define SDMA2_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 7583 //SDMA2_RLC3_MIDCMD_DATA8 7584 #define SDMA2_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 7585 #define SDMA2_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 7586 //SDMA2_RLC3_MIDCMD_DATA9 7587 #define SDMA2_RLC3_MIDCMD_DATA9__DATA9__SHIFT 0x0 7588 #define SDMA2_RLC3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 7589 //SDMA2_RLC3_MIDCMD_DATA10 7590 #define SDMA2_RLC3_MIDCMD_DATA10__DATA10__SHIFT 0x0 7591 #define SDMA2_RLC3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 7592 //SDMA2_RLC3_MIDCMD_CNTL 7593 #define SDMA2_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 7594 #define SDMA2_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 7595 #define SDMA2_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 7596 #define SDMA2_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 7597 #define SDMA2_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 7598 #define SDMA2_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 7599 #define SDMA2_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 7600 #define SDMA2_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 7601 //SDMA2_RLC4_RB_CNTL 7602 #define SDMA2_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 7603 #define SDMA2_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 7604 #define SDMA2_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 7605 #define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 7606 #define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 7607 #define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 7608 #define SDMA2_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 7609 #define SDMA2_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 7610 #define SDMA2_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L 7611 #define SDMA2_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL 7612 #define SDMA2_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 7613 #define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 7614 #define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 7615 #define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 7616 #define SDMA2_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L 7617 #define SDMA2_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L 7618 //SDMA2_RLC4_RB_BASE 7619 #define SDMA2_RLC4_RB_BASE__ADDR__SHIFT 0x0 7620 #define SDMA2_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL 7621 //SDMA2_RLC4_RB_BASE_HI 7622 #define SDMA2_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 7623 #define SDMA2_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 7624 //SDMA2_RLC4_RB_RPTR 7625 #define SDMA2_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 7626 #define SDMA2_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 7627 //SDMA2_RLC4_RB_RPTR_HI 7628 #define SDMA2_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 7629 #define SDMA2_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 7630 //SDMA2_RLC4_RB_WPTR 7631 #define SDMA2_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 7632 #define SDMA2_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 7633 //SDMA2_RLC4_RB_WPTR_HI 7634 #define SDMA2_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 7635 #define SDMA2_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 7636 //SDMA2_RLC4_RB_WPTR_POLL_CNTL 7637 #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 7638 #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 7639 #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 7640 #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 7641 #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 7642 #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 7643 #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 7644 #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 7645 #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 7646 #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 7647 //SDMA2_RLC4_RB_RPTR_ADDR_HI 7648 #define SDMA2_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 7649 #define SDMA2_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 7650 //SDMA2_RLC4_RB_RPTR_ADDR_LO 7651 #define SDMA2_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 7652 #define SDMA2_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 7653 #define SDMA2_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 7654 #define SDMA2_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 7655 //SDMA2_RLC4_IB_CNTL 7656 #define SDMA2_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 7657 #define SDMA2_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 7658 #define SDMA2_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 7659 #define SDMA2_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 7660 #define SDMA2_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L 7661 #define SDMA2_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 7662 #define SDMA2_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 7663 #define SDMA2_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L 7664 //SDMA2_RLC4_IB_RPTR 7665 #define SDMA2_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 7666 #define SDMA2_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL 7667 //SDMA2_RLC4_IB_OFFSET 7668 #define SDMA2_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 7669 #define SDMA2_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 7670 //SDMA2_RLC4_IB_BASE_LO 7671 #define SDMA2_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 7672 #define SDMA2_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 7673 //SDMA2_RLC4_IB_BASE_HI 7674 #define SDMA2_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 7675 #define SDMA2_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 7676 //SDMA2_RLC4_IB_SIZE 7677 #define SDMA2_RLC4_IB_SIZE__SIZE__SHIFT 0x0 7678 #define SDMA2_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL 7679 //SDMA2_RLC4_SKIP_CNTL 7680 #define SDMA2_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 7681 #define SDMA2_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 7682 //SDMA2_RLC4_CONTEXT_STATUS 7683 #define SDMA2_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 7684 #define SDMA2_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 7685 #define SDMA2_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 7686 #define SDMA2_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 7687 #define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 7688 #define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 7689 #define SDMA2_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 7690 #define SDMA2_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 7691 #define SDMA2_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 7692 #define SDMA2_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L 7693 #define SDMA2_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 7694 #define SDMA2_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 7695 #define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 7696 #define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 7697 #define SDMA2_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 7698 #define SDMA2_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 7699 //SDMA2_RLC4_DOORBELL 7700 #define SDMA2_RLC4_DOORBELL__ENABLE__SHIFT 0x1c 7701 #define SDMA2_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e 7702 #define SDMA2_RLC4_DOORBELL__ENABLE_MASK 0x10000000L 7703 #define SDMA2_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L 7704 //SDMA2_RLC4_STATUS 7705 #define SDMA2_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 7706 #define SDMA2_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 7707 #define SDMA2_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 7708 #define SDMA2_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 7709 //SDMA2_RLC4_DOORBELL_LOG 7710 #define SDMA2_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 7711 #define SDMA2_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 7712 #define SDMA2_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 7713 #define SDMA2_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 7714 //SDMA2_RLC4_WATERMARK 7715 #define SDMA2_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 7716 #define SDMA2_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 7717 #define SDMA2_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 7718 #define SDMA2_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 7719 //SDMA2_RLC4_DOORBELL_OFFSET 7720 #define SDMA2_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 7721 #define SDMA2_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 7722 //SDMA2_RLC4_CSA_ADDR_LO 7723 #define SDMA2_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 7724 #define SDMA2_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 7725 //SDMA2_RLC4_CSA_ADDR_HI 7726 #define SDMA2_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 7727 #define SDMA2_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 7728 //SDMA2_RLC4_IB_SUB_REMAIN 7729 #define SDMA2_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 7730 #define SDMA2_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 7731 //SDMA2_RLC4_PREEMPT 7732 #define SDMA2_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 7733 #define SDMA2_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L 7734 //SDMA2_RLC4_DUMMY_REG 7735 #define SDMA2_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 7736 #define SDMA2_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 7737 //SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI 7738 #define SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 7739 #define SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 7740 //SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO 7741 #define SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 7742 #define SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 7743 //SDMA2_RLC4_RB_AQL_CNTL 7744 #define SDMA2_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 7745 #define SDMA2_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 7746 #define SDMA2_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 7747 #define SDMA2_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 7748 #define SDMA2_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 7749 #define SDMA2_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 7750 //SDMA2_RLC4_MINOR_PTR_UPDATE 7751 #define SDMA2_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 7752 #define SDMA2_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 7753 //SDMA2_RLC4_MIDCMD_DATA0 7754 #define SDMA2_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 7755 #define SDMA2_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 7756 //SDMA2_RLC4_MIDCMD_DATA1 7757 #define SDMA2_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 7758 #define SDMA2_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 7759 //SDMA2_RLC4_MIDCMD_DATA2 7760 #define SDMA2_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 7761 #define SDMA2_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 7762 //SDMA2_RLC4_MIDCMD_DATA3 7763 #define SDMA2_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 7764 #define SDMA2_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 7765 //SDMA2_RLC4_MIDCMD_DATA4 7766 #define SDMA2_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 7767 #define SDMA2_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 7768 //SDMA2_RLC4_MIDCMD_DATA5 7769 #define SDMA2_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 7770 #define SDMA2_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 7771 //SDMA2_RLC4_MIDCMD_DATA6 7772 #define SDMA2_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 7773 #define SDMA2_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 7774 //SDMA2_RLC4_MIDCMD_DATA7 7775 #define SDMA2_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 7776 #define SDMA2_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 7777 //SDMA2_RLC4_MIDCMD_DATA8 7778 #define SDMA2_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 7779 #define SDMA2_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 7780 //SDMA2_RLC4_MIDCMD_DATA9 7781 #define SDMA2_RLC4_MIDCMD_DATA9__DATA9__SHIFT 0x0 7782 #define SDMA2_RLC4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 7783 //SDMA2_RLC4_MIDCMD_DATA10 7784 #define SDMA2_RLC4_MIDCMD_DATA10__DATA10__SHIFT 0x0 7785 #define SDMA2_RLC4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 7786 //SDMA2_RLC4_MIDCMD_CNTL 7787 #define SDMA2_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 7788 #define SDMA2_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 7789 #define SDMA2_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 7790 #define SDMA2_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 7791 #define SDMA2_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 7792 #define SDMA2_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 7793 #define SDMA2_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 7794 #define SDMA2_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 7795 //SDMA2_RLC5_RB_CNTL 7796 #define SDMA2_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 7797 #define SDMA2_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 7798 #define SDMA2_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 7799 #define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 7800 #define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 7801 #define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 7802 #define SDMA2_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 7803 #define SDMA2_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 7804 #define SDMA2_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L 7805 #define SDMA2_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL 7806 #define SDMA2_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 7807 #define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 7808 #define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 7809 #define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 7810 #define SDMA2_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L 7811 #define SDMA2_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L 7812 //SDMA2_RLC5_RB_BASE 7813 #define SDMA2_RLC5_RB_BASE__ADDR__SHIFT 0x0 7814 #define SDMA2_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL 7815 //SDMA2_RLC5_RB_BASE_HI 7816 #define SDMA2_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 7817 #define SDMA2_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 7818 //SDMA2_RLC5_RB_RPTR 7819 #define SDMA2_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 7820 #define SDMA2_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 7821 //SDMA2_RLC5_RB_RPTR_HI 7822 #define SDMA2_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 7823 #define SDMA2_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 7824 //SDMA2_RLC5_RB_WPTR 7825 #define SDMA2_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 7826 #define SDMA2_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 7827 //SDMA2_RLC5_RB_WPTR_HI 7828 #define SDMA2_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 7829 #define SDMA2_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 7830 //SDMA2_RLC5_RB_WPTR_POLL_CNTL 7831 #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 7832 #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 7833 #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 7834 #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 7835 #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 7836 #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 7837 #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 7838 #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 7839 #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 7840 #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 7841 //SDMA2_RLC5_RB_RPTR_ADDR_HI 7842 #define SDMA2_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 7843 #define SDMA2_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 7844 //SDMA2_RLC5_RB_RPTR_ADDR_LO 7845 #define SDMA2_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 7846 #define SDMA2_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 7847 #define SDMA2_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 7848 #define SDMA2_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 7849 //SDMA2_RLC5_IB_CNTL 7850 #define SDMA2_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 7851 #define SDMA2_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 7852 #define SDMA2_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 7853 #define SDMA2_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 7854 #define SDMA2_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L 7855 #define SDMA2_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 7856 #define SDMA2_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 7857 #define SDMA2_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L 7858 //SDMA2_RLC5_IB_RPTR 7859 #define SDMA2_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 7860 #define SDMA2_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL 7861 //SDMA2_RLC5_IB_OFFSET 7862 #define SDMA2_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 7863 #define SDMA2_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 7864 //SDMA2_RLC5_IB_BASE_LO 7865 #define SDMA2_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 7866 #define SDMA2_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 7867 //SDMA2_RLC5_IB_BASE_HI 7868 #define SDMA2_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 7869 #define SDMA2_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 7870 //SDMA2_RLC5_IB_SIZE 7871 #define SDMA2_RLC5_IB_SIZE__SIZE__SHIFT 0x0 7872 #define SDMA2_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL 7873 //SDMA2_RLC5_SKIP_CNTL 7874 #define SDMA2_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 7875 #define SDMA2_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 7876 //SDMA2_RLC5_CONTEXT_STATUS 7877 #define SDMA2_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 7878 #define SDMA2_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 7879 #define SDMA2_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 7880 #define SDMA2_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 7881 #define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 7882 #define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 7883 #define SDMA2_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 7884 #define SDMA2_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 7885 #define SDMA2_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 7886 #define SDMA2_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L 7887 #define SDMA2_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 7888 #define SDMA2_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 7889 #define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 7890 #define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 7891 #define SDMA2_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 7892 #define SDMA2_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 7893 //SDMA2_RLC5_DOORBELL 7894 #define SDMA2_RLC5_DOORBELL__ENABLE__SHIFT 0x1c 7895 #define SDMA2_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e 7896 #define SDMA2_RLC5_DOORBELL__ENABLE_MASK 0x10000000L 7897 #define SDMA2_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L 7898 //SDMA2_RLC5_STATUS 7899 #define SDMA2_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 7900 #define SDMA2_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 7901 #define SDMA2_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 7902 #define SDMA2_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 7903 //SDMA2_RLC5_DOORBELL_LOG 7904 #define SDMA2_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 7905 #define SDMA2_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 7906 #define SDMA2_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 7907 #define SDMA2_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 7908 //SDMA2_RLC5_WATERMARK 7909 #define SDMA2_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 7910 #define SDMA2_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 7911 #define SDMA2_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 7912 #define SDMA2_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 7913 //SDMA2_RLC5_DOORBELL_OFFSET 7914 #define SDMA2_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 7915 #define SDMA2_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 7916 //SDMA2_RLC5_CSA_ADDR_LO 7917 #define SDMA2_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 7918 #define SDMA2_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 7919 //SDMA2_RLC5_CSA_ADDR_HI 7920 #define SDMA2_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 7921 #define SDMA2_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 7922 //SDMA2_RLC5_IB_SUB_REMAIN 7923 #define SDMA2_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 7924 #define SDMA2_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 7925 //SDMA2_RLC5_PREEMPT 7926 #define SDMA2_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 7927 #define SDMA2_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L 7928 //SDMA2_RLC5_DUMMY_REG 7929 #define SDMA2_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 7930 #define SDMA2_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 7931 //SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI 7932 #define SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 7933 #define SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 7934 //SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO 7935 #define SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 7936 #define SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 7937 //SDMA2_RLC5_RB_AQL_CNTL 7938 #define SDMA2_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 7939 #define SDMA2_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 7940 #define SDMA2_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 7941 #define SDMA2_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 7942 #define SDMA2_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 7943 #define SDMA2_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 7944 //SDMA2_RLC5_MINOR_PTR_UPDATE 7945 #define SDMA2_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 7946 #define SDMA2_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 7947 //SDMA2_RLC5_MIDCMD_DATA0 7948 #define SDMA2_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 7949 #define SDMA2_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 7950 //SDMA2_RLC5_MIDCMD_DATA1 7951 #define SDMA2_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 7952 #define SDMA2_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 7953 //SDMA2_RLC5_MIDCMD_DATA2 7954 #define SDMA2_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 7955 #define SDMA2_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 7956 //SDMA2_RLC5_MIDCMD_DATA3 7957 #define SDMA2_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 7958 #define SDMA2_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 7959 //SDMA2_RLC5_MIDCMD_DATA4 7960 #define SDMA2_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 7961 #define SDMA2_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 7962 //SDMA2_RLC5_MIDCMD_DATA5 7963 #define SDMA2_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 7964 #define SDMA2_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 7965 //SDMA2_RLC5_MIDCMD_DATA6 7966 #define SDMA2_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 7967 #define SDMA2_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 7968 //SDMA2_RLC5_MIDCMD_DATA7 7969 #define SDMA2_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 7970 #define SDMA2_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 7971 //SDMA2_RLC5_MIDCMD_DATA8 7972 #define SDMA2_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 7973 #define SDMA2_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 7974 //SDMA2_RLC5_MIDCMD_DATA9 7975 #define SDMA2_RLC5_MIDCMD_DATA9__DATA9__SHIFT 0x0 7976 #define SDMA2_RLC5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 7977 //SDMA2_RLC5_MIDCMD_DATA10 7978 #define SDMA2_RLC5_MIDCMD_DATA10__DATA10__SHIFT 0x0 7979 #define SDMA2_RLC5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 7980 //SDMA2_RLC5_MIDCMD_CNTL 7981 #define SDMA2_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 7982 #define SDMA2_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 7983 #define SDMA2_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 7984 #define SDMA2_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 7985 #define SDMA2_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 7986 #define SDMA2_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 7987 #define SDMA2_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 7988 #define SDMA2_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 7989 //SDMA2_RLC6_RB_CNTL 7990 #define SDMA2_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 7991 #define SDMA2_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 7992 #define SDMA2_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 7993 #define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 7994 #define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 7995 #define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 7996 #define SDMA2_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 7997 #define SDMA2_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 7998 #define SDMA2_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L 7999 #define SDMA2_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL 8000 #define SDMA2_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 8001 #define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 8002 #define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 8003 #define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 8004 #define SDMA2_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L 8005 #define SDMA2_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L 8006 //SDMA2_RLC6_RB_BASE 8007 #define SDMA2_RLC6_RB_BASE__ADDR__SHIFT 0x0 8008 #define SDMA2_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL 8009 //SDMA2_RLC6_RB_BASE_HI 8010 #define SDMA2_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 8011 #define SDMA2_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 8012 //SDMA2_RLC6_RB_RPTR 8013 #define SDMA2_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 8014 #define SDMA2_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 8015 //SDMA2_RLC6_RB_RPTR_HI 8016 #define SDMA2_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 8017 #define SDMA2_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 8018 //SDMA2_RLC6_RB_WPTR 8019 #define SDMA2_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 8020 #define SDMA2_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 8021 //SDMA2_RLC6_RB_WPTR_HI 8022 #define SDMA2_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 8023 #define SDMA2_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 8024 //SDMA2_RLC6_RB_WPTR_POLL_CNTL 8025 #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 8026 #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 8027 #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 8028 #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 8029 #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 8030 #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 8031 #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 8032 #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 8033 #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 8034 #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 8035 //SDMA2_RLC6_RB_RPTR_ADDR_HI 8036 #define SDMA2_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 8037 #define SDMA2_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 8038 //SDMA2_RLC6_RB_RPTR_ADDR_LO 8039 #define SDMA2_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 8040 #define SDMA2_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 8041 #define SDMA2_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 8042 #define SDMA2_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 8043 //SDMA2_RLC6_IB_CNTL 8044 #define SDMA2_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 8045 #define SDMA2_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 8046 #define SDMA2_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 8047 #define SDMA2_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 8048 #define SDMA2_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L 8049 #define SDMA2_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 8050 #define SDMA2_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 8051 #define SDMA2_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L 8052 //SDMA2_RLC6_IB_RPTR 8053 #define SDMA2_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 8054 #define SDMA2_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL 8055 //SDMA2_RLC6_IB_OFFSET 8056 #define SDMA2_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 8057 #define SDMA2_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 8058 //SDMA2_RLC6_IB_BASE_LO 8059 #define SDMA2_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 8060 #define SDMA2_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 8061 //SDMA2_RLC6_IB_BASE_HI 8062 #define SDMA2_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 8063 #define SDMA2_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 8064 //SDMA2_RLC6_IB_SIZE 8065 #define SDMA2_RLC6_IB_SIZE__SIZE__SHIFT 0x0 8066 #define SDMA2_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL 8067 //SDMA2_RLC6_SKIP_CNTL 8068 #define SDMA2_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 8069 #define SDMA2_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 8070 //SDMA2_RLC6_CONTEXT_STATUS 8071 #define SDMA2_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 8072 #define SDMA2_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 8073 #define SDMA2_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 8074 #define SDMA2_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 8075 #define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 8076 #define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 8077 #define SDMA2_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 8078 #define SDMA2_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 8079 #define SDMA2_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 8080 #define SDMA2_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L 8081 #define SDMA2_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 8082 #define SDMA2_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 8083 #define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 8084 #define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 8085 #define SDMA2_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 8086 #define SDMA2_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 8087 //SDMA2_RLC6_DOORBELL 8088 #define SDMA2_RLC6_DOORBELL__ENABLE__SHIFT 0x1c 8089 #define SDMA2_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e 8090 #define SDMA2_RLC6_DOORBELL__ENABLE_MASK 0x10000000L 8091 #define SDMA2_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L 8092 //SDMA2_RLC6_STATUS 8093 #define SDMA2_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 8094 #define SDMA2_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 8095 #define SDMA2_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 8096 #define SDMA2_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 8097 //SDMA2_RLC6_DOORBELL_LOG 8098 #define SDMA2_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 8099 #define SDMA2_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 8100 #define SDMA2_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 8101 #define SDMA2_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 8102 //SDMA2_RLC6_WATERMARK 8103 #define SDMA2_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 8104 #define SDMA2_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 8105 #define SDMA2_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 8106 #define SDMA2_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 8107 //SDMA2_RLC6_DOORBELL_OFFSET 8108 #define SDMA2_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 8109 #define SDMA2_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 8110 //SDMA2_RLC6_CSA_ADDR_LO 8111 #define SDMA2_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 8112 #define SDMA2_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 8113 //SDMA2_RLC6_CSA_ADDR_HI 8114 #define SDMA2_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 8115 #define SDMA2_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 8116 //SDMA2_RLC6_IB_SUB_REMAIN 8117 #define SDMA2_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 8118 #define SDMA2_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 8119 //SDMA2_RLC6_PREEMPT 8120 #define SDMA2_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 8121 #define SDMA2_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L 8122 //SDMA2_RLC6_DUMMY_REG 8123 #define SDMA2_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 8124 #define SDMA2_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 8125 //SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI 8126 #define SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 8127 #define SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 8128 //SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO 8129 #define SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 8130 #define SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 8131 //SDMA2_RLC6_RB_AQL_CNTL 8132 #define SDMA2_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 8133 #define SDMA2_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 8134 #define SDMA2_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 8135 #define SDMA2_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 8136 #define SDMA2_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 8137 #define SDMA2_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 8138 //SDMA2_RLC6_MINOR_PTR_UPDATE 8139 #define SDMA2_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 8140 #define SDMA2_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 8141 //SDMA2_RLC6_MIDCMD_DATA0 8142 #define SDMA2_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 8143 #define SDMA2_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 8144 //SDMA2_RLC6_MIDCMD_DATA1 8145 #define SDMA2_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 8146 #define SDMA2_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 8147 //SDMA2_RLC6_MIDCMD_DATA2 8148 #define SDMA2_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 8149 #define SDMA2_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 8150 //SDMA2_RLC6_MIDCMD_DATA3 8151 #define SDMA2_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 8152 #define SDMA2_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 8153 //SDMA2_RLC6_MIDCMD_DATA4 8154 #define SDMA2_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 8155 #define SDMA2_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 8156 //SDMA2_RLC6_MIDCMD_DATA5 8157 #define SDMA2_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 8158 #define SDMA2_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 8159 //SDMA2_RLC6_MIDCMD_DATA6 8160 #define SDMA2_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 8161 #define SDMA2_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 8162 //SDMA2_RLC6_MIDCMD_DATA7 8163 #define SDMA2_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 8164 #define SDMA2_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 8165 //SDMA2_RLC6_MIDCMD_DATA8 8166 #define SDMA2_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 8167 #define SDMA2_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 8168 //SDMA2_RLC6_MIDCMD_DATA9 8169 #define SDMA2_RLC6_MIDCMD_DATA9__DATA9__SHIFT 0x0 8170 #define SDMA2_RLC6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 8171 //SDMA2_RLC6_MIDCMD_DATA10 8172 #define SDMA2_RLC6_MIDCMD_DATA10__DATA10__SHIFT 0x0 8173 #define SDMA2_RLC6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 8174 //SDMA2_RLC6_MIDCMD_CNTL 8175 #define SDMA2_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 8176 #define SDMA2_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 8177 #define SDMA2_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 8178 #define SDMA2_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 8179 #define SDMA2_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 8180 #define SDMA2_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 8181 #define SDMA2_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 8182 #define SDMA2_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 8183 //SDMA2_RLC7_RB_CNTL 8184 #define SDMA2_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 8185 #define SDMA2_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 8186 #define SDMA2_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 8187 #define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 8188 #define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 8189 #define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 8190 #define SDMA2_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 8191 #define SDMA2_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 8192 #define SDMA2_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L 8193 #define SDMA2_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL 8194 #define SDMA2_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 8195 #define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 8196 #define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 8197 #define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 8198 #define SDMA2_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L 8199 #define SDMA2_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L 8200 //SDMA2_RLC7_RB_BASE 8201 #define SDMA2_RLC7_RB_BASE__ADDR__SHIFT 0x0 8202 #define SDMA2_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL 8203 //SDMA2_RLC7_RB_BASE_HI 8204 #define SDMA2_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 8205 #define SDMA2_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 8206 //SDMA2_RLC7_RB_RPTR 8207 #define SDMA2_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 8208 #define SDMA2_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 8209 //SDMA2_RLC7_RB_RPTR_HI 8210 #define SDMA2_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 8211 #define SDMA2_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 8212 //SDMA2_RLC7_RB_WPTR 8213 #define SDMA2_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 8214 #define SDMA2_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 8215 //SDMA2_RLC7_RB_WPTR_HI 8216 #define SDMA2_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 8217 #define SDMA2_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 8218 //SDMA2_RLC7_RB_WPTR_POLL_CNTL 8219 #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 8220 #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 8221 #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 8222 #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 8223 #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 8224 #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 8225 #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 8226 #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 8227 #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 8228 #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 8229 //SDMA2_RLC7_RB_RPTR_ADDR_HI 8230 #define SDMA2_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 8231 #define SDMA2_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 8232 //SDMA2_RLC7_RB_RPTR_ADDR_LO 8233 #define SDMA2_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 8234 #define SDMA2_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 8235 #define SDMA2_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 8236 #define SDMA2_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 8237 //SDMA2_RLC7_IB_CNTL 8238 #define SDMA2_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 8239 #define SDMA2_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 8240 #define SDMA2_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 8241 #define SDMA2_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 8242 #define SDMA2_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L 8243 #define SDMA2_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 8244 #define SDMA2_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 8245 #define SDMA2_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L 8246 //SDMA2_RLC7_IB_RPTR 8247 #define SDMA2_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 8248 #define SDMA2_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL 8249 //SDMA2_RLC7_IB_OFFSET 8250 #define SDMA2_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 8251 #define SDMA2_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 8252 //SDMA2_RLC7_IB_BASE_LO 8253 #define SDMA2_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 8254 #define SDMA2_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 8255 //SDMA2_RLC7_IB_BASE_HI 8256 #define SDMA2_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 8257 #define SDMA2_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 8258 //SDMA2_RLC7_IB_SIZE 8259 #define SDMA2_RLC7_IB_SIZE__SIZE__SHIFT 0x0 8260 #define SDMA2_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL 8261 //SDMA2_RLC7_SKIP_CNTL 8262 #define SDMA2_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 8263 #define SDMA2_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 8264 //SDMA2_RLC7_CONTEXT_STATUS 8265 #define SDMA2_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 8266 #define SDMA2_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 8267 #define SDMA2_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 8268 #define SDMA2_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 8269 #define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 8270 #define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 8271 #define SDMA2_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 8272 #define SDMA2_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 8273 #define SDMA2_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 8274 #define SDMA2_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L 8275 #define SDMA2_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 8276 #define SDMA2_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 8277 #define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 8278 #define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 8279 #define SDMA2_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 8280 #define SDMA2_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 8281 //SDMA2_RLC7_DOORBELL 8282 #define SDMA2_RLC7_DOORBELL__ENABLE__SHIFT 0x1c 8283 #define SDMA2_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e 8284 #define SDMA2_RLC7_DOORBELL__ENABLE_MASK 0x10000000L 8285 #define SDMA2_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L 8286 //SDMA2_RLC7_STATUS 8287 #define SDMA2_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 8288 #define SDMA2_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 8289 #define SDMA2_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 8290 #define SDMA2_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 8291 //SDMA2_RLC7_DOORBELL_LOG 8292 #define SDMA2_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 8293 #define SDMA2_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 8294 #define SDMA2_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 8295 #define SDMA2_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 8296 //SDMA2_RLC7_WATERMARK 8297 #define SDMA2_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 8298 #define SDMA2_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 8299 #define SDMA2_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 8300 #define SDMA2_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 8301 //SDMA2_RLC7_DOORBELL_OFFSET 8302 #define SDMA2_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 8303 #define SDMA2_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 8304 //SDMA2_RLC7_CSA_ADDR_LO 8305 #define SDMA2_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 8306 #define SDMA2_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 8307 //SDMA2_RLC7_CSA_ADDR_HI 8308 #define SDMA2_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 8309 #define SDMA2_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 8310 //SDMA2_RLC7_IB_SUB_REMAIN 8311 #define SDMA2_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 8312 #define SDMA2_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 8313 //SDMA2_RLC7_PREEMPT 8314 #define SDMA2_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 8315 #define SDMA2_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L 8316 //SDMA2_RLC7_DUMMY_REG 8317 #define SDMA2_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 8318 #define SDMA2_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 8319 //SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI 8320 #define SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 8321 #define SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 8322 //SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO 8323 #define SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 8324 #define SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 8325 //SDMA2_RLC7_RB_AQL_CNTL 8326 #define SDMA2_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 8327 #define SDMA2_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 8328 #define SDMA2_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 8329 #define SDMA2_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 8330 #define SDMA2_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 8331 #define SDMA2_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 8332 //SDMA2_RLC7_MINOR_PTR_UPDATE 8333 #define SDMA2_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 8334 #define SDMA2_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 8335 //SDMA2_RLC7_MIDCMD_DATA0 8336 #define SDMA2_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 8337 #define SDMA2_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 8338 //SDMA2_RLC7_MIDCMD_DATA1 8339 #define SDMA2_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 8340 #define SDMA2_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 8341 //SDMA2_RLC7_MIDCMD_DATA2 8342 #define SDMA2_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 8343 #define SDMA2_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 8344 //SDMA2_RLC7_MIDCMD_DATA3 8345 #define SDMA2_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 8346 #define SDMA2_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 8347 //SDMA2_RLC7_MIDCMD_DATA4 8348 #define SDMA2_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 8349 #define SDMA2_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 8350 //SDMA2_RLC7_MIDCMD_DATA5 8351 #define SDMA2_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 8352 #define SDMA2_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 8353 //SDMA2_RLC7_MIDCMD_DATA6 8354 #define SDMA2_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 8355 #define SDMA2_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 8356 //SDMA2_RLC7_MIDCMD_DATA7 8357 #define SDMA2_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 8358 #define SDMA2_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 8359 //SDMA2_RLC7_MIDCMD_DATA8 8360 #define SDMA2_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 8361 #define SDMA2_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 8362 //SDMA2_RLC7_MIDCMD_DATA9 8363 #define SDMA2_RLC7_MIDCMD_DATA9__DATA9__SHIFT 0x0 8364 #define SDMA2_RLC7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 8365 //SDMA2_RLC7_MIDCMD_DATA10 8366 #define SDMA2_RLC7_MIDCMD_DATA10__DATA10__SHIFT 0x0 8367 #define SDMA2_RLC7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 8368 //SDMA2_RLC7_MIDCMD_CNTL 8369 #define SDMA2_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 8370 #define SDMA2_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 8371 #define SDMA2_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 8372 #define SDMA2_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 8373 #define SDMA2_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 8374 #define SDMA2_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 8375 #define SDMA2_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 8376 #define SDMA2_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 8377 8378 8379 // addressBlock: sdma0_sdma3dec 8380 //SDMA3_UCODE_ADDR 8381 #define SDMA3_UCODE_ADDR__VALUE__SHIFT 0x0 8382 #define SDMA3_UCODE_ADDR__VALUE_MASK 0x00003FFFL 8383 //SDMA3_UCODE_DATA 8384 #define SDMA3_UCODE_DATA__VALUE__SHIFT 0x0 8385 #define SDMA3_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 8386 //SDMA3_VF_ENABLE 8387 #define SDMA3_VF_ENABLE__VF_ENABLE__SHIFT 0x0 8388 #define SDMA3_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 8389 #define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_ADDR__SHIFT 0x0 8390 #define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_DATA__SHIFT 0x1 8391 #define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_ADDR_MASK 0x00000001L 8392 #define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_DATA_MASK 0x00000002L 8393 //SDMA3_CONTEXT_GROUP_BOUNDARY 8394 #define SDMA3_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 8395 #define SDMA3_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 8396 //SDMA3_POWER_CNTL 8397 #define SDMA3_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 8398 #define SDMA3_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 8399 #define SDMA3_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 8400 #define SDMA3_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 8401 #define SDMA3_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 8402 #define SDMA3_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 8403 #define SDMA3_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 8404 #define SDMA3_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 8405 #define SDMA3_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 8406 #define SDMA3_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a 8407 #define SDMA3_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L 8408 #define SDMA3_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L 8409 #define SDMA3_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L 8410 #define SDMA3_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 8411 #define SDMA3_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 8412 #define SDMA3_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 8413 #define SDMA3_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 8414 #define SDMA3_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 8415 #define SDMA3_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 8416 #define SDMA3_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 8417 //SDMA3_CLK_CTRL 8418 #define SDMA3_CLK_CTRL__ON_DELAY__SHIFT 0x0 8419 #define SDMA3_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 8420 #define SDMA3_CLK_CTRL__RESERVED__SHIFT 0xc 8421 #define SDMA3_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 8422 #define SDMA3_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 8423 #define SDMA3_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 8424 #define SDMA3_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 8425 #define SDMA3_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 8426 #define SDMA3_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 8427 #define SDMA3_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 8428 #define SDMA3_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 8429 #define SDMA3_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 8430 #define SDMA3_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 8431 #define SDMA3_CLK_CTRL__RESERVED_MASK 0x00FFF000L 8432 #define SDMA3_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 8433 #define SDMA3_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 8434 #define SDMA3_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 8435 #define SDMA3_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 8436 #define SDMA3_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 8437 #define SDMA3_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 8438 #define SDMA3_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 8439 #define SDMA3_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 8440 //SDMA3_CNTL 8441 #define SDMA3_CNTL__TRAP_ENABLE__SHIFT 0x0 8442 #define SDMA3_CNTL__UTC_L1_ENABLE__SHIFT 0x1 8443 #define SDMA3_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 8444 #define SDMA3_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 8445 #define SDMA3_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 8446 #define SDMA3_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 8447 #define SDMA3_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x6 8448 #define SDMA3_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 8449 #define SDMA3_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 8450 #define SDMA3_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 8451 #define SDMA3_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 8452 #define SDMA3_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 8453 #define SDMA3_CNTL__TRAP_ENABLE_MASK 0x00000001L 8454 #define SDMA3_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 8455 #define SDMA3_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 8456 #define SDMA3_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 8457 #define SDMA3_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 8458 #define SDMA3_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 8459 #define SDMA3_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000040L 8460 #define SDMA3_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 8461 #define SDMA3_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 8462 #define SDMA3_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 8463 #define SDMA3_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 8464 #define SDMA3_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 8465 //SDMA3_CHICKEN_BITS 8466 #define SDMA3_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 8467 #define SDMA3_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 8468 #define SDMA3_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 8469 #define SDMA3_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 8470 #define SDMA3_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 8471 #define SDMA3_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 8472 #define SDMA3_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 8473 #define SDMA3_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 8474 #define SDMA3_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 8475 #define SDMA3_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 8476 #define SDMA3_CHICKEN_BITS__SRAM_FGCG_ENABLE__SHIFT 0x1a 8477 #define SDMA3_CHICKEN_BITS__RESERVED__SHIFT 0x1b 8478 #define SDMA3_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 8479 #define SDMA3_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 8480 #define SDMA3_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 8481 #define SDMA3_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 8482 #define SDMA3_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 8483 #define SDMA3_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 8484 #define SDMA3_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 8485 #define SDMA3_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 8486 #define SDMA3_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 8487 #define SDMA3_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 8488 #define SDMA3_CHICKEN_BITS__SRAM_FGCG_ENABLE_MASK 0x04000000L 8489 #define SDMA3_CHICKEN_BITS__RESERVED_MASK 0xF8000000L 8490 //SDMA3_GB_ADDR_CONFIG 8491 #define SDMA3_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 8492 #define SDMA3_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 8493 #define SDMA3_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 8494 #define SDMA3_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 8495 #define SDMA3_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 8496 #define SDMA3_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 8497 #define SDMA3_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 8498 #define SDMA3_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 8499 #define SDMA3_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 8500 #define SDMA3_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 8501 //SDMA3_GB_ADDR_CONFIG_READ 8502 #define SDMA3_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 8503 #define SDMA3_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 8504 #define SDMA3_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 8505 #define SDMA3_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 8506 #define SDMA3_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 8507 #define SDMA3_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 8508 #define SDMA3_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 8509 #define SDMA3_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 8510 #define SDMA3_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 8511 #define SDMA3_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 8512 //SDMA3_RB_RPTR_FETCH_HI 8513 #define SDMA3_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 8514 #define SDMA3_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 8515 //SDMA3_SEM_WAIT_FAIL_TIMER_CNTL 8516 #define SDMA3_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 8517 #define SDMA3_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 8518 //SDMA3_RB_RPTR_FETCH 8519 #define SDMA3_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 8520 #define SDMA3_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 8521 //SDMA3_IB_OFFSET_FETCH 8522 #define SDMA3_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 8523 #define SDMA3_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 8524 //SDMA3_PROGRAM 8525 #define SDMA3_PROGRAM__STREAM__SHIFT 0x0 8526 #define SDMA3_PROGRAM__STREAM_MASK 0xFFFFFFFFL 8527 //SDMA3_STATUS_REG 8528 #define SDMA3_STATUS_REG__IDLE__SHIFT 0x0 8529 #define SDMA3_STATUS_REG__REG_IDLE__SHIFT 0x1 8530 #define SDMA3_STATUS_REG__RB_EMPTY__SHIFT 0x2 8531 #define SDMA3_STATUS_REG__RB_FULL__SHIFT 0x3 8532 #define SDMA3_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 8533 #define SDMA3_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 8534 #define SDMA3_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 8535 #define SDMA3_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 8536 #define SDMA3_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 8537 #define SDMA3_STATUS_REG__INSIDE_IB__SHIFT 0x9 8538 #define SDMA3_STATUS_REG__EX_IDLE__SHIFT 0xa 8539 #define SDMA3_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 8540 #define SDMA3_STATUS_REG__PACKET_READY__SHIFT 0xc 8541 #define SDMA3_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 8542 #define SDMA3_STATUS_REG__SRBM_IDLE__SHIFT 0xe 8543 #define SDMA3_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 8544 #define SDMA3_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 8545 #define SDMA3_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 8546 #define SDMA3_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 8547 #define SDMA3_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 8548 #define SDMA3_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 8549 #define SDMA3_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 8550 #define SDMA3_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 8551 #define SDMA3_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 8552 #define SDMA3_STATUS_REG__SEM_IDLE__SHIFT 0x1a 8553 #define SDMA3_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 8554 #define SDMA3_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 8555 #define SDMA3_STATUS_REG__INT_IDLE__SHIFT 0x1e 8556 #define SDMA3_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 8557 #define SDMA3_STATUS_REG__IDLE_MASK 0x00000001L 8558 #define SDMA3_STATUS_REG__REG_IDLE_MASK 0x00000002L 8559 #define SDMA3_STATUS_REG__RB_EMPTY_MASK 0x00000004L 8560 #define SDMA3_STATUS_REG__RB_FULL_MASK 0x00000008L 8561 #define SDMA3_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 8562 #define SDMA3_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 8563 #define SDMA3_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 8564 #define SDMA3_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 8565 #define SDMA3_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 8566 #define SDMA3_STATUS_REG__INSIDE_IB_MASK 0x00000200L 8567 #define SDMA3_STATUS_REG__EX_IDLE_MASK 0x00000400L 8568 #define SDMA3_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 8569 #define SDMA3_STATUS_REG__PACKET_READY_MASK 0x00001000L 8570 #define SDMA3_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 8571 #define SDMA3_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 8572 #define SDMA3_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 8573 #define SDMA3_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 8574 #define SDMA3_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 8575 #define SDMA3_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 8576 #define SDMA3_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 8577 #define SDMA3_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 8578 #define SDMA3_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 8579 #define SDMA3_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 8580 #define SDMA3_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 8581 #define SDMA3_STATUS_REG__SEM_IDLE_MASK 0x04000000L 8582 #define SDMA3_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 8583 #define SDMA3_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 8584 #define SDMA3_STATUS_REG__INT_IDLE_MASK 0x40000000L 8585 #define SDMA3_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 8586 //SDMA3_STATUS1_REG 8587 #define SDMA3_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 8588 #define SDMA3_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 8589 #define SDMA3_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 8590 #define SDMA3_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 8591 #define SDMA3_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 8592 #define SDMA3_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 8593 #define SDMA3_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 8594 #define SDMA3_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 8595 #define SDMA3_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 8596 #define SDMA3_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 8597 #define SDMA3_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 8598 #define SDMA3_STATUS1_REG__EX_START__SHIFT 0xf 8599 #define SDMA3_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 8600 #define SDMA3_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 8601 #define SDMA3_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 8602 #define SDMA3_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 8603 #define SDMA3_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 8604 #define SDMA3_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 8605 #define SDMA3_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 8606 #define SDMA3_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 8607 #define SDMA3_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 8608 #define SDMA3_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 8609 #define SDMA3_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 8610 #define SDMA3_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 8611 #define SDMA3_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 8612 #define SDMA3_STATUS1_REG__EX_START_MASK 0x00008000L 8613 #define SDMA3_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 8614 #define SDMA3_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 8615 //SDMA3_RD_BURST_CNTL 8616 #define SDMA3_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 8617 #define SDMA3_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 8618 #define SDMA3_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 8619 #define SDMA3_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL 8620 //SDMA3_HBM_PAGE_CONFIG 8621 #define SDMA3_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 8622 #define SDMA3_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L 8623 //SDMA3_UCODE_CHECKSUM 8624 #define SDMA3_UCODE_CHECKSUM__DATA__SHIFT 0x0 8625 #define SDMA3_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 8626 //SDMA3_F32_CNTL 8627 #define SDMA3_F32_CNTL__HALT__SHIFT 0x0 8628 #define SDMA3_F32_CNTL__STEP__SHIFT 0x1 8629 #define SDMA3_F32_CNTL__RESET__SHIFT 0x8 8630 #define SDMA3_F32_CNTL__HALT_MASK 0x00000001L 8631 #define SDMA3_F32_CNTL__STEP_MASK 0x00000002L 8632 #define SDMA3_F32_CNTL__RESET_MASK 0x00000100L 8633 //SDMA3_FREEZE 8634 #define SDMA3_FREEZE__PREEMPT__SHIFT 0x0 8635 #define SDMA3_FREEZE__FREEZE__SHIFT 0x4 8636 #define SDMA3_FREEZE__FROZEN__SHIFT 0x5 8637 #define SDMA3_FREEZE__F32_FREEZE__SHIFT 0x6 8638 #define SDMA3_FREEZE__PREEMPT_MASK 0x00000001L 8639 #define SDMA3_FREEZE__FREEZE_MASK 0x00000010L 8640 #define SDMA3_FREEZE__FROZEN_MASK 0x00000020L 8641 #define SDMA3_FREEZE__F32_FREEZE_MASK 0x00000040L 8642 //SDMA3_PHASE0_QUANTUM 8643 #define SDMA3_PHASE0_QUANTUM__UNIT__SHIFT 0x0 8644 #define SDMA3_PHASE0_QUANTUM__VALUE__SHIFT 0x8 8645 #define SDMA3_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 8646 #define SDMA3_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 8647 #define SDMA3_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 8648 #define SDMA3_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 8649 //SDMA3_PHASE1_QUANTUM 8650 #define SDMA3_PHASE1_QUANTUM__UNIT__SHIFT 0x0 8651 #define SDMA3_PHASE1_QUANTUM__VALUE__SHIFT 0x8 8652 #define SDMA3_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 8653 #define SDMA3_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 8654 #define SDMA3_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 8655 #define SDMA3_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 8656 //CC_SDMA3_EDC_CONFIG 8657 #define CC_SDMA3_EDC_CONFIG__DIS_EDC__SHIFT 0x1 8658 #define CC_SDMA3_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 8659 //SDMA3_BA_THRESHOLD 8660 #define SDMA3_BA_THRESHOLD__READ_THRES__SHIFT 0x0 8661 #define SDMA3_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 8662 #define SDMA3_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 8663 #define SDMA3_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 8664 //SDMA3_ID 8665 #define SDMA3_ID__DEVICE_ID__SHIFT 0x0 8666 #define SDMA3_ID__DEVICE_ID_MASK 0x000000FFL 8667 //SDMA3_VERSION 8668 #define SDMA3_VERSION__MINVER__SHIFT 0x0 8669 #define SDMA3_VERSION__MAJVER__SHIFT 0x8 8670 #define SDMA3_VERSION__REV__SHIFT 0x10 8671 #define SDMA3_VERSION__MINVER_MASK 0x0000007FL 8672 #define SDMA3_VERSION__MAJVER_MASK 0x00007F00L 8673 #define SDMA3_VERSION__REV_MASK 0x003F0000L 8674 //SDMA3_EDC_COUNTER 8675 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x0 8676 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x2 8677 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x4 8678 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0x6 8679 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0x8 8680 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa 8681 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xc 8682 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 8683 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0x10 8684 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x12 8685 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x14 8686 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x16 8687 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x18 8688 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x1a 8689 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x1c 8690 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x1e 8691 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000003L 8692 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x0000000CL 8693 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000030L 8694 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x000000C0L 8695 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000300L 8696 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00000C00L 8697 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00003000L 8698 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x0000C000L 8699 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00030000L 8700 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x000C0000L 8701 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00300000L 8702 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00C00000L 8703 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x03000000L 8704 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x0C000000L 8705 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x30000000L 8706 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0xC0000000L 8707 //SDMA3_EDC_COUNTER2 8708 #define SDMA3_EDC_COUNTER2__SDMA_UCODE_BUF_SED__SHIFT 0x0 8709 #define SDMA3_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 8710 #define SDMA3_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED__SHIFT 0x4 8711 #define SDMA3_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x6 8712 #define SDMA3_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x8 8713 #define SDMA3_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED__SHIFT 0xa 8714 #define SDMA3_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED__SHIFT 0xc 8715 #define SDMA3_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED__SHIFT 0xe 8716 #define SDMA3_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 8717 #define SDMA3_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED__SHIFT 0x12 8718 #define SDMA3_EDC_COUNTER2__SDMA_UCODE_BUF_SED_MASK 0x00000003L 8719 #define SDMA3_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED_MASK 0x0000000CL 8720 #define SDMA3_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED_MASK 0x00000030L 8721 #define SDMA3_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED_MASK 0x000000C0L 8722 #define SDMA3_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000300L 8723 #define SDMA3_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED_MASK 0x00000C00L 8724 #define SDMA3_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED_MASK 0x00003000L 8725 #define SDMA3_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED_MASK 0x0000C000L 8726 #define SDMA3_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00030000L 8727 #define SDMA3_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED_MASK 0x000C0000L 8728 //SDMA3_STATUS2_REG 8729 #define SDMA3_STATUS2_REG__ID__SHIFT 0x0 8730 #define SDMA3_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 8731 #define SDMA3_STATUS2_REG__CMD_OP__SHIFT 0x10 8732 #define SDMA3_STATUS2_REG__ID_MASK 0x00000007L 8733 #define SDMA3_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L 8734 #define SDMA3_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 8735 //SDMA3_ATOMIC_CNTL 8736 #define SDMA3_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 8737 #define SDMA3_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 8738 #define SDMA3_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 8739 #define SDMA3_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 8740 //SDMA3_ATOMIC_PREOP_LO 8741 #define SDMA3_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 8742 #define SDMA3_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 8743 //SDMA3_ATOMIC_PREOP_HI 8744 #define SDMA3_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 8745 #define SDMA3_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 8746 //SDMA3_UTCL1_CNTL 8747 #define SDMA3_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 8748 #define SDMA3_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 8749 #define SDMA3_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 8750 #define SDMA3_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 8751 #define SDMA3_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 8752 #define SDMA3_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 8753 #define SDMA3_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 8754 #define SDMA3_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 8755 #define SDMA3_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 8756 #define SDMA3_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 8757 #define SDMA3_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 8758 #define SDMA3_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 8759 //SDMA3_UTCL1_WATERMK 8760 #define SDMA3_UTCL1_WATERMK__REQ_WATERMK__SHIFT 0x0 8761 #define SDMA3_UTCL1_WATERMK__REQ_DEPTH__SHIFT 0x3 8762 #define SDMA3_UTCL1_WATERMK__PAGE_WATERMK__SHIFT 0x5 8763 #define SDMA3_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x8 8764 #define SDMA3_UTCL1_WATERMK__RESERVED__SHIFT 0x10 8765 #define SDMA3_UTCL1_WATERMK__REQ_WATERMK_MASK 0x00000007L 8766 #define SDMA3_UTCL1_WATERMK__REQ_DEPTH_MASK 0x00000018L 8767 #define SDMA3_UTCL1_WATERMK__PAGE_WATERMK_MASK 0x000000E0L 8768 #define SDMA3_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x0000FF00L 8769 #define SDMA3_UTCL1_WATERMK__RESERVED_MASK 0xFFFF0000L 8770 //SDMA3_UTCL1_RD_STATUS 8771 #define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 8772 #define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 8773 #define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 8774 #define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 8775 #define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 8776 #define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 8777 #define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 8778 #define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 8779 #define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 8780 #define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 8781 #define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 8782 #define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 8783 #define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 8784 #define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 8785 #define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 8786 #define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 8787 #define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 8788 #define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 8789 #define SDMA3_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 8790 #define SDMA3_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 8791 #define SDMA3_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 8792 #define SDMA3_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 8793 #define SDMA3_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 8794 #define SDMA3_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 8795 #define SDMA3_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 8796 #define SDMA3_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 8797 #define SDMA3_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 8798 #define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 8799 #define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 8800 #define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 8801 #define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 8802 #define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 8803 #define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 8804 #define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 8805 #define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 8806 #define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 8807 #define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 8808 #define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 8809 #define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 8810 #define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 8811 #define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 8812 #define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 8813 #define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 8814 #define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 8815 #define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 8816 #define SDMA3_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 8817 #define SDMA3_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 8818 #define SDMA3_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 8819 #define SDMA3_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 8820 #define SDMA3_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 8821 #define SDMA3_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 8822 #define SDMA3_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 8823 #define SDMA3_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 8824 #define SDMA3_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 8825 //SDMA3_UTCL1_WR_STATUS 8826 #define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 8827 #define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 8828 #define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 8829 #define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 8830 #define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 8831 #define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 8832 #define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 8833 #define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 8834 #define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 8835 #define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 8836 #define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 8837 #define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 8838 #define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 8839 #define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 8840 #define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 8841 #define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 8842 #define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 8843 #define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 8844 #define SDMA3_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 8845 #define SDMA3_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 8846 #define SDMA3_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 8847 #define SDMA3_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 8848 #define SDMA3_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 8849 #define SDMA3_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 8850 #define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 8851 #define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 8852 #define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 8853 #define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 8854 #define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 8855 #define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 8856 #define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 8857 #define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 8858 #define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 8859 #define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 8860 #define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 8861 #define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 8862 #define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 8863 #define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 8864 #define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 8865 #define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 8866 #define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 8867 #define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 8868 #define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 8869 #define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 8870 #define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 8871 #define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 8872 #define SDMA3_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 8873 #define SDMA3_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 8874 #define SDMA3_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 8875 #define SDMA3_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 8876 #define SDMA3_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 8877 #define SDMA3_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 8878 #define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 8879 #define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 8880 #define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 8881 #define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 8882 //SDMA3_UTCL1_INV0 8883 #define SDMA3_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 8884 #define SDMA3_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 8885 #define SDMA3_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 8886 #define SDMA3_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 8887 #define SDMA3_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 8888 #define SDMA3_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 8889 #define SDMA3_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 8890 #define SDMA3_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 8891 #define SDMA3_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 8892 #define SDMA3_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 8893 #define SDMA3_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 8894 #define SDMA3_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 8895 #define SDMA3_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 8896 #define SDMA3_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 8897 #define SDMA3_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 8898 #define SDMA3_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 8899 #define SDMA3_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 8900 #define SDMA3_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 8901 #define SDMA3_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 8902 #define SDMA3_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 8903 #define SDMA3_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 8904 #define SDMA3_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 8905 #define SDMA3_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 8906 #define SDMA3_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 8907 #define SDMA3_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 8908 #define SDMA3_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 8909 #define SDMA3_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 8910 #define SDMA3_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 8911 //SDMA3_UTCL1_INV1 8912 #define SDMA3_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 8913 #define SDMA3_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 8914 //SDMA3_UTCL1_INV2 8915 #define SDMA3_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 8916 #define SDMA3_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 8917 //SDMA3_UTCL1_RD_XNACK0 8918 #define SDMA3_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 8919 #define SDMA3_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 8920 //SDMA3_UTCL1_RD_XNACK1 8921 #define SDMA3_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 8922 #define SDMA3_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 8923 #define SDMA3_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 8924 #define SDMA3_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 8925 #define SDMA3_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 8926 #define SDMA3_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 8927 #define SDMA3_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 8928 #define SDMA3_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 8929 //SDMA3_UTCL1_WR_XNACK0 8930 #define SDMA3_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 8931 #define SDMA3_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 8932 //SDMA3_UTCL1_WR_XNACK1 8933 #define SDMA3_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 8934 #define SDMA3_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 8935 #define SDMA3_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 8936 #define SDMA3_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 8937 #define SDMA3_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 8938 #define SDMA3_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 8939 #define SDMA3_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 8940 #define SDMA3_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 8941 //SDMA3_UTCL1_TIMEOUT 8942 #define SDMA3_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 8943 #define SDMA3_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 8944 #define SDMA3_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 8945 #define SDMA3_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 8946 //SDMA3_UTCL1_PAGE 8947 #define SDMA3_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 8948 #define SDMA3_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 8949 #define SDMA3_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 8950 #define SDMA3_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 8951 #define SDMA3_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 8952 #define SDMA3_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 8953 #define SDMA3_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 8954 #define SDMA3_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 8955 //SDMA3_POWER_CNTL_IDLE 8956 #define SDMA3_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 8957 #define SDMA3_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 8958 #define SDMA3_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 8959 #define SDMA3_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 8960 #define SDMA3_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 8961 #define SDMA3_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 8962 //SDMA3_RELAX_ORDERING_LUT 8963 #define SDMA3_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 8964 #define SDMA3_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 8965 #define SDMA3_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 8966 #define SDMA3_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 8967 #define SDMA3_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 8968 #define SDMA3_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 8969 #define SDMA3_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 8970 #define SDMA3_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 8971 #define SDMA3_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 8972 #define SDMA3_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 8973 #define SDMA3_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 8974 #define SDMA3_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 8975 #define SDMA3_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 8976 #define SDMA3_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 8977 #define SDMA3_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 8978 #define SDMA3_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 8979 #define SDMA3_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 8980 #define SDMA3_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 8981 #define SDMA3_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 8982 #define SDMA3_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 8983 #define SDMA3_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 8984 #define SDMA3_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 8985 #define SDMA3_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 8986 #define SDMA3_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 8987 #define SDMA3_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 8988 #define SDMA3_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 8989 #define SDMA3_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 8990 #define SDMA3_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 8991 #define SDMA3_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 8992 #define SDMA3_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 8993 #define SDMA3_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 8994 #define SDMA3_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 8995 #define SDMA3_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 8996 #define SDMA3_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 8997 #define SDMA3_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 8998 #define SDMA3_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 8999 #define SDMA3_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 9000 #define SDMA3_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 9001 //SDMA3_CHICKEN_BITS_2 9002 #define SDMA3_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 9003 #define SDMA3_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x4 9004 #define SDMA3_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 9005 #define SDMA3_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00000010L 9006 //SDMA3_STATUS3_REG 9007 #define SDMA3_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 9008 #define SDMA3_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 9009 #define SDMA3_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 9010 #define SDMA3_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 9011 #define SDMA3_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 9012 #define SDMA3_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 9013 #define SDMA3_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 9014 #define SDMA3_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 9015 #define SDMA3_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L 9016 #define SDMA3_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L 9017 //SDMA3_PHYSICAL_ADDR_LO 9018 #define SDMA3_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 9019 #define SDMA3_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 9020 #define SDMA3_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 9021 #define SDMA3_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 9022 #define SDMA3_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 9023 #define SDMA3_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 9024 #define SDMA3_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 9025 #define SDMA3_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 9026 //SDMA3_PHYSICAL_ADDR_HI 9027 #define SDMA3_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 9028 #define SDMA3_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 9029 //SDMA3_PHASE2_QUANTUM 9030 #define SDMA3_PHASE2_QUANTUM__UNIT__SHIFT 0x0 9031 #define SDMA3_PHASE2_QUANTUM__VALUE__SHIFT 0x8 9032 #define SDMA3_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 9033 #define SDMA3_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 9034 #define SDMA3_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 9035 #define SDMA3_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 9036 //SDMA3_ERROR_LOG 9037 #define SDMA3_ERROR_LOG__OVERRIDE__SHIFT 0x0 9038 #define SDMA3_ERROR_LOG__STATUS__SHIFT 0x10 9039 #define SDMA3_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 9040 #define SDMA3_ERROR_LOG__STATUS_MASK 0xFFFF0000L 9041 //SDMA3_PUB_DUMMY_REG0 9042 #define SDMA3_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 9043 #define SDMA3_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 9044 //SDMA3_PUB_DUMMY_REG1 9045 #define SDMA3_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 9046 #define SDMA3_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 9047 //SDMA3_PUB_DUMMY_REG2 9048 #define SDMA3_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 9049 #define SDMA3_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 9050 //SDMA3_PUB_DUMMY_REG3 9051 #define SDMA3_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 9052 #define SDMA3_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 9053 //SDMA3_F32_COUNTER 9054 #define SDMA3_F32_COUNTER__VALUE__SHIFT 0x0 9055 #define SDMA3_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 9056 //SDMA3_PERFCNT_PERFCOUNTER0_CFG 9057 #define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 9058 #define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 9059 #define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 9060 #define SDMA3_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 9061 #define SDMA3_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 9062 #define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 9063 #define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 9064 #define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 9065 #define SDMA3_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 9066 #define SDMA3_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 9067 //SDMA3_PERFCNT_PERFCOUNTER1_CFG 9068 #define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 9069 #define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 9070 #define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 9071 #define SDMA3_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 9072 #define SDMA3_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 9073 #define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 9074 #define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 9075 #define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 9076 #define SDMA3_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 9077 #define SDMA3_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 9078 //SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL 9079 #define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 9080 #define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 9081 #define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 9082 #define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 9083 #define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 9084 #define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 9085 #define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 9086 #define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 9087 #define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 9088 #define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 9089 #define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 9090 #define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 9091 //SDMA3_PERFCNT_MISC_CNTL 9092 #define SDMA3_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 9093 #define SDMA3_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL 9094 //SDMA3_PERFCNT_PERFCOUNTER_LO 9095 #define SDMA3_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 9096 #define SDMA3_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 9097 //SDMA3_PERFCNT_PERFCOUNTER_HI 9098 #define SDMA3_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 9099 #define SDMA3_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 9100 #define SDMA3_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 9101 #define SDMA3_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 9102 //SDMA3_CRD_CNTL 9103 #define SDMA3_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 9104 #define SDMA3_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 9105 #define SDMA3_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 9106 #define SDMA3_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 9107 //SDMA3_ULV_CNTL 9108 #define SDMA3_ULV_CNTL__HYSTERESIS__SHIFT 0x0 9109 #define SDMA3_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b 9110 #define SDMA3_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c 9111 #define SDMA3_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 9112 #define SDMA3_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 9113 #define SDMA3_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 9114 #define SDMA3_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 9115 #define SDMA3_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L 9116 #define SDMA3_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L 9117 #define SDMA3_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 9118 #define SDMA3_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 9119 #define SDMA3_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 9120 //SDMA3_EA_DBIT_ADDR_DATA 9121 #define SDMA3_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 9122 #define SDMA3_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 9123 //SDMA3_EA_DBIT_ADDR_INDEX 9124 #define SDMA3_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 9125 #define SDMA3_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 9126 //SDMA3_STATUS4_REG 9127 #define SDMA3_STATUS4_REG__IDLE__SHIFT 0x0 9128 #define SDMA3_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2 9129 #define SDMA3_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3 9130 #define SDMA3_STATUS4_REG__MMHUB_RD_OUTSTANDING__SHIFT 0x4 9131 #define SDMA3_STATUS4_REG__MMHUB_WR_OUTSTANDING__SHIFT 0x5 9132 #define SDMA3_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x6 9133 #define SDMA3_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x7 9134 #define SDMA3_STATUS4_REG__REG_POLLING__SHIFT 0x8 9135 #define SDMA3_STATUS4_REG__MEM_POLLING__SHIFT 0x9 9136 #define SDMA3_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xa 9137 #define SDMA3_STATUS4_REG__UTCL2_WR_XNACK__SHIFT 0xc 9138 #define SDMA3_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0xe 9139 #define SDMA3_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x12 9140 #define SDMA3_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x13 9141 #define SDMA3_STATUS4_REG__IDLE_MASK 0x00000001L 9142 #define SDMA3_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L 9143 #define SDMA3_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L 9144 #define SDMA3_STATUS4_REG__MMHUB_RD_OUTSTANDING_MASK 0x00000010L 9145 #define SDMA3_STATUS4_REG__MMHUB_WR_OUTSTANDING_MASK 0x00000020L 9146 #define SDMA3_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000040L 9147 #define SDMA3_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000080L 9148 #define SDMA3_STATUS4_REG__REG_POLLING_MASK 0x00000100L 9149 #define SDMA3_STATUS4_REG__MEM_POLLING_MASK 0x00000200L 9150 #define SDMA3_STATUS4_REG__UTCL2_RD_XNACK_MASK 0x00000C00L 9151 #define SDMA3_STATUS4_REG__UTCL2_WR_XNACK_MASK 0x00003000L 9152 #define SDMA3_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x0003C000L 9153 #define SDMA3_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00040000L 9154 #define SDMA3_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00080000L 9155 //SDMA3_SCRATCH_RAM_DATA 9156 #define SDMA3_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 9157 #define SDMA3_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL 9158 //SDMA3_SCRATCH_RAM_ADDR 9159 #define SDMA3_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 9160 #define SDMA3_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL 9161 //SDMA3_CE_CTRL 9162 #define SDMA3_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 9163 #define SDMA3_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 9164 #define SDMA3_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5 9165 #define SDMA3_CE_CTRL__RESERVED__SHIFT 0x8 9166 #define SDMA3_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L 9167 #define SDMA3_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L 9168 #define SDMA3_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L 9169 #define SDMA3_CE_CTRL__RESERVED_MASK 0xFFFFFF00L 9170 //SDMA3_RAS_STATUS 9171 #define SDMA3_RAS_STATUS__RB_FETCH_ECC__SHIFT 0x0 9172 #define SDMA3_RAS_STATUS__IB_FETCH_ECC__SHIFT 0x1 9173 #define SDMA3_RAS_STATUS__F32_DATA_ECC__SHIFT 0x2 9174 #define SDMA3_RAS_STATUS__SEM_WPTR_ATOMIC_ECC__SHIFT 0x3 9175 #define SDMA3_RAS_STATUS__COPY_DATA_ECC__SHIFT 0x4 9176 #define SDMA3_RAS_STATUS__SRAM_ECC__SHIFT 0x5 9177 #define SDMA3_RAS_STATUS__RB_FETCH_NACK_GEN_ERR__SHIFT 0x8 9178 #define SDMA3_RAS_STATUS__IB_FETCH_NACK_GEN_ERR__SHIFT 0x9 9179 #define SDMA3_RAS_STATUS__F32_DATA_NACK_GEN_ERR__SHIFT 0xa 9180 #define SDMA3_RAS_STATUS__COPY_DATA_NACK_GEN_ERR__SHIFT 0xb 9181 #define SDMA3_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR__SHIFT 0xc 9182 #define SDMA3_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR__SHIFT 0xd 9183 #define SDMA3_RAS_STATUS__RB_FETCH_ECC_MASK 0x00000001L 9184 #define SDMA3_RAS_STATUS__IB_FETCH_ECC_MASK 0x00000002L 9185 #define SDMA3_RAS_STATUS__F32_DATA_ECC_MASK 0x00000004L 9186 #define SDMA3_RAS_STATUS__SEM_WPTR_ATOMIC_ECC_MASK 0x00000008L 9187 #define SDMA3_RAS_STATUS__COPY_DATA_ECC_MASK 0x00000010L 9188 #define SDMA3_RAS_STATUS__SRAM_ECC_MASK 0x00000020L 9189 #define SDMA3_RAS_STATUS__RB_FETCH_NACK_GEN_ERR_MASK 0x00000100L 9190 #define SDMA3_RAS_STATUS__IB_FETCH_NACK_GEN_ERR_MASK 0x00000200L 9191 #define SDMA3_RAS_STATUS__F32_DATA_NACK_GEN_ERR_MASK 0x00000400L 9192 #define SDMA3_RAS_STATUS__COPY_DATA_NACK_GEN_ERR_MASK 0x00000800L 9193 #define SDMA3_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR_MASK 0x00001000L 9194 #define SDMA3_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR_MASK 0x00002000L 9195 //SDMA3_CLK_STATUS 9196 #define SDMA3_CLK_STATUS__DYN_CLK__SHIFT 0x0 9197 #define SDMA3_CLK_STATUS__PTR_CLK__SHIFT 0x1 9198 #define SDMA3_CLK_STATUS__REG_CLK__SHIFT 0x2 9199 #define SDMA3_CLK_STATUS__F32_CLK__SHIFT 0x3 9200 #define SDMA3_CLK_STATUS__DYN_CLK_MASK 0x00000001L 9201 #define SDMA3_CLK_STATUS__PTR_CLK_MASK 0x00000002L 9202 #define SDMA3_CLK_STATUS__REG_CLK_MASK 0x00000004L 9203 #define SDMA3_CLK_STATUS__F32_CLK_MASK 0x00000008L 9204 //SDMA3_GFX_RB_CNTL 9205 #define SDMA3_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 9206 #define SDMA3_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 9207 #define SDMA3_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 9208 #define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 9209 #define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 9210 #define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 9211 #define SDMA3_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 9212 #define SDMA3_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 9213 #define SDMA3_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 9214 #define SDMA3_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL 9215 #define SDMA3_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 9216 #define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 9217 #define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 9218 #define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 9219 #define SDMA3_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 9220 #define SDMA3_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 9221 //SDMA3_GFX_RB_BASE 9222 #define SDMA3_GFX_RB_BASE__ADDR__SHIFT 0x0 9223 #define SDMA3_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 9224 //SDMA3_GFX_RB_BASE_HI 9225 #define SDMA3_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 9226 #define SDMA3_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 9227 //SDMA3_GFX_RB_RPTR 9228 #define SDMA3_GFX_RB_RPTR__OFFSET__SHIFT 0x0 9229 #define SDMA3_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 9230 //SDMA3_GFX_RB_RPTR_HI 9231 #define SDMA3_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 9232 #define SDMA3_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 9233 //SDMA3_GFX_RB_WPTR 9234 #define SDMA3_GFX_RB_WPTR__OFFSET__SHIFT 0x0 9235 #define SDMA3_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 9236 //SDMA3_GFX_RB_WPTR_HI 9237 #define SDMA3_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 9238 #define SDMA3_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 9239 //SDMA3_GFX_RB_WPTR_POLL_CNTL 9240 #define SDMA3_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 9241 #define SDMA3_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 9242 #define SDMA3_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 9243 #define SDMA3_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 9244 #define SDMA3_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 9245 #define SDMA3_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 9246 #define SDMA3_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 9247 #define SDMA3_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 9248 #define SDMA3_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 9249 #define SDMA3_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 9250 //SDMA3_GFX_RB_RPTR_ADDR_HI 9251 #define SDMA3_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 9252 #define SDMA3_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 9253 //SDMA3_GFX_RB_RPTR_ADDR_LO 9254 #define SDMA3_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 9255 #define SDMA3_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 9256 #define SDMA3_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 9257 #define SDMA3_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 9258 //SDMA3_GFX_IB_CNTL 9259 #define SDMA3_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 9260 #define SDMA3_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 9261 #define SDMA3_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 9262 #define SDMA3_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 9263 #define SDMA3_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 9264 #define SDMA3_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 9265 #define SDMA3_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 9266 #define SDMA3_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 9267 //SDMA3_GFX_IB_RPTR 9268 #define SDMA3_GFX_IB_RPTR__OFFSET__SHIFT 0x2 9269 #define SDMA3_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 9270 //SDMA3_GFX_IB_OFFSET 9271 #define SDMA3_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 9272 #define SDMA3_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 9273 //SDMA3_GFX_IB_BASE_LO 9274 #define SDMA3_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 9275 #define SDMA3_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 9276 //SDMA3_GFX_IB_BASE_HI 9277 #define SDMA3_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 9278 #define SDMA3_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 9279 //SDMA3_GFX_IB_SIZE 9280 #define SDMA3_GFX_IB_SIZE__SIZE__SHIFT 0x0 9281 #define SDMA3_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 9282 //SDMA3_GFX_SKIP_CNTL 9283 #define SDMA3_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 9284 #define SDMA3_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 9285 //SDMA3_GFX_CONTEXT_STATUS 9286 #define SDMA3_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 9287 #define SDMA3_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 9288 #define SDMA3_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 9289 #define SDMA3_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 9290 #define SDMA3_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 9291 #define SDMA3_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 9292 #define SDMA3_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 9293 #define SDMA3_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 9294 #define SDMA3_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 9295 #define SDMA3_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 9296 #define SDMA3_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 9297 #define SDMA3_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 9298 #define SDMA3_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 9299 #define SDMA3_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 9300 #define SDMA3_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 9301 #define SDMA3_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 9302 //SDMA3_GFX_DOORBELL 9303 #define SDMA3_GFX_DOORBELL__ENABLE__SHIFT 0x1c 9304 #define SDMA3_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 9305 #define SDMA3_GFX_DOORBELL__ENABLE_MASK 0x10000000L 9306 #define SDMA3_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 9307 //SDMA3_GFX_CONTEXT_CNTL 9308 #define SDMA3_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 9309 #define SDMA3_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 9310 #define SDMA3_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 9311 #define SDMA3_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0x0F000000L 9312 //SDMA3_GFX_STATUS 9313 #define SDMA3_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 9314 #define SDMA3_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 9315 #define SDMA3_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 9316 #define SDMA3_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 9317 //SDMA3_GFX_DOORBELL_LOG 9318 #define SDMA3_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 9319 #define SDMA3_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 9320 #define SDMA3_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 9321 #define SDMA3_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 9322 //SDMA3_GFX_WATERMARK 9323 #define SDMA3_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 9324 #define SDMA3_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 9325 #define SDMA3_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 9326 #define SDMA3_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 9327 //SDMA3_GFX_DOORBELL_OFFSET 9328 #define SDMA3_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 9329 #define SDMA3_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 9330 //SDMA3_GFX_CSA_ADDR_LO 9331 #define SDMA3_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 9332 #define SDMA3_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 9333 //SDMA3_GFX_CSA_ADDR_HI 9334 #define SDMA3_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 9335 #define SDMA3_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 9336 //SDMA3_GFX_IB_SUB_REMAIN 9337 #define SDMA3_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 9338 #define SDMA3_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 9339 //SDMA3_GFX_PREEMPT 9340 #define SDMA3_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 9341 #define SDMA3_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 9342 //SDMA3_GFX_DUMMY_REG 9343 #define SDMA3_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 9344 #define SDMA3_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 9345 //SDMA3_GFX_RB_WPTR_POLL_ADDR_HI 9346 #define SDMA3_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 9347 #define SDMA3_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 9348 //SDMA3_GFX_RB_WPTR_POLL_ADDR_LO 9349 #define SDMA3_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 9350 #define SDMA3_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 9351 //SDMA3_GFX_RB_AQL_CNTL 9352 #define SDMA3_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 9353 #define SDMA3_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 9354 #define SDMA3_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 9355 #define SDMA3_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 9356 #define SDMA3_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 9357 #define SDMA3_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 9358 //SDMA3_GFX_MINOR_PTR_UPDATE 9359 #define SDMA3_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 9360 #define SDMA3_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 9361 //SDMA3_GFX_MIDCMD_DATA0 9362 #define SDMA3_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 9363 #define SDMA3_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 9364 //SDMA3_GFX_MIDCMD_DATA1 9365 #define SDMA3_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 9366 #define SDMA3_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 9367 //SDMA3_GFX_MIDCMD_DATA2 9368 #define SDMA3_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 9369 #define SDMA3_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 9370 //SDMA3_GFX_MIDCMD_DATA3 9371 #define SDMA3_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 9372 #define SDMA3_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 9373 //SDMA3_GFX_MIDCMD_DATA4 9374 #define SDMA3_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 9375 #define SDMA3_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 9376 //SDMA3_GFX_MIDCMD_DATA5 9377 #define SDMA3_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 9378 #define SDMA3_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 9379 //SDMA3_GFX_MIDCMD_DATA6 9380 #define SDMA3_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 9381 #define SDMA3_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 9382 //SDMA3_GFX_MIDCMD_DATA7 9383 #define SDMA3_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 9384 #define SDMA3_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 9385 //SDMA3_GFX_MIDCMD_DATA8 9386 #define SDMA3_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 9387 #define SDMA3_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 9388 //SDMA3_GFX_MIDCMD_DATA9 9389 #define SDMA3_GFX_MIDCMD_DATA9__DATA9__SHIFT 0x0 9390 #define SDMA3_GFX_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 9391 //SDMA3_GFX_MIDCMD_DATA10 9392 #define SDMA3_GFX_MIDCMD_DATA10__DATA10__SHIFT 0x0 9393 #define SDMA3_GFX_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 9394 //SDMA3_GFX_MIDCMD_CNTL 9395 #define SDMA3_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 9396 #define SDMA3_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 9397 #define SDMA3_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 9398 #define SDMA3_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 9399 #define SDMA3_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 9400 #define SDMA3_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 9401 #define SDMA3_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 9402 #define SDMA3_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 9403 //SDMA3_PAGE_RB_CNTL 9404 #define SDMA3_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 9405 #define SDMA3_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 9406 #define SDMA3_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 9407 #define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 9408 #define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 9409 #define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 9410 #define SDMA3_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 9411 #define SDMA3_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 9412 #define SDMA3_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 9413 #define SDMA3_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL 9414 #define SDMA3_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 9415 #define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 9416 #define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 9417 #define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 9418 #define SDMA3_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 9419 #define SDMA3_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 9420 //SDMA3_PAGE_RB_BASE 9421 #define SDMA3_PAGE_RB_BASE__ADDR__SHIFT 0x0 9422 #define SDMA3_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 9423 //SDMA3_PAGE_RB_BASE_HI 9424 #define SDMA3_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 9425 #define SDMA3_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 9426 //SDMA3_PAGE_RB_RPTR 9427 #define SDMA3_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 9428 #define SDMA3_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 9429 //SDMA3_PAGE_RB_RPTR_HI 9430 #define SDMA3_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 9431 #define SDMA3_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 9432 //SDMA3_PAGE_RB_WPTR 9433 #define SDMA3_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 9434 #define SDMA3_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 9435 //SDMA3_PAGE_RB_WPTR_HI 9436 #define SDMA3_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 9437 #define SDMA3_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 9438 //SDMA3_PAGE_RB_WPTR_POLL_CNTL 9439 #define SDMA3_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 9440 #define SDMA3_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 9441 #define SDMA3_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 9442 #define SDMA3_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 9443 #define SDMA3_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 9444 #define SDMA3_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 9445 #define SDMA3_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 9446 #define SDMA3_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 9447 #define SDMA3_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 9448 #define SDMA3_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 9449 //SDMA3_PAGE_RB_RPTR_ADDR_HI 9450 #define SDMA3_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 9451 #define SDMA3_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 9452 //SDMA3_PAGE_RB_RPTR_ADDR_LO 9453 #define SDMA3_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 9454 #define SDMA3_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 9455 #define SDMA3_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 9456 #define SDMA3_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 9457 //SDMA3_PAGE_IB_CNTL 9458 #define SDMA3_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 9459 #define SDMA3_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 9460 #define SDMA3_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 9461 #define SDMA3_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 9462 #define SDMA3_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 9463 #define SDMA3_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 9464 #define SDMA3_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 9465 #define SDMA3_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 9466 //SDMA3_PAGE_IB_RPTR 9467 #define SDMA3_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 9468 #define SDMA3_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 9469 //SDMA3_PAGE_IB_OFFSET 9470 #define SDMA3_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 9471 #define SDMA3_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 9472 //SDMA3_PAGE_IB_BASE_LO 9473 #define SDMA3_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 9474 #define SDMA3_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 9475 //SDMA3_PAGE_IB_BASE_HI 9476 #define SDMA3_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 9477 #define SDMA3_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 9478 //SDMA3_PAGE_IB_SIZE 9479 #define SDMA3_PAGE_IB_SIZE__SIZE__SHIFT 0x0 9480 #define SDMA3_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 9481 //SDMA3_PAGE_SKIP_CNTL 9482 #define SDMA3_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 9483 #define SDMA3_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 9484 //SDMA3_PAGE_CONTEXT_STATUS 9485 #define SDMA3_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 9486 #define SDMA3_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 9487 #define SDMA3_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 9488 #define SDMA3_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 9489 #define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 9490 #define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 9491 #define SDMA3_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 9492 #define SDMA3_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 9493 #define SDMA3_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 9494 #define SDMA3_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 9495 #define SDMA3_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 9496 #define SDMA3_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 9497 #define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 9498 #define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 9499 #define SDMA3_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 9500 #define SDMA3_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 9501 //SDMA3_PAGE_DOORBELL 9502 #define SDMA3_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 9503 #define SDMA3_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 9504 #define SDMA3_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 9505 #define SDMA3_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 9506 //SDMA3_PAGE_STATUS 9507 #define SDMA3_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 9508 #define SDMA3_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 9509 #define SDMA3_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 9510 #define SDMA3_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 9511 //SDMA3_PAGE_DOORBELL_LOG 9512 #define SDMA3_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 9513 #define SDMA3_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 9514 #define SDMA3_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 9515 #define SDMA3_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 9516 //SDMA3_PAGE_WATERMARK 9517 #define SDMA3_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 9518 #define SDMA3_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 9519 #define SDMA3_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 9520 #define SDMA3_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 9521 //SDMA3_PAGE_DOORBELL_OFFSET 9522 #define SDMA3_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 9523 #define SDMA3_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 9524 //SDMA3_PAGE_CSA_ADDR_LO 9525 #define SDMA3_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 9526 #define SDMA3_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 9527 //SDMA3_PAGE_CSA_ADDR_HI 9528 #define SDMA3_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 9529 #define SDMA3_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 9530 //SDMA3_PAGE_IB_SUB_REMAIN 9531 #define SDMA3_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 9532 #define SDMA3_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 9533 //SDMA3_PAGE_PREEMPT 9534 #define SDMA3_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 9535 #define SDMA3_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 9536 //SDMA3_PAGE_DUMMY_REG 9537 #define SDMA3_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 9538 #define SDMA3_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 9539 //SDMA3_PAGE_RB_WPTR_POLL_ADDR_HI 9540 #define SDMA3_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 9541 #define SDMA3_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 9542 //SDMA3_PAGE_RB_WPTR_POLL_ADDR_LO 9543 #define SDMA3_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 9544 #define SDMA3_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 9545 //SDMA3_PAGE_RB_AQL_CNTL 9546 #define SDMA3_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 9547 #define SDMA3_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 9548 #define SDMA3_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 9549 #define SDMA3_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 9550 #define SDMA3_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 9551 #define SDMA3_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 9552 //SDMA3_PAGE_MINOR_PTR_UPDATE 9553 #define SDMA3_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 9554 #define SDMA3_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 9555 //SDMA3_PAGE_MIDCMD_DATA0 9556 #define SDMA3_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 9557 #define SDMA3_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 9558 //SDMA3_PAGE_MIDCMD_DATA1 9559 #define SDMA3_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 9560 #define SDMA3_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 9561 //SDMA3_PAGE_MIDCMD_DATA2 9562 #define SDMA3_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 9563 #define SDMA3_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 9564 //SDMA3_PAGE_MIDCMD_DATA3 9565 #define SDMA3_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 9566 #define SDMA3_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 9567 //SDMA3_PAGE_MIDCMD_DATA4 9568 #define SDMA3_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 9569 #define SDMA3_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 9570 //SDMA3_PAGE_MIDCMD_DATA5 9571 #define SDMA3_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 9572 #define SDMA3_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 9573 //SDMA3_PAGE_MIDCMD_DATA6 9574 #define SDMA3_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 9575 #define SDMA3_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 9576 //SDMA3_PAGE_MIDCMD_DATA7 9577 #define SDMA3_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 9578 #define SDMA3_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 9579 //SDMA3_PAGE_MIDCMD_DATA8 9580 #define SDMA3_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 9581 #define SDMA3_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 9582 //SDMA3_PAGE_MIDCMD_DATA9 9583 #define SDMA3_PAGE_MIDCMD_DATA9__DATA9__SHIFT 0x0 9584 #define SDMA3_PAGE_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 9585 //SDMA3_PAGE_MIDCMD_DATA10 9586 #define SDMA3_PAGE_MIDCMD_DATA10__DATA10__SHIFT 0x0 9587 #define SDMA3_PAGE_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 9588 //SDMA3_PAGE_MIDCMD_CNTL 9589 #define SDMA3_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 9590 #define SDMA3_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 9591 #define SDMA3_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 9592 #define SDMA3_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 9593 #define SDMA3_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 9594 #define SDMA3_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 9595 #define SDMA3_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 9596 #define SDMA3_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 9597 //SDMA3_RLC0_RB_CNTL 9598 #define SDMA3_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 9599 #define SDMA3_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 9600 #define SDMA3_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 9601 #define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 9602 #define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 9603 #define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 9604 #define SDMA3_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 9605 #define SDMA3_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 9606 #define SDMA3_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 9607 #define SDMA3_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL 9608 #define SDMA3_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 9609 #define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 9610 #define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 9611 #define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 9612 #define SDMA3_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 9613 #define SDMA3_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 9614 //SDMA3_RLC0_RB_BASE 9615 #define SDMA3_RLC0_RB_BASE__ADDR__SHIFT 0x0 9616 #define SDMA3_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 9617 //SDMA3_RLC0_RB_BASE_HI 9618 #define SDMA3_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 9619 #define SDMA3_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 9620 //SDMA3_RLC0_RB_RPTR 9621 #define SDMA3_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 9622 #define SDMA3_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 9623 //SDMA3_RLC0_RB_RPTR_HI 9624 #define SDMA3_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 9625 #define SDMA3_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 9626 //SDMA3_RLC0_RB_WPTR 9627 #define SDMA3_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 9628 #define SDMA3_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 9629 //SDMA3_RLC0_RB_WPTR_HI 9630 #define SDMA3_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 9631 #define SDMA3_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 9632 //SDMA3_RLC0_RB_WPTR_POLL_CNTL 9633 #define SDMA3_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 9634 #define SDMA3_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 9635 #define SDMA3_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 9636 #define SDMA3_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 9637 #define SDMA3_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 9638 #define SDMA3_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 9639 #define SDMA3_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 9640 #define SDMA3_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 9641 #define SDMA3_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 9642 #define SDMA3_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 9643 //SDMA3_RLC0_RB_RPTR_ADDR_HI 9644 #define SDMA3_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 9645 #define SDMA3_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 9646 //SDMA3_RLC0_RB_RPTR_ADDR_LO 9647 #define SDMA3_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 9648 #define SDMA3_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 9649 #define SDMA3_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 9650 #define SDMA3_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 9651 //SDMA3_RLC0_IB_CNTL 9652 #define SDMA3_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 9653 #define SDMA3_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 9654 #define SDMA3_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 9655 #define SDMA3_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 9656 #define SDMA3_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 9657 #define SDMA3_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 9658 #define SDMA3_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 9659 #define SDMA3_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 9660 //SDMA3_RLC0_IB_RPTR 9661 #define SDMA3_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 9662 #define SDMA3_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 9663 //SDMA3_RLC0_IB_OFFSET 9664 #define SDMA3_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 9665 #define SDMA3_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 9666 //SDMA3_RLC0_IB_BASE_LO 9667 #define SDMA3_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 9668 #define SDMA3_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 9669 //SDMA3_RLC0_IB_BASE_HI 9670 #define SDMA3_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 9671 #define SDMA3_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 9672 //SDMA3_RLC0_IB_SIZE 9673 #define SDMA3_RLC0_IB_SIZE__SIZE__SHIFT 0x0 9674 #define SDMA3_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 9675 //SDMA3_RLC0_SKIP_CNTL 9676 #define SDMA3_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 9677 #define SDMA3_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 9678 //SDMA3_RLC0_CONTEXT_STATUS 9679 #define SDMA3_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 9680 #define SDMA3_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 9681 #define SDMA3_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 9682 #define SDMA3_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 9683 #define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 9684 #define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 9685 #define SDMA3_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 9686 #define SDMA3_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 9687 #define SDMA3_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 9688 #define SDMA3_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 9689 #define SDMA3_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 9690 #define SDMA3_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 9691 #define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 9692 #define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 9693 #define SDMA3_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 9694 #define SDMA3_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 9695 //SDMA3_RLC0_DOORBELL 9696 #define SDMA3_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 9697 #define SDMA3_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 9698 #define SDMA3_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 9699 #define SDMA3_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 9700 //SDMA3_RLC0_STATUS 9701 #define SDMA3_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 9702 #define SDMA3_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 9703 #define SDMA3_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 9704 #define SDMA3_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 9705 //SDMA3_RLC0_DOORBELL_LOG 9706 #define SDMA3_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 9707 #define SDMA3_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 9708 #define SDMA3_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 9709 #define SDMA3_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 9710 //SDMA3_RLC0_WATERMARK 9711 #define SDMA3_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 9712 #define SDMA3_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 9713 #define SDMA3_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 9714 #define SDMA3_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 9715 //SDMA3_RLC0_DOORBELL_OFFSET 9716 #define SDMA3_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 9717 #define SDMA3_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 9718 //SDMA3_RLC0_CSA_ADDR_LO 9719 #define SDMA3_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 9720 #define SDMA3_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 9721 //SDMA3_RLC0_CSA_ADDR_HI 9722 #define SDMA3_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 9723 #define SDMA3_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 9724 //SDMA3_RLC0_IB_SUB_REMAIN 9725 #define SDMA3_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 9726 #define SDMA3_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 9727 //SDMA3_RLC0_PREEMPT 9728 #define SDMA3_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 9729 #define SDMA3_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 9730 //SDMA3_RLC0_DUMMY_REG 9731 #define SDMA3_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 9732 #define SDMA3_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 9733 //SDMA3_RLC0_RB_WPTR_POLL_ADDR_HI 9734 #define SDMA3_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 9735 #define SDMA3_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 9736 //SDMA3_RLC0_RB_WPTR_POLL_ADDR_LO 9737 #define SDMA3_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 9738 #define SDMA3_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 9739 //SDMA3_RLC0_RB_AQL_CNTL 9740 #define SDMA3_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 9741 #define SDMA3_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 9742 #define SDMA3_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 9743 #define SDMA3_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 9744 #define SDMA3_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 9745 #define SDMA3_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 9746 //SDMA3_RLC0_MINOR_PTR_UPDATE 9747 #define SDMA3_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 9748 #define SDMA3_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 9749 //SDMA3_RLC0_MIDCMD_DATA0 9750 #define SDMA3_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 9751 #define SDMA3_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 9752 //SDMA3_RLC0_MIDCMD_DATA1 9753 #define SDMA3_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 9754 #define SDMA3_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 9755 //SDMA3_RLC0_MIDCMD_DATA2 9756 #define SDMA3_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 9757 #define SDMA3_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 9758 //SDMA3_RLC0_MIDCMD_DATA3 9759 #define SDMA3_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 9760 #define SDMA3_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 9761 //SDMA3_RLC0_MIDCMD_DATA4 9762 #define SDMA3_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 9763 #define SDMA3_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 9764 //SDMA3_RLC0_MIDCMD_DATA5 9765 #define SDMA3_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 9766 #define SDMA3_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 9767 //SDMA3_RLC0_MIDCMD_DATA6 9768 #define SDMA3_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 9769 #define SDMA3_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 9770 //SDMA3_RLC0_MIDCMD_DATA7 9771 #define SDMA3_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 9772 #define SDMA3_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 9773 //SDMA3_RLC0_MIDCMD_DATA8 9774 #define SDMA3_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 9775 #define SDMA3_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 9776 //SDMA3_RLC0_MIDCMD_DATA9 9777 #define SDMA3_RLC0_MIDCMD_DATA9__DATA9__SHIFT 0x0 9778 #define SDMA3_RLC0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 9779 //SDMA3_RLC0_MIDCMD_DATA10 9780 #define SDMA3_RLC0_MIDCMD_DATA10__DATA10__SHIFT 0x0 9781 #define SDMA3_RLC0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 9782 //SDMA3_RLC0_MIDCMD_CNTL 9783 #define SDMA3_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 9784 #define SDMA3_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 9785 #define SDMA3_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 9786 #define SDMA3_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 9787 #define SDMA3_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 9788 #define SDMA3_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 9789 #define SDMA3_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 9790 #define SDMA3_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 9791 //SDMA3_RLC1_RB_CNTL 9792 #define SDMA3_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 9793 #define SDMA3_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 9794 #define SDMA3_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 9795 #define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 9796 #define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 9797 #define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 9798 #define SDMA3_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 9799 #define SDMA3_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 9800 #define SDMA3_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 9801 #define SDMA3_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL 9802 #define SDMA3_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 9803 #define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 9804 #define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 9805 #define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 9806 #define SDMA3_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 9807 #define SDMA3_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 9808 //SDMA3_RLC1_RB_BASE 9809 #define SDMA3_RLC1_RB_BASE__ADDR__SHIFT 0x0 9810 #define SDMA3_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 9811 //SDMA3_RLC1_RB_BASE_HI 9812 #define SDMA3_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 9813 #define SDMA3_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 9814 //SDMA3_RLC1_RB_RPTR 9815 #define SDMA3_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 9816 #define SDMA3_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 9817 //SDMA3_RLC1_RB_RPTR_HI 9818 #define SDMA3_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 9819 #define SDMA3_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 9820 //SDMA3_RLC1_RB_WPTR 9821 #define SDMA3_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 9822 #define SDMA3_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 9823 //SDMA3_RLC1_RB_WPTR_HI 9824 #define SDMA3_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 9825 #define SDMA3_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 9826 //SDMA3_RLC1_RB_WPTR_POLL_CNTL 9827 #define SDMA3_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 9828 #define SDMA3_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 9829 #define SDMA3_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 9830 #define SDMA3_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 9831 #define SDMA3_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 9832 #define SDMA3_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 9833 #define SDMA3_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 9834 #define SDMA3_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 9835 #define SDMA3_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 9836 #define SDMA3_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 9837 //SDMA3_RLC1_RB_RPTR_ADDR_HI 9838 #define SDMA3_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 9839 #define SDMA3_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 9840 //SDMA3_RLC1_RB_RPTR_ADDR_LO 9841 #define SDMA3_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 9842 #define SDMA3_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 9843 #define SDMA3_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 9844 #define SDMA3_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 9845 //SDMA3_RLC1_IB_CNTL 9846 #define SDMA3_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 9847 #define SDMA3_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 9848 #define SDMA3_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 9849 #define SDMA3_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 9850 #define SDMA3_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 9851 #define SDMA3_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 9852 #define SDMA3_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 9853 #define SDMA3_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 9854 //SDMA3_RLC1_IB_RPTR 9855 #define SDMA3_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 9856 #define SDMA3_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 9857 //SDMA3_RLC1_IB_OFFSET 9858 #define SDMA3_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 9859 #define SDMA3_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 9860 //SDMA3_RLC1_IB_BASE_LO 9861 #define SDMA3_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 9862 #define SDMA3_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 9863 //SDMA3_RLC1_IB_BASE_HI 9864 #define SDMA3_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 9865 #define SDMA3_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 9866 //SDMA3_RLC1_IB_SIZE 9867 #define SDMA3_RLC1_IB_SIZE__SIZE__SHIFT 0x0 9868 #define SDMA3_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 9869 //SDMA3_RLC1_SKIP_CNTL 9870 #define SDMA3_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 9871 #define SDMA3_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 9872 //SDMA3_RLC1_CONTEXT_STATUS 9873 #define SDMA3_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 9874 #define SDMA3_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 9875 #define SDMA3_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 9876 #define SDMA3_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 9877 #define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 9878 #define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 9879 #define SDMA3_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 9880 #define SDMA3_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 9881 #define SDMA3_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 9882 #define SDMA3_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 9883 #define SDMA3_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 9884 #define SDMA3_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 9885 #define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 9886 #define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 9887 #define SDMA3_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 9888 #define SDMA3_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 9889 //SDMA3_RLC1_DOORBELL 9890 #define SDMA3_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 9891 #define SDMA3_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 9892 #define SDMA3_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 9893 #define SDMA3_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 9894 //SDMA3_RLC1_STATUS 9895 #define SDMA3_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 9896 #define SDMA3_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 9897 #define SDMA3_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 9898 #define SDMA3_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 9899 //SDMA3_RLC1_DOORBELL_LOG 9900 #define SDMA3_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 9901 #define SDMA3_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 9902 #define SDMA3_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 9903 #define SDMA3_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 9904 //SDMA3_RLC1_WATERMARK 9905 #define SDMA3_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 9906 #define SDMA3_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 9907 #define SDMA3_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 9908 #define SDMA3_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 9909 //SDMA3_RLC1_DOORBELL_OFFSET 9910 #define SDMA3_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 9911 #define SDMA3_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 9912 //SDMA3_RLC1_CSA_ADDR_LO 9913 #define SDMA3_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 9914 #define SDMA3_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 9915 //SDMA3_RLC1_CSA_ADDR_HI 9916 #define SDMA3_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 9917 #define SDMA3_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 9918 //SDMA3_RLC1_IB_SUB_REMAIN 9919 #define SDMA3_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 9920 #define SDMA3_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 9921 //SDMA3_RLC1_PREEMPT 9922 #define SDMA3_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 9923 #define SDMA3_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 9924 //SDMA3_RLC1_DUMMY_REG 9925 #define SDMA3_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 9926 #define SDMA3_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 9927 //SDMA3_RLC1_RB_WPTR_POLL_ADDR_HI 9928 #define SDMA3_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 9929 #define SDMA3_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 9930 //SDMA3_RLC1_RB_WPTR_POLL_ADDR_LO 9931 #define SDMA3_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 9932 #define SDMA3_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 9933 //SDMA3_RLC1_RB_AQL_CNTL 9934 #define SDMA3_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 9935 #define SDMA3_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 9936 #define SDMA3_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 9937 #define SDMA3_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 9938 #define SDMA3_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 9939 #define SDMA3_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 9940 //SDMA3_RLC1_MINOR_PTR_UPDATE 9941 #define SDMA3_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 9942 #define SDMA3_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 9943 //SDMA3_RLC1_MIDCMD_DATA0 9944 #define SDMA3_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 9945 #define SDMA3_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 9946 //SDMA3_RLC1_MIDCMD_DATA1 9947 #define SDMA3_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 9948 #define SDMA3_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 9949 //SDMA3_RLC1_MIDCMD_DATA2 9950 #define SDMA3_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 9951 #define SDMA3_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 9952 //SDMA3_RLC1_MIDCMD_DATA3 9953 #define SDMA3_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 9954 #define SDMA3_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 9955 //SDMA3_RLC1_MIDCMD_DATA4 9956 #define SDMA3_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 9957 #define SDMA3_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 9958 //SDMA3_RLC1_MIDCMD_DATA5 9959 #define SDMA3_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 9960 #define SDMA3_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 9961 //SDMA3_RLC1_MIDCMD_DATA6 9962 #define SDMA3_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 9963 #define SDMA3_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 9964 //SDMA3_RLC1_MIDCMD_DATA7 9965 #define SDMA3_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 9966 #define SDMA3_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 9967 //SDMA3_RLC1_MIDCMD_DATA8 9968 #define SDMA3_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 9969 #define SDMA3_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 9970 //SDMA3_RLC1_MIDCMD_DATA9 9971 #define SDMA3_RLC1_MIDCMD_DATA9__DATA9__SHIFT 0x0 9972 #define SDMA3_RLC1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 9973 //SDMA3_RLC1_MIDCMD_DATA10 9974 #define SDMA3_RLC1_MIDCMD_DATA10__DATA10__SHIFT 0x0 9975 #define SDMA3_RLC1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 9976 //SDMA3_RLC1_MIDCMD_CNTL 9977 #define SDMA3_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 9978 #define SDMA3_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 9979 #define SDMA3_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 9980 #define SDMA3_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 9981 #define SDMA3_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 9982 #define SDMA3_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 9983 #define SDMA3_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 9984 #define SDMA3_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 9985 //SDMA3_RLC2_RB_CNTL 9986 #define SDMA3_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 9987 #define SDMA3_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 9988 #define SDMA3_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 9989 #define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 9990 #define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 9991 #define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 9992 #define SDMA3_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 9993 #define SDMA3_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 9994 #define SDMA3_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L 9995 #define SDMA3_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL 9996 #define SDMA3_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 9997 #define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 9998 #define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 9999 #define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 10000 #define SDMA3_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L 10001 #define SDMA3_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L 10002 //SDMA3_RLC2_RB_BASE 10003 #define SDMA3_RLC2_RB_BASE__ADDR__SHIFT 0x0 10004 #define SDMA3_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL 10005 //SDMA3_RLC2_RB_BASE_HI 10006 #define SDMA3_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 10007 #define SDMA3_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 10008 //SDMA3_RLC2_RB_RPTR 10009 #define SDMA3_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 10010 #define SDMA3_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 10011 //SDMA3_RLC2_RB_RPTR_HI 10012 #define SDMA3_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 10013 #define SDMA3_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 10014 //SDMA3_RLC2_RB_WPTR 10015 #define SDMA3_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 10016 #define SDMA3_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 10017 //SDMA3_RLC2_RB_WPTR_HI 10018 #define SDMA3_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 10019 #define SDMA3_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 10020 //SDMA3_RLC2_RB_WPTR_POLL_CNTL 10021 #define SDMA3_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 10022 #define SDMA3_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 10023 #define SDMA3_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 10024 #define SDMA3_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 10025 #define SDMA3_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 10026 #define SDMA3_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 10027 #define SDMA3_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 10028 #define SDMA3_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 10029 #define SDMA3_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 10030 #define SDMA3_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 10031 //SDMA3_RLC2_RB_RPTR_ADDR_HI 10032 #define SDMA3_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 10033 #define SDMA3_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 10034 //SDMA3_RLC2_RB_RPTR_ADDR_LO 10035 #define SDMA3_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 10036 #define SDMA3_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 10037 #define SDMA3_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 10038 #define SDMA3_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 10039 //SDMA3_RLC2_IB_CNTL 10040 #define SDMA3_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 10041 #define SDMA3_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 10042 #define SDMA3_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 10043 #define SDMA3_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 10044 #define SDMA3_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L 10045 #define SDMA3_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 10046 #define SDMA3_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 10047 #define SDMA3_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L 10048 //SDMA3_RLC2_IB_RPTR 10049 #define SDMA3_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 10050 #define SDMA3_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL 10051 //SDMA3_RLC2_IB_OFFSET 10052 #define SDMA3_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 10053 #define SDMA3_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 10054 //SDMA3_RLC2_IB_BASE_LO 10055 #define SDMA3_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 10056 #define SDMA3_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 10057 //SDMA3_RLC2_IB_BASE_HI 10058 #define SDMA3_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 10059 #define SDMA3_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 10060 //SDMA3_RLC2_IB_SIZE 10061 #define SDMA3_RLC2_IB_SIZE__SIZE__SHIFT 0x0 10062 #define SDMA3_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL 10063 //SDMA3_RLC2_SKIP_CNTL 10064 #define SDMA3_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 10065 #define SDMA3_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 10066 //SDMA3_RLC2_CONTEXT_STATUS 10067 #define SDMA3_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 10068 #define SDMA3_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 10069 #define SDMA3_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 10070 #define SDMA3_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 10071 #define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 10072 #define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 10073 #define SDMA3_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 10074 #define SDMA3_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 10075 #define SDMA3_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 10076 #define SDMA3_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L 10077 #define SDMA3_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 10078 #define SDMA3_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 10079 #define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 10080 #define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 10081 #define SDMA3_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 10082 #define SDMA3_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 10083 //SDMA3_RLC2_DOORBELL 10084 #define SDMA3_RLC2_DOORBELL__ENABLE__SHIFT 0x1c 10085 #define SDMA3_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e 10086 #define SDMA3_RLC2_DOORBELL__ENABLE_MASK 0x10000000L 10087 #define SDMA3_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L 10088 //SDMA3_RLC2_STATUS 10089 #define SDMA3_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 10090 #define SDMA3_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 10091 #define SDMA3_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 10092 #define SDMA3_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 10093 //SDMA3_RLC2_DOORBELL_LOG 10094 #define SDMA3_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 10095 #define SDMA3_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 10096 #define SDMA3_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 10097 #define SDMA3_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 10098 //SDMA3_RLC2_WATERMARK 10099 #define SDMA3_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 10100 #define SDMA3_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 10101 #define SDMA3_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 10102 #define SDMA3_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 10103 //SDMA3_RLC2_DOORBELL_OFFSET 10104 #define SDMA3_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 10105 #define SDMA3_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 10106 //SDMA3_RLC2_CSA_ADDR_LO 10107 #define SDMA3_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 10108 #define SDMA3_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 10109 //SDMA3_RLC2_CSA_ADDR_HI 10110 #define SDMA3_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 10111 #define SDMA3_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 10112 //SDMA3_RLC2_IB_SUB_REMAIN 10113 #define SDMA3_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 10114 #define SDMA3_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 10115 //SDMA3_RLC2_PREEMPT 10116 #define SDMA3_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 10117 #define SDMA3_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L 10118 //SDMA3_RLC2_DUMMY_REG 10119 #define SDMA3_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 10120 #define SDMA3_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 10121 //SDMA3_RLC2_RB_WPTR_POLL_ADDR_HI 10122 #define SDMA3_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 10123 #define SDMA3_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 10124 //SDMA3_RLC2_RB_WPTR_POLL_ADDR_LO 10125 #define SDMA3_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 10126 #define SDMA3_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 10127 //SDMA3_RLC2_RB_AQL_CNTL 10128 #define SDMA3_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 10129 #define SDMA3_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 10130 #define SDMA3_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 10131 #define SDMA3_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 10132 #define SDMA3_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 10133 #define SDMA3_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 10134 //SDMA3_RLC2_MINOR_PTR_UPDATE 10135 #define SDMA3_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 10136 #define SDMA3_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 10137 //SDMA3_RLC2_MIDCMD_DATA0 10138 #define SDMA3_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 10139 #define SDMA3_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 10140 //SDMA3_RLC2_MIDCMD_DATA1 10141 #define SDMA3_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 10142 #define SDMA3_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 10143 //SDMA3_RLC2_MIDCMD_DATA2 10144 #define SDMA3_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 10145 #define SDMA3_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 10146 //SDMA3_RLC2_MIDCMD_DATA3 10147 #define SDMA3_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 10148 #define SDMA3_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 10149 //SDMA3_RLC2_MIDCMD_DATA4 10150 #define SDMA3_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 10151 #define SDMA3_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 10152 //SDMA3_RLC2_MIDCMD_DATA5 10153 #define SDMA3_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 10154 #define SDMA3_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 10155 //SDMA3_RLC2_MIDCMD_DATA6 10156 #define SDMA3_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 10157 #define SDMA3_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 10158 //SDMA3_RLC2_MIDCMD_DATA7 10159 #define SDMA3_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 10160 #define SDMA3_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 10161 //SDMA3_RLC2_MIDCMD_DATA8 10162 #define SDMA3_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 10163 #define SDMA3_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 10164 //SDMA3_RLC2_MIDCMD_DATA9 10165 #define SDMA3_RLC2_MIDCMD_DATA9__DATA9__SHIFT 0x0 10166 #define SDMA3_RLC2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 10167 //SDMA3_RLC2_MIDCMD_DATA10 10168 #define SDMA3_RLC2_MIDCMD_DATA10__DATA10__SHIFT 0x0 10169 #define SDMA3_RLC2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 10170 //SDMA3_RLC2_MIDCMD_CNTL 10171 #define SDMA3_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 10172 #define SDMA3_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 10173 #define SDMA3_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 10174 #define SDMA3_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 10175 #define SDMA3_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 10176 #define SDMA3_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 10177 #define SDMA3_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 10178 #define SDMA3_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 10179 //SDMA3_RLC3_RB_CNTL 10180 #define SDMA3_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 10181 #define SDMA3_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 10182 #define SDMA3_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 10183 #define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 10184 #define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 10185 #define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 10186 #define SDMA3_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 10187 #define SDMA3_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 10188 #define SDMA3_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L 10189 #define SDMA3_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL 10190 #define SDMA3_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 10191 #define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 10192 #define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 10193 #define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 10194 #define SDMA3_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L 10195 #define SDMA3_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L 10196 //SDMA3_RLC3_RB_BASE 10197 #define SDMA3_RLC3_RB_BASE__ADDR__SHIFT 0x0 10198 #define SDMA3_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL 10199 //SDMA3_RLC3_RB_BASE_HI 10200 #define SDMA3_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 10201 #define SDMA3_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 10202 //SDMA3_RLC3_RB_RPTR 10203 #define SDMA3_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 10204 #define SDMA3_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 10205 //SDMA3_RLC3_RB_RPTR_HI 10206 #define SDMA3_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 10207 #define SDMA3_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 10208 //SDMA3_RLC3_RB_WPTR 10209 #define SDMA3_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 10210 #define SDMA3_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 10211 //SDMA3_RLC3_RB_WPTR_HI 10212 #define SDMA3_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 10213 #define SDMA3_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 10214 //SDMA3_RLC3_RB_WPTR_POLL_CNTL 10215 #define SDMA3_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 10216 #define SDMA3_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 10217 #define SDMA3_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 10218 #define SDMA3_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 10219 #define SDMA3_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 10220 #define SDMA3_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 10221 #define SDMA3_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 10222 #define SDMA3_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 10223 #define SDMA3_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 10224 #define SDMA3_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 10225 //SDMA3_RLC3_RB_RPTR_ADDR_HI 10226 #define SDMA3_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 10227 #define SDMA3_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 10228 //SDMA3_RLC3_RB_RPTR_ADDR_LO 10229 #define SDMA3_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 10230 #define SDMA3_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 10231 #define SDMA3_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 10232 #define SDMA3_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 10233 //SDMA3_RLC3_IB_CNTL 10234 #define SDMA3_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 10235 #define SDMA3_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 10236 #define SDMA3_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 10237 #define SDMA3_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 10238 #define SDMA3_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L 10239 #define SDMA3_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 10240 #define SDMA3_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 10241 #define SDMA3_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L 10242 //SDMA3_RLC3_IB_RPTR 10243 #define SDMA3_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 10244 #define SDMA3_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL 10245 //SDMA3_RLC3_IB_OFFSET 10246 #define SDMA3_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 10247 #define SDMA3_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 10248 //SDMA3_RLC3_IB_BASE_LO 10249 #define SDMA3_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 10250 #define SDMA3_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 10251 //SDMA3_RLC3_IB_BASE_HI 10252 #define SDMA3_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 10253 #define SDMA3_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 10254 //SDMA3_RLC3_IB_SIZE 10255 #define SDMA3_RLC3_IB_SIZE__SIZE__SHIFT 0x0 10256 #define SDMA3_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL 10257 //SDMA3_RLC3_SKIP_CNTL 10258 #define SDMA3_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 10259 #define SDMA3_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 10260 //SDMA3_RLC3_CONTEXT_STATUS 10261 #define SDMA3_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 10262 #define SDMA3_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 10263 #define SDMA3_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 10264 #define SDMA3_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 10265 #define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 10266 #define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 10267 #define SDMA3_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 10268 #define SDMA3_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 10269 #define SDMA3_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 10270 #define SDMA3_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L 10271 #define SDMA3_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 10272 #define SDMA3_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 10273 #define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 10274 #define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 10275 #define SDMA3_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 10276 #define SDMA3_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 10277 //SDMA3_RLC3_DOORBELL 10278 #define SDMA3_RLC3_DOORBELL__ENABLE__SHIFT 0x1c 10279 #define SDMA3_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e 10280 #define SDMA3_RLC3_DOORBELL__ENABLE_MASK 0x10000000L 10281 #define SDMA3_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L 10282 //SDMA3_RLC3_STATUS 10283 #define SDMA3_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 10284 #define SDMA3_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 10285 #define SDMA3_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 10286 #define SDMA3_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 10287 //SDMA3_RLC3_DOORBELL_LOG 10288 #define SDMA3_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 10289 #define SDMA3_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 10290 #define SDMA3_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 10291 #define SDMA3_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 10292 //SDMA3_RLC3_WATERMARK 10293 #define SDMA3_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 10294 #define SDMA3_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 10295 #define SDMA3_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 10296 #define SDMA3_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 10297 //SDMA3_RLC3_DOORBELL_OFFSET 10298 #define SDMA3_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 10299 #define SDMA3_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 10300 //SDMA3_RLC3_CSA_ADDR_LO 10301 #define SDMA3_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 10302 #define SDMA3_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 10303 //SDMA3_RLC3_CSA_ADDR_HI 10304 #define SDMA3_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 10305 #define SDMA3_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 10306 //SDMA3_RLC3_IB_SUB_REMAIN 10307 #define SDMA3_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 10308 #define SDMA3_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 10309 //SDMA3_RLC3_PREEMPT 10310 #define SDMA3_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 10311 #define SDMA3_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L 10312 //SDMA3_RLC3_DUMMY_REG 10313 #define SDMA3_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 10314 #define SDMA3_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 10315 //SDMA3_RLC3_RB_WPTR_POLL_ADDR_HI 10316 #define SDMA3_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 10317 #define SDMA3_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 10318 //SDMA3_RLC3_RB_WPTR_POLL_ADDR_LO 10319 #define SDMA3_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 10320 #define SDMA3_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 10321 //SDMA3_RLC3_RB_AQL_CNTL 10322 #define SDMA3_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 10323 #define SDMA3_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 10324 #define SDMA3_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 10325 #define SDMA3_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 10326 #define SDMA3_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 10327 #define SDMA3_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 10328 //SDMA3_RLC3_MINOR_PTR_UPDATE 10329 #define SDMA3_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 10330 #define SDMA3_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 10331 //SDMA3_RLC3_MIDCMD_DATA0 10332 #define SDMA3_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 10333 #define SDMA3_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 10334 //SDMA3_RLC3_MIDCMD_DATA1 10335 #define SDMA3_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 10336 #define SDMA3_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 10337 //SDMA3_RLC3_MIDCMD_DATA2 10338 #define SDMA3_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 10339 #define SDMA3_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 10340 //SDMA3_RLC3_MIDCMD_DATA3 10341 #define SDMA3_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 10342 #define SDMA3_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 10343 //SDMA3_RLC3_MIDCMD_DATA4 10344 #define SDMA3_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 10345 #define SDMA3_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 10346 //SDMA3_RLC3_MIDCMD_DATA5 10347 #define SDMA3_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 10348 #define SDMA3_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 10349 //SDMA3_RLC3_MIDCMD_DATA6 10350 #define SDMA3_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 10351 #define SDMA3_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 10352 //SDMA3_RLC3_MIDCMD_DATA7 10353 #define SDMA3_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 10354 #define SDMA3_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 10355 //SDMA3_RLC3_MIDCMD_DATA8 10356 #define SDMA3_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 10357 #define SDMA3_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 10358 //SDMA3_RLC3_MIDCMD_DATA9 10359 #define SDMA3_RLC3_MIDCMD_DATA9__DATA9__SHIFT 0x0 10360 #define SDMA3_RLC3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 10361 //SDMA3_RLC3_MIDCMD_DATA10 10362 #define SDMA3_RLC3_MIDCMD_DATA10__DATA10__SHIFT 0x0 10363 #define SDMA3_RLC3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 10364 //SDMA3_RLC3_MIDCMD_CNTL 10365 #define SDMA3_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 10366 #define SDMA3_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 10367 #define SDMA3_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 10368 #define SDMA3_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 10369 #define SDMA3_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 10370 #define SDMA3_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 10371 #define SDMA3_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 10372 #define SDMA3_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 10373 //SDMA3_RLC4_RB_CNTL 10374 #define SDMA3_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 10375 #define SDMA3_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 10376 #define SDMA3_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 10377 #define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 10378 #define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 10379 #define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 10380 #define SDMA3_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 10381 #define SDMA3_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 10382 #define SDMA3_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L 10383 #define SDMA3_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL 10384 #define SDMA3_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 10385 #define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 10386 #define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 10387 #define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 10388 #define SDMA3_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L 10389 #define SDMA3_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L 10390 //SDMA3_RLC4_RB_BASE 10391 #define SDMA3_RLC4_RB_BASE__ADDR__SHIFT 0x0 10392 #define SDMA3_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL 10393 //SDMA3_RLC4_RB_BASE_HI 10394 #define SDMA3_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 10395 #define SDMA3_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 10396 //SDMA3_RLC4_RB_RPTR 10397 #define SDMA3_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 10398 #define SDMA3_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 10399 //SDMA3_RLC4_RB_RPTR_HI 10400 #define SDMA3_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 10401 #define SDMA3_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 10402 //SDMA3_RLC4_RB_WPTR 10403 #define SDMA3_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 10404 #define SDMA3_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 10405 //SDMA3_RLC4_RB_WPTR_HI 10406 #define SDMA3_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 10407 #define SDMA3_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 10408 //SDMA3_RLC4_RB_WPTR_POLL_CNTL 10409 #define SDMA3_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 10410 #define SDMA3_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 10411 #define SDMA3_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 10412 #define SDMA3_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 10413 #define SDMA3_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 10414 #define SDMA3_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 10415 #define SDMA3_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 10416 #define SDMA3_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 10417 #define SDMA3_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 10418 #define SDMA3_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 10419 //SDMA3_RLC4_RB_RPTR_ADDR_HI 10420 #define SDMA3_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 10421 #define SDMA3_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 10422 //SDMA3_RLC4_RB_RPTR_ADDR_LO 10423 #define SDMA3_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 10424 #define SDMA3_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 10425 #define SDMA3_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 10426 #define SDMA3_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 10427 //SDMA3_RLC4_IB_CNTL 10428 #define SDMA3_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 10429 #define SDMA3_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 10430 #define SDMA3_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 10431 #define SDMA3_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 10432 #define SDMA3_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L 10433 #define SDMA3_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 10434 #define SDMA3_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 10435 #define SDMA3_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L 10436 //SDMA3_RLC4_IB_RPTR 10437 #define SDMA3_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 10438 #define SDMA3_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL 10439 //SDMA3_RLC4_IB_OFFSET 10440 #define SDMA3_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 10441 #define SDMA3_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 10442 //SDMA3_RLC4_IB_BASE_LO 10443 #define SDMA3_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 10444 #define SDMA3_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 10445 //SDMA3_RLC4_IB_BASE_HI 10446 #define SDMA3_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 10447 #define SDMA3_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 10448 //SDMA3_RLC4_IB_SIZE 10449 #define SDMA3_RLC4_IB_SIZE__SIZE__SHIFT 0x0 10450 #define SDMA3_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL 10451 //SDMA3_RLC4_SKIP_CNTL 10452 #define SDMA3_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 10453 #define SDMA3_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 10454 //SDMA3_RLC4_CONTEXT_STATUS 10455 #define SDMA3_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 10456 #define SDMA3_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 10457 #define SDMA3_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 10458 #define SDMA3_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 10459 #define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 10460 #define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 10461 #define SDMA3_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 10462 #define SDMA3_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 10463 #define SDMA3_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 10464 #define SDMA3_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L 10465 #define SDMA3_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 10466 #define SDMA3_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 10467 #define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 10468 #define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 10469 #define SDMA3_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 10470 #define SDMA3_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 10471 //SDMA3_RLC4_DOORBELL 10472 #define SDMA3_RLC4_DOORBELL__ENABLE__SHIFT 0x1c 10473 #define SDMA3_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e 10474 #define SDMA3_RLC4_DOORBELL__ENABLE_MASK 0x10000000L 10475 #define SDMA3_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L 10476 //SDMA3_RLC4_STATUS 10477 #define SDMA3_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 10478 #define SDMA3_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 10479 #define SDMA3_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 10480 #define SDMA3_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 10481 //SDMA3_RLC4_DOORBELL_LOG 10482 #define SDMA3_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 10483 #define SDMA3_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 10484 #define SDMA3_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 10485 #define SDMA3_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 10486 //SDMA3_RLC4_WATERMARK 10487 #define SDMA3_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 10488 #define SDMA3_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 10489 #define SDMA3_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 10490 #define SDMA3_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 10491 //SDMA3_RLC4_DOORBELL_OFFSET 10492 #define SDMA3_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 10493 #define SDMA3_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 10494 //SDMA3_RLC4_CSA_ADDR_LO 10495 #define SDMA3_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 10496 #define SDMA3_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 10497 //SDMA3_RLC4_CSA_ADDR_HI 10498 #define SDMA3_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 10499 #define SDMA3_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 10500 //SDMA3_RLC4_IB_SUB_REMAIN 10501 #define SDMA3_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 10502 #define SDMA3_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 10503 //SDMA3_RLC4_PREEMPT 10504 #define SDMA3_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 10505 #define SDMA3_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L 10506 //SDMA3_RLC4_DUMMY_REG 10507 #define SDMA3_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 10508 #define SDMA3_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 10509 //SDMA3_RLC4_RB_WPTR_POLL_ADDR_HI 10510 #define SDMA3_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 10511 #define SDMA3_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 10512 //SDMA3_RLC4_RB_WPTR_POLL_ADDR_LO 10513 #define SDMA3_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 10514 #define SDMA3_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 10515 //SDMA3_RLC4_RB_AQL_CNTL 10516 #define SDMA3_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 10517 #define SDMA3_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 10518 #define SDMA3_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 10519 #define SDMA3_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 10520 #define SDMA3_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 10521 #define SDMA3_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 10522 //SDMA3_RLC4_MINOR_PTR_UPDATE 10523 #define SDMA3_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 10524 #define SDMA3_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 10525 //SDMA3_RLC4_MIDCMD_DATA0 10526 #define SDMA3_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 10527 #define SDMA3_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 10528 //SDMA3_RLC4_MIDCMD_DATA1 10529 #define SDMA3_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 10530 #define SDMA3_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 10531 //SDMA3_RLC4_MIDCMD_DATA2 10532 #define SDMA3_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 10533 #define SDMA3_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 10534 //SDMA3_RLC4_MIDCMD_DATA3 10535 #define SDMA3_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 10536 #define SDMA3_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 10537 //SDMA3_RLC4_MIDCMD_DATA4 10538 #define SDMA3_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 10539 #define SDMA3_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 10540 //SDMA3_RLC4_MIDCMD_DATA5 10541 #define SDMA3_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 10542 #define SDMA3_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 10543 //SDMA3_RLC4_MIDCMD_DATA6 10544 #define SDMA3_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 10545 #define SDMA3_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 10546 //SDMA3_RLC4_MIDCMD_DATA7 10547 #define SDMA3_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 10548 #define SDMA3_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 10549 //SDMA3_RLC4_MIDCMD_DATA8 10550 #define SDMA3_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 10551 #define SDMA3_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 10552 //SDMA3_RLC4_MIDCMD_DATA9 10553 #define SDMA3_RLC4_MIDCMD_DATA9__DATA9__SHIFT 0x0 10554 #define SDMA3_RLC4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 10555 //SDMA3_RLC4_MIDCMD_DATA10 10556 #define SDMA3_RLC4_MIDCMD_DATA10__DATA10__SHIFT 0x0 10557 #define SDMA3_RLC4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 10558 //SDMA3_RLC4_MIDCMD_CNTL 10559 #define SDMA3_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 10560 #define SDMA3_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 10561 #define SDMA3_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 10562 #define SDMA3_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 10563 #define SDMA3_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 10564 #define SDMA3_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 10565 #define SDMA3_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 10566 #define SDMA3_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 10567 //SDMA3_RLC5_RB_CNTL 10568 #define SDMA3_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 10569 #define SDMA3_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 10570 #define SDMA3_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 10571 #define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 10572 #define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 10573 #define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 10574 #define SDMA3_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 10575 #define SDMA3_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 10576 #define SDMA3_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L 10577 #define SDMA3_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL 10578 #define SDMA3_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 10579 #define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 10580 #define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 10581 #define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 10582 #define SDMA3_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L 10583 #define SDMA3_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L 10584 //SDMA3_RLC5_RB_BASE 10585 #define SDMA3_RLC5_RB_BASE__ADDR__SHIFT 0x0 10586 #define SDMA3_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL 10587 //SDMA3_RLC5_RB_BASE_HI 10588 #define SDMA3_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 10589 #define SDMA3_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 10590 //SDMA3_RLC5_RB_RPTR 10591 #define SDMA3_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 10592 #define SDMA3_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 10593 //SDMA3_RLC5_RB_RPTR_HI 10594 #define SDMA3_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 10595 #define SDMA3_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 10596 //SDMA3_RLC5_RB_WPTR 10597 #define SDMA3_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 10598 #define SDMA3_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 10599 //SDMA3_RLC5_RB_WPTR_HI 10600 #define SDMA3_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 10601 #define SDMA3_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 10602 //SDMA3_RLC5_RB_WPTR_POLL_CNTL 10603 #define SDMA3_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 10604 #define SDMA3_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 10605 #define SDMA3_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 10606 #define SDMA3_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 10607 #define SDMA3_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 10608 #define SDMA3_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 10609 #define SDMA3_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 10610 #define SDMA3_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 10611 #define SDMA3_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 10612 #define SDMA3_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 10613 //SDMA3_RLC5_RB_RPTR_ADDR_HI 10614 #define SDMA3_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 10615 #define SDMA3_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 10616 //SDMA3_RLC5_RB_RPTR_ADDR_LO 10617 #define SDMA3_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 10618 #define SDMA3_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 10619 #define SDMA3_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 10620 #define SDMA3_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 10621 //SDMA3_RLC5_IB_CNTL 10622 #define SDMA3_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 10623 #define SDMA3_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 10624 #define SDMA3_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 10625 #define SDMA3_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 10626 #define SDMA3_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L 10627 #define SDMA3_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 10628 #define SDMA3_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 10629 #define SDMA3_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L 10630 //SDMA3_RLC5_IB_RPTR 10631 #define SDMA3_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 10632 #define SDMA3_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL 10633 //SDMA3_RLC5_IB_OFFSET 10634 #define SDMA3_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 10635 #define SDMA3_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 10636 //SDMA3_RLC5_IB_BASE_LO 10637 #define SDMA3_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 10638 #define SDMA3_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 10639 //SDMA3_RLC5_IB_BASE_HI 10640 #define SDMA3_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 10641 #define SDMA3_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 10642 //SDMA3_RLC5_IB_SIZE 10643 #define SDMA3_RLC5_IB_SIZE__SIZE__SHIFT 0x0 10644 #define SDMA3_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL 10645 //SDMA3_RLC5_SKIP_CNTL 10646 #define SDMA3_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 10647 #define SDMA3_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 10648 //SDMA3_RLC5_CONTEXT_STATUS 10649 #define SDMA3_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 10650 #define SDMA3_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 10651 #define SDMA3_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 10652 #define SDMA3_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 10653 #define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 10654 #define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 10655 #define SDMA3_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 10656 #define SDMA3_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 10657 #define SDMA3_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 10658 #define SDMA3_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L 10659 #define SDMA3_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 10660 #define SDMA3_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 10661 #define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 10662 #define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 10663 #define SDMA3_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 10664 #define SDMA3_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 10665 //SDMA3_RLC5_DOORBELL 10666 #define SDMA3_RLC5_DOORBELL__ENABLE__SHIFT 0x1c 10667 #define SDMA3_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e 10668 #define SDMA3_RLC5_DOORBELL__ENABLE_MASK 0x10000000L 10669 #define SDMA3_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L 10670 //SDMA3_RLC5_STATUS 10671 #define SDMA3_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 10672 #define SDMA3_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 10673 #define SDMA3_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 10674 #define SDMA3_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 10675 //SDMA3_RLC5_DOORBELL_LOG 10676 #define SDMA3_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 10677 #define SDMA3_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 10678 #define SDMA3_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 10679 #define SDMA3_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 10680 //SDMA3_RLC5_WATERMARK 10681 #define SDMA3_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 10682 #define SDMA3_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 10683 #define SDMA3_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 10684 #define SDMA3_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 10685 //SDMA3_RLC5_DOORBELL_OFFSET 10686 #define SDMA3_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 10687 #define SDMA3_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 10688 //SDMA3_RLC5_CSA_ADDR_LO 10689 #define SDMA3_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 10690 #define SDMA3_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 10691 //SDMA3_RLC5_CSA_ADDR_HI 10692 #define SDMA3_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 10693 #define SDMA3_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 10694 //SDMA3_RLC5_IB_SUB_REMAIN 10695 #define SDMA3_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 10696 #define SDMA3_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 10697 //SDMA3_RLC5_PREEMPT 10698 #define SDMA3_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 10699 #define SDMA3_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L 10700 //SDMA3_RLC5_DUMMY_REG 10701 #define SDMA3_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 10702 #define SDMA3_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 10703 //SDMA3_RLC5_RB_WPTR_POLL_ADDR_HI 10704 #define SDMA3_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 10705 #define SDMA3_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 10706 //SDMA3_RLC5_RB_WPTR_POLL_ADDR_LO 10707 #define SDMA3_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 10708 #define SDMA3_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 10709 //SDMA3_RLC5_RB_AQL_CNTL 10710 #define SDMA3_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 10711 #define SDMA3_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 10712 #define SDMA3_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 10713 #define SDMA3_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 10714 #define SDMA3_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 10715 #define SDMA3_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 10716 //SDMA3_RLC5_MINOR_PTR_UPDATE 10717 #define SDMA3_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 10718 #define SDMA3_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 10719 //SDMA3_RLC5_MIDCMD_DATA0 10720 #define SDMA3_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 10721 #define SDMA3_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 10722 //SDMA3_RLC5_MIDCMD_DATA1 10723 #define SDMA3_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 10724 #define SDMA3_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 10725 //SDMA3_RLC5_MIDCMD_DATA2 10726 #define SDMA3_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 10727 #define SDMA3_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 10728 //SDMA3_RLC5_MIDCMD_DATA3 10729 #define SDMA3_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 10730 #define SDMA3_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 10731 //SDMA3_RLC5_MIDCMD_DATA4 10732 #define SDMA3_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 10733 #define SDMA3_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 10734 //SDMA3_RLC5_MIDCMD_DATA5 10735 #define SDMA3_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 10736 #define SDMA3_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 10737 //SDMA3_RLC5_MIDCMD_DATA6 10738 #define SDMA3_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 10739 #define SDMA3_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 10740 //SDMA3_RLC5_MIDCMD_DATA7 10741 #define SDMA3_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 10742 #define SDMA3_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 10743 //SDMA3_RLC5_MIDCMD_DATA8 10744 #define SDMA3_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 10745 #define SDMA3_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 10746 //SDMA3_RLC5_MIDCMD_DATA9 10747 #define SDMA3_RLC5_MIDCMD_DATA9__DATA9__SHIFT 0x0 10748 #define SDMA3_RLC5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 10749 //SDMA3_RLC5_MIDCMD_DATA10 10750 #define SDMA3_RLC5_MIDCMD_DATA10__DATA10__SHIFT 0x0 10751 #define SDMA3_RLC5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 10752 //SDMA3_RLC5_MIDCMD_CNTL 10753 #define SDMA3_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 10754 #define SDMA3_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 10755 #define SDMA3_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 10756 #define SDMA3_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 10757 #define SDMA3_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 10758 #define SDMA3_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 10759 #define SDMA3_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 10760 #define SDMA3_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 10761 //SDMA3_RLC6_RB_CNTL 10762 #define SDMA3_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 10763 #define SDMA3_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 10764 #define SDMA3_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 10765 #define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 10766 #define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 10767 #define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 10768 #define SDMA3_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 10769 #define SDMA3_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 10770 #define SDMA3_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L 10771 #define SDMA3_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL 10772 #define SDMA3_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 10773 #define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 10774 #define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 10775 #define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 10776 #define SDMA3_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L 10777 #define SDMA3_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L 10778 //SDMA3_RLC6_RB_BASE 10779 #define SDMA3_RLC6_RB_BASE__ADDR__SHIFT 0x0 10780 #define SDMA3_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL 10781 //SDMA3_RLC6_RB_BASE_HI 10782 #define SDMA3_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 10783 #define SDMA3_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 10784 //SDMA3_RLC6_RB_RPTR 10785 #define SDMA3_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 10786 #define SDMA3_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 10787 //SDMA3_RLC6_RB_RPTR_HI 10788 #define SDMA3_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 10789 #define SDMA3_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 10790 //SDMA3_RLC6_RB_WPTR 10791 #define SDMA3_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 10792 #define SDMA3_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 10793 //SDMA3_RLC6_RB_WPTR_HI 10794 #define SDMA3_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 10795 #define SDMA3_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 10796 //SDMA3_RLC6_RB_WPTR_POLL_CNTL 10797 #define SDMA3_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 10798 #define SDMA3_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 10799 #define SDMA3_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 10800 #define SDMA3_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 10801 #define SDMA3_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 10802 #define SDMA3_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 10803 #define SDMA3_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 10804 #define SDMA3_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 10805 #define SDMA3_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 10806 #define SDMA3_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 10807 //SDMA3_RLC6_RB_RPTR_ADDR_HI 10808 #define SDMA3_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 10809 #define SDMA3_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 10810 //SDMA3_RLC6_RB_RPTR_ADDR_LO 10811 #define SDMA3_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 10812 #define SDMA3_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 10813 #define SDMA3_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 10814 #define SDMA3_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 10815 //SDMA3_RLC6_IB_CNTL 10816 #define SDMA3_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 10817 #define SDMA3_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 10818 #define SDMA3_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 10819 #define SDMA3_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 10820 #define SDMA3_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L 10821 #define SDMA3_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 10822 #define SDMA3_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 10823 #define SDMA3_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L 10824 //SDMA3_RLC6_IB_RPTR 10825 #define SDMA3_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 10826 #define SDMA3_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL 10827 //SDMA3_RLC6_IB_OFFSET 10828 #define SDMA3_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 10829 #define SDMA3_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 10830 //SDMA3_RLC6_IB_BASE_LO 10831 #define SDMA3_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 10832 #define SDMA3_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 10833 //SDMA3_RLC6_IB_BASE_HI 10834 #define SDMA3_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 10835 #define SDMA3_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 10836 //SDMA3_RLC6_IB_SIZE 10837 #define SDMA3_RLC6_IB_SIZE__SIZE__SHIFT 0x0 10838 #define SDMA3_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL 10839 //SDMA3_RLC6_SKIP_CNTL 10840 #define SDMA3_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 10841 #define SDMA3_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 10842 //SDMA3_RLC6_CONTEXT_STATUS 10843 #define SDMA3_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 10844 #define SDMA3_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 10845 #define SDMA3_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 10846 #define SDMA3_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 10847 #define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 10848 #define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 10849 #define SDMA3_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 10850 #define SDMA3_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 10851 #define SDMA3_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 10852 #define SDMA3_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L 10853 #define SDMA3_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 10854 #define SDMA3_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 10855 #define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 10856 #define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 10857 #define SDMA3_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 10858 #define SDMA3_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 10859 //SDMA3_RLC6_DOORBELL 10860 #define SDMA3_RLC6_DOORBELL__ENABLE__SHIFT 0x1c 10861 #define SDMA3_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e 10862 #define SDMA3_RLC6_DOORBELL__ENABLE_MASK 0x10000000L 10863 #define SDMA3_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L 10864 //SDMA3_RLC6_STATUS 10865 #define SDMA3_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 10866 #define SDMA3_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 10867 #define SDMA3_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 10868 #define SDMA3_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 10869 //SDMA3_RLC6_DOORBELL_LOG 10870 #define SDMA3_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 10871 #define SDMA3_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 10872 #define SDMA3_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 10873 #define SDMA3_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 10874 //SDMA3_RLC6_WATERMARK 10875 #define SDMA3_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 10876 #define SDMA3_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 10877 #define SDMA3_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 10878 #define SDMA3_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 10879 //SDMA3_RLC6_DOORBELL_OFFSET 10880 #define SDMA3_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 10881 #define SDMA3_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 10882 //SDMA3_RLC6_CSA_ADDR_LO 10883 #define SDMA3_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 10884 #define SDMA3_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 10885 //SDMA3_RLC6_CSA_ADDR_HI 10886 #define SDMA3_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 10887 #define SDMA3_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 10888 //SDMA3_RLC6_IB_SUB_REMAIN 10889 #define SDMA3_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 10890 #define SDMA3_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 10891 //SDMA3_RLC6_PREEMPT 10892 #define SDMA3_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 10893 #define SDMA3_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L 10894 //SDMA3_RLC6_DUMMY_REG 10895 #define SDMA3_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 10896 #define SDMA3_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 10897 //SDMA3_RLC6_RB_WPTR_POLL_ADDR_HI 10898 #define SDMA3_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 10899 #define SDMA3_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 10900 //SDMA3_RLC6_RB_WPTR_POLL_ADDR_LO 10901 #define SDMA3_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 10902 #define SDMA3_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 10903 //SDMA3_RLC6_RB_AQL_CNTL 10904 #define SDMA3_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 10905 #define SDMA3_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 10906 #define SDMA3_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 10907 #define SDMA3_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 10908 #define SDMA3_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 10909 #define SDMA3_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 10910 //SDMA3_RLC6_MINOR_PTR_UPDATE 10911 #define SDMA3_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 10912 #define SDMA3_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 10913 //SDMA3_RLC6_MIDCMD_DATA0 10914 #define SDMA3_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 10915 #define SDMA3_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 10916 //SDMA3_RLC6_MIDCMD_DATA1 10917 #define SDMA3_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 10918 #define SDMA3_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 10919 //SDMA3_RLC6_MIDCMD_DATA2 10920 #define SDMA3_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 10921 #define SDMA3_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 10922 //SDMA3_RLC6_MIDCMD_DATA3 10923 #define SDMA3_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 10924 #define SDMA3_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 10925 //SDMA3_RLC6_MIDCMD_DATA4 10926 #define SDMA3_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 10927 #define SDMA3_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 10928 //SDMA3_RLC6_MIDCMD_DATA5 10929 #define SDMA3_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 10930 #define SDMA3_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 10931 //SDMA3_RLC6_MIDCMD_DATA6 10932 #define SDMA3_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 10933 #define SDMA3_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 10934 //SDMA3_RLC6_MIDCMD_DATA7 10935 #define SDMA3_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 10936 #define SDMA3_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 10937 //SDMA3_RLC6_MIDCMD_DATA8 10938 #define SDMA3_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 10939 #define SDMA3_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 10940 //SDMA3_RLC6_MIDCMD_DATA9 10941 #define SDMA3_RLC6_MIDCMD_DATA9__DATA9__SHIFT 0x0 10942 #define SDMA3_RLC6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 10943 //SDMA3_RLC6_MIDCMD_DATA10 10944 #define SDMA3_RLC6_MIDCMD_DATA10__DATA10__SHIFT 0x0 10945 #define SDMA3_RLC6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 10946 //SDMA3_RLC6_MIDCMD_CNTL 10947 #define SDMA3_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 10948 #define SDMA3_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 10949 #define SDMA3_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 10950 #define SDMA3_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 10951 #define SDMA3_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 10952 #define SDMA3_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 10953 #define SDMA3_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 10954 #define SDMA3_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 10955 //SDMA3_RLC7_RB_CNTL 10956 #define SDMA3_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 10957 #define SDMA3_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 10958 #define SDMA3_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 10959 #define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 10960 #define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 10961 #define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 10962 #define SDMA3_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 10963 #define SDMA3_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 10964 #define SDMA3_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L 10965 #define SDMA3_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL 10966 #define SDMA3_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 10967 #define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 10968 #define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 10969 #define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 10970 #define SDMA3_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L 10971 #define SDMA3_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L 10972 //SDMA3_RLC7_RB_BASE 10973 #define SDMA3_RLC7_RB_BASE__ADDR__SHIFT 0x0 10974 #define SDMA3_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL 10975 //SDMA3_RLC7_RB_BASE_HI 10976 #define SDMA3_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 10977 #define SDMA3_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 10978 //SDMA3_RLC7_RB_RPTR 10979 #define SDMA3_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 10980 #define SDMA3_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 10981 //SDMA3_RLC7_RB_RPTR_HI 10982 #define SDMA3_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 10983 #define SDMA3_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 10984 //SDMA3_RLC7_RB_WPTR 10985 #define SDMA3_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 10986 #define SDMA3_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 10987 //SDMA3_RLC7_RB_WPTR_HI 10988 #define SDMA3_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 10989 #define SDMA3_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 10990 //SDMA3_RLC7_RB_WPTR_POLL_CNTL 10991 #define SDMA3_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 10992 #define SDMA3_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 10993 #define SDMA3_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 10994 #define SDMA3_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 10995 #define SDMA3_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 10996 #define SDMA3_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 10997 #define SDMA3_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 10998 #define SDMA3_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 10999 #define SDMA3_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 11000 #define SDMA3_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 11001 //SDMA3_RLC7_RB_RPTR_ADDR_HI 11002 #define SDMA3_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 11003 #define SDMA3_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 11004 //SDMA3_RLC7_RB_RPTR_ADDR_LO 11005 #define SDMA3_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 11006 #define SDMA3_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 11007 #define SDMA3_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 11008 #define SDMA3_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 11009 //SDMA3_RLC7_IB_CNTL 11010 #define SDMA3_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 11011 #define SDMA3_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 11012 #define SDMA3_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 11013 #define SDMA3_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 11014 #define SDMA3_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L 11015 #define SDMA3_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 11016 #define SDMA3_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 11017 #define SDMA3_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L 11018 //SDMA3_RLC7_IB_RPTR 11019 #define SDMA3_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 11020 #define SDMA3_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL 11021 //SDMA3_RLC7_IB_OFFSET 11022 #define SDMA3_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 11023 #define SDMA3_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 11024 //SDMA3_RLC7_IB_BASE_LO 11025 #define SDMA3_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 11026 #define SDMA3_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 11027 //SDMA3_RLC7_IB_BASE_HI 11028 #define SDMA3_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 11029 #define SDMA3_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 11030 //SDMA3_RLC7_IB_SIZE 11031 #define SDMA3_RLC7_IB_SIZE__SIZE__SHIFT 0x0 11032 #define SDMA3_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL 11033 //SDMA3_RLC7_SKIP_CNTL 11034 #define SDMA3_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 11035 #define SDMA3_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 11036 //SDMA3_RLC7_CONTEXT_STATUS 11037 #define SDMA3_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 11038 #define SDMA3_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 11039 #define SDMA3_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 11040 #define SDMA3_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 11041 #define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 11042 #define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 11043 #define SDMA3_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 11044 #define SDMA3_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 11045 #define SDMA3_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 11046 #define SDMA3_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L 11047 #define SDMA3_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 11048 #define SDMA3_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 11049 #define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 11050 #define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 11051 #define SDMA3_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 11052 #define SDMA3_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 11053 //SDMA3_RLC7_DOORBELL 11054 #define SDMA3_RLC7_DOORBELL__ENABLE__SHIFT 0x1c 11055 #define SDMA3_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e 11056 #define SDMA3_RLC7_DOORBELL__ENABLE_MASK 0x10000000L 11057 #define SDMA3_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L 11058 //SDMA3_RLC7_STATUS 11059 #define SDMA3_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 11060 #define SDMA3_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 11061 #define SDMA3_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 11062 #define SDMA3_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 11063 //SDMA3_RLC7_DOORBELL_LOG 11064 #define SDMA3_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 11065 #define SDMA3_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 11066 #define SDMA3_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 11067 #define SDMA3_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 11068 //SDMA3_RLC7_WATERMARK 11069 #define SDMA3_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 11070 #define SDMA3_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 11071 #define SDMA3_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 11072 #define SDMA3_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 11073 //SDMA3_RLC7_DOORBELL_OFFSET 11074 #define SDMA3_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 11075 #define SDMA3_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 11076 //SDMA3_RLC7_CSA_ADDR_LO 11077 #define SDMA3_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 11078 #define SDMA3_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 11079 //SDMA3_RLC7_CSA_ADDR_HI 11080 #define SDMA3_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 11081 #define SDMA3_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 11082 //SDMA3_RLC7_IB_SUB_REMAIN 11083 #define SDMA3_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 11084 #define SDMA3_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 11085 //SDMA3_RLC7_PREEMPT 11086 #define SDMA3_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 11087 #define SDMA3_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L 11088 //SDMA3_RLC7_DUMMY_REG 11089 #define SDMA3_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 11090 #define SDMA3_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 11091 //SDMA3_RLC7_RB_WPTR_POLL_ADDR_HI 11092 #define SDMA3_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 11093 #define SDMA3_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 11094 //SDMA3_RLC7_RB_WPTR_POLL_ADDR_LO 11095 #define SDMA3_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 11096 #define SDMA3_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 11097 //SDMA3_RLC7_RB_AQL_CNTL 11098 #define SDMA3_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 11099 #define SDMA3_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 11100 #define SDMA3_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 11101 #define SDMA3_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 11102 #define SDMA3_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 11103 #define SDMA3_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 11104 //SDMA3_RLC7_MINOR_PTR_UPDATE 11105 #define SDMA3_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 11106 #define SDMA3_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 11107 //SDMA3_RLC7_MIDCMD_DATA0 11108 #define SDMA3_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 11109 #define SDMA3_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 11110 //SDMA3_RLC7_MIDCMD_DATA1 11111 #define SDMA3_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 11112 #define SDMA3_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 11113 //SDMA3_RLC7_MIDCMD_DATA2 11114 #define SDMA3_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 11115 #define SDMA3_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 11116 //SDMA3_RLC7_MIDCMD_DATA3 11117 #define SDMA3_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 11118 #define SDMA3_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 11119 //SDMA3_RLC7_MIDCMD_DATA4 11120 #define SDMA3_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 11121 #define SDMA3_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 11122 //SDMA3_RLC7_MIDCMD_DATA5 11123 #define SDMA3_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 11124 #define SDMA3_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 11125 //SDMA3_RLC7_MIDCMD_DATA6 11126 #define SDMA3_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 11127 #define SDMA3_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 11128 //SDMA3_RLC7_MIDCMD_DATA7 11129 #define SDMA3_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 11130 #define SDMA3_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 11131 //SDMA3_RLC7_MIDCMD_DATA8 11132 #define SDMA3_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 11133 #define SDMA3_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 11134 //SDMA3_RLC7_MIDCMD_DATA9 11135 #define SDMA3_RLC7_MIDCMD_DATA9__DATA9__SHIFT 0x0 11136 #define SDMA3_RLC7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 11137 //SDMA3_RLC7_MIDCMD_DATA10 11138 #define SDMA3_RLC7_MIDCMD_DATA10__DATA10__SHIFT 0x0 11139 #define SDMA3_RLC7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 11140 //SDMA3_RLC7_MIDCMD_CNTL 11141 #define SDMA3_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 11142 #define SDMA3_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 11143 #define SDMA3_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 11144 #define SDMA3_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 11145 #define SDMA3_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 11146 #define SDMA3_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 11147 #define SDMA3_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 11148 #define SDMA3_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 11149 11150 11151 // addressBlock: sdma0_sdma4dec 11152 //SDMA4_UCODE_ADDR 11153 #define SDMA4_UCODE_ADDR__VALUE__SHIFT 0x0 11154 #define SDMA4_UCODE_ADDR__VALUE_MASK 0x00003FFFL 11155 //SDMA4_UCODE_DATA 11156 #define SDMA4_UCODE_DATA__VALUE__SHIFT 0x0 11157 #define SDMA4_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 11158 //SDMA4_VF_ENABLE 11159 #define SDMA4_VF_ENABLE__VF_ENABLE__SHIFT 0x0 11160 #define SDMA4_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 11161 #define SDMA4_PUB_REG_TYPE0__SDMA4_UCODE_ADDR__SHIFT 0x0 11162 #define SDMA4_PUB_REG_TYPE0__SDMA4_UCODE_DATA__SHIFT 0x1 11163 #define SDMA4_PUB_REG_TYPE0__SDMA4_UCODE_ADDR_MASK 0x00000001L 11164 #define SDMA4_PUB_REG_TYPE0__SDMA4_UCODE_DATA_MASK 0x00000002L 11165 //SDMA4_CONTEXT_GROUP_BOUNDARY 11166 #define SDMA4_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 11167 #define SDMA4_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 11168 //SDMA4_POWER_CNTL 11169 #define SDMA4_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 11170 #define SDMA4_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 11171 #define SDMA4_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 11172 #define SDMA4_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 11173 #define SDMA4_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 11174 #define SDMA4_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 11175 #define SDMA4_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 11176 #define SDMA4_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 11177 #define SDMA4_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 11178 #define SDMA4_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a 11179 #define SDMA4_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L 11180 #define SDMA4_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L 11181 #define SDMA4_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L 11182 #define SDMA4_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 11183 #define SDMA4_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 11184 #define SDMA4_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 11185 #define SDMA4_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 11186 #define SDMA4_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 11187 #define SDMA4_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 11188 #define SDMA4_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 11189 //SDMA4_CLK_CTRL 11190 #define SDMA4_CLK_CTRL__ON_DELAY__SHIFT 0x0 11191 #define SDMA4_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 11192 #define SDMA4_CLK_CTRL__RESERVED__SHIFT 0xc 11193 #define SDMA4_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 11194 #define SDMA4_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 11195 #define SDMA4_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 11196 #define SDMA4_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 11197 #define SDMA4_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 11198 #define SDMA4_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 11199 #define SDMA4_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 11200 #define SDMA4_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 11201 #define SDMA4_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 11202 #define SDMA4_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 11203 #define SDMA4_CLK_CTRL__RESERVED_MASK 0x00FFF000L 11204 #define SDMA4_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 11205 #define SDMA4_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 11206 #define SDMA4_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 11207 #define SDMA4_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 11208 #define SDMA4_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 11209 #define SDMA4_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 11210 #define SDMA4_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 11211 #define SDMA4_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 11212 //SDMA4_CNTL 11213 #define SDMA4_CNTL__TRAP_ENABLE__SHIFT 0x0 11214 #define SDMA4_CNTL__UTC_L1_ENABLE__SHIFT 0x1 11215 #define SDMA4_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 11216 #define SDMA4_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 11217 #define SDMA4_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 11218 #define SDMA4_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 11219 #define SDMA4_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x6 11220 #define SDMA4_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 11221 #define SDMA4_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 11222 #define SDMA4_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 11223 #define SDMA4_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 11224 #define SDMA4_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 11225 #define SDMA4_CNTL__TRAP_ENABLE_MASK 0x00000001L 11226 #define SDMA4_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 11227 #define SDMA4_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 11228 #define SDMA4_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 11229 #define SDMA4_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 11230 #define SDMA4_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 11231 #define SDMA4_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000040L 11232 #define SDMA4_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 11233 #define SDMA4_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 11234 #define SDMA4_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 11235 #define SDMA4_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 11236 #define SDMA4_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 11237 //SDMA4_CHICKEN_BITS 11238 #define SDMA4_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 11239 #define SDMA4_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 11240 #define SDMA4_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 11241 #define SDMA4_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 11242 #define SDMA4_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 11243 #define SDMA4_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 11244 #define SDMA4_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 11245 #define SDMA4_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 11246 #define SDMA4_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 11247 #define SDMA4_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 11248 #define SDMA4_CHICKEN_BITS__SRAM_FGCG_ENABLE__SHIFT 0x1a 11249 #define SDMA4_CHICKEN_BITS__RESERVED__SHIFT 0x1b 11250 #define SDMA4_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 11251 #define SDMA4_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 11252 #define SDMA4_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 11253 #define SDMA4_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 11254 #define SDMA4_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 11255 #define SDMA4_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 11256 #define SDMA4_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 11257 #define SDMA4_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 11258 #define SDMA4_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 11259 #define SDMA4_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 11260 #define SDMA4_CHICKEN_BITS__SRAM_FGCG_ENABLE_MASK 0x04000000L 11261 #define SDMA4_CHICKEN_BITS__RESERVED_MASK 0xF8000000L 11262 //SDMA4_GB_ADDR_CONFIG 11263 #define SDMA4_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 11264 #define SDMA4_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 11265 #define SDMA4_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 11266 #define SDMA4_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 11267 #define SDMA4_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 11268 #define SDMA4_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 11269 #define SDMA4_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 11270 #define SDMA4_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 11271 #define SDMA4_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 11272 #define SDMA4_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 11273 //SDMA4_GB_ADDR_CONFIG_READ 11274 #define SDMA4_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 11275 #define SDMA4_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 11276 #define SDMA4_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 11277 #define SDMA4_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 11278 #define SDMA4_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 11279 #define SDMA4_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 11280 #define SDMA4_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 11281 #define SDMA4_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 11282 #define SDMA4_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 11283 #define SDMA4_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 11284 //SDMA4_RB_RPTR_FETCH_HI 11285 #define SDMA4_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 11286 #define SDMA4_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 11287 //SDMA4_SEM_WAIT_FAIL_TIMER_CNTL 11288 #define SDMA4_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 11289 #define SDMA4_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 11290 //SDMA4_RB_RPTR_FETCH 11291 #define SDMA4_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 11292 #define SDMA4_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 11293 //SDMA4_IB_OFFSET_FETCH 11294 #define SDMA4_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 11295 #define SDMA4_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 11296 //SDMA4_PROGRAM 11297 #define SDMA4_PROGRAM__STREAM__SHIFT 0x0 11298 #define SDMA4_PROGRAM__STREAM_MASK 0xFFFFFFFFL 11299 //SDMA4_STATUS_REG 11300 #define SDMA4_STATUS_REG__IDLE__SHIFT 0x0 11301 #define SDMA4_STATUS_REG__REG_IDLE__SHIFT 0x1 11302 #define SDMA4_STATUS_REG__RB_EMPTY__SHIFT 0x2 11303 #define SDMA4_STATUS_REG__RB_FULL__SHIFT 0x3 11304 #define SDMA4_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 11305 #define SDMA4_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 11306 #define SDMA4_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 11307 #define SDMA4_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 11308 #define SDMA4_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 11309 #define SDMA4_STATUS_REG__INSIDE_IB__SHIFT 0x9 11310 #define SDMA4_STATUS_REG__EX_IDLE__SHIFT 0xa 11311 #define SDMA4_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 11312 #define SDMA4_STATUS_REG__PACKET_READY__SHIFT 0xc 11313 #define SDMA4_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 11314 #define SDMA4_STATUS_REG__SRBM_IDLE__SHIFT 0xe 11315 #define SDMA4_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 11316 #define SDMA4_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 11317 #define SDMA4_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 11318 #define SDMA4_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 11319 #define SDMA4_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 11320 #define SDMA4_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 11321 #define SDMA4_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 11322 #define SDMA4_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 11323 #define SDMA4_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 11324 #define SDMA4_STATUS_REG__SEM_IDLE__SHIFT 0x1a 11325 #define SDMA4_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 11326 #define SDMA4_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 11327 #define SDMA4_STATUS_REG__INT_IDLE__SHIFT 0x1e 11328 #define SDMA4_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 11329 #define SDMA4_STATUS_REG__IDLE_MASK 0x00000001L 11330 #define SDMA4_STATUS_REG__REG_IDLE_MASK 0x00000002L 11331 #define SDMA4_STATUS_REG__RB_EMPTY_MASK 0x00000004L 11332 #define SDMA4_STATUS_REG__RB_FULL_MASK 0x00000008L 11333 #define SDMA4_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 11334 #define SDMA4_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 11335 #define SDMA4_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 11336 #define SDMA4_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 11337 #define SDMA4_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 11338 #define SDMA4_STATUS_REG__INSIDE_IB_MASK 0x00000200L 11339 #define SDMA4_STATUS_REG__EX_IDLE_MASK 0x00000400L 11340 #define SDMA4_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 11341 #define SDMA4_STATUS_REG__PACKET_READY_MASK 0x00001000L 11342 #define SDMA4_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 11343 #define SDMA4_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 11344 #define SDMA4_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 11345 #define SDMA4_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 11346 #define SDMA4_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 11347 #define SDMA4_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 11348 #define SDMA4_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 11349 #define SDMA4_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 11350 #define SDMA4_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 11351 #define SDMA4_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 11352 #define SDMA4_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 11353 #define SDMA4_STATUS_REG__SEM_IDLE_MASK 0x04000000L 11354 #define SDMA4_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 11355 #define SDMA4_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 11356 #define SDMA4_STATUS_REG__INT_IDLE_MASK 0x40000000L 11357 #define SDMA4_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 11358 //SDMA4_STATUS1_REG 11359 #define SDMA4_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 11360 #define SDMA4_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 11361 #define SDMA4_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 11362 #define SDMA4_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 11363 #define SDMA4_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 11364 #define SDMA4_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 11365 #define SDMA4_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 11366 #define SDMA4_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 11367 #define SDMA4_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 11368 #define SDMA4_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 11369 #define SDMA4_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 11370 #define SDMA4_STATUS1_REG__EX_START__SHIFT 0xf 11371 #define SDMA4_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 11372 #define SDMA4_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 11373 #define SDMA4_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 11374 #define SDMA4_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 11375 #define SDMA4_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 11376 #define SDMA4_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 11377 #define SDMA4_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 11378 #define SDMA4_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 11379 #define SDMA4_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 11380 #define SDMA4_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 11381 #define SDMA4_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 11382 #define SDMA4_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 11383 #define SDMA4_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 11384 #define SDMA4_STATUS1_REG__EX_START_MASK 0x00008000L 11385 #define SDMA4_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 11386 #define SDMA4_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 11387 //SDMA4_RD_BURST_CNTL 11388 #define SDMA4_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 11389 #define SDMA4_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 11390 #define SDMA4_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 11391 #define SDMA4_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL 11392 //SDMA4_HBM_PAGE_CONFIG 11393 #define SDMA4_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 11394 #define SDMA4_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L 11395 //SDMA4_UCODE_CHECKSUM 11396 #define SDMA4_UCODE_CHECKSUM__DATA__SHIFT 0x0 11397 #define SDMA4_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 11398 //SDMA4_F32_CNTL 11399 #define SDMA4_F32_CNTL__HALT__SHIFT 0x0 11400 #define SDMA4_F32_CNTL__STEP__SHIFT 0x1 11401 #define SDMA4_F32_CNTL__RESET__SHIFT 0x8 11402 #define SDMA4_F32_CNTL__HALT_MASK 0x00000001L 11403 #define SDMA4_F32_CNTL__STEP_MASK 0x00000002L 11404 #define SDMA4_F32_CNTL__RESET_MASK 0x00000100L 11405 //SDMA4_FREEZE 11406 #define SDMA4_FREEZE__PREEMPT__SHIFT 0x0 11407 #define SDMA4_FREEZE__FREEZE__SHIFT 0x4 11408 #define SDMA4_FREEZE__FROZEN__SHIFT 0x5 11409 #define SDMA4_FREEZE__F32_FREEZE__SHIFT 0x6 11410 #define SDMA4_FREEZE__PREEMPT_MASK 0x00000001L 11411 #define SDMA4_FREEZE__FREEZE_MASK 0x00000010L 11412 #define SDMA4_FREEZE__FROZEN_MASK 0x00000020L 11413 #define SDMA4_FREEZE__F32_FREEZE_MASK 0x00000040L 11414 //SDMA4_PHASE0_QUANTUM 11415 #define SDMA4_PHASE0_QUANTUM__UNIT__SHIFT 0x0 11416 #define SDMA4_PHASE0_QUANTUM__VALUE__SHIFT 0x8 11417 #define SDMA4_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 11418 #define SDMA4_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 11419 #define SDMA4_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 11420 #define SDMA4_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 11421 //SDMA4_PHASE1_QUANTUM 11422 #define SDMA4_PHASE1_QUANTUM__UNIT__SHIFT 0x0 11423 #define SDMA4_PHASE1_QUANTUM__VALUE__SHIFT 0x8 11424 #define SDMA4_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 11425 #define SDMA4_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 11426 #define SDMA4_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 11427 #define SDMA4_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 11428 //CC_SDMA4_EDC_CONFIG 11429 #define CC_SDMA4_EDC_CONFIG__DIS_EDC__SHIFT 0x1 11430 #define CC_SDMA4_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 11431 //SDMA4_BA_THRESHOLD 11432 #define SDMA4_BA_THRESHOLD__READ_THRES__SHIFT 0x0 11433 #define SDMA4_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 11434 #define SDMA4_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 11435 #define SDMA4_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 11436 //SDMA4_ID 11437 #define SDMA4_ID__DEVICE_ID__SHIFT 0x0 11438 #define SDMA4_ID__DEVICE_ID_MASK 0x000000FFL 11439 //SDMA4_VERSION 11440 #define SDMA4_VERSION__MINVER__SHIFT 0x0 11441 #define SDMA4_VERSION__MAJVER__SHIFT 0x8 11442 #define SDMA4_VERSION__REV__SHIFT 0x10 11443 #define SDMA4_VERSION__MINVER_MASK 0x0000007FL 11444 #define SDMA4_VERSION__MAJVER_MASK 0x00007F00L 11445 #define SDMA4_VERSION__REV_MASK 0x003F0000L 11446 //SDMA4_EDC_COUNTER 11447 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x0 11448 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x2 11449 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x4 11450 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0x6 11451 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0x8 11452 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa 11453 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xc 11454 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 11455 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0x10 11456 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x12 11457 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x14 11458 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x16 11459 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x18 11460 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x1a 11461 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x1c 11462 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x1e 11463 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000003L 11464 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x0000000CL 11465 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000030L 11466 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x000000C0L 11467 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000300L 11468 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00000C00L 11469 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00003000L 11470 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x0000C000L 11471 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00030000L 11472 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x000C0000L 11473 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00300000L 11474 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00C00000L 11475 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x03000000L 11476 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x0C000000L 11477 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x30000000L 11478 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0xC0000000L 11479 //SDMA4_EDC_COUNTER2 11480 #define SDMA4_EDC_COUNTER2__SDMA_UCODE_BUF_SED__SHIFT 0x0 11481 #define SDMA4_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 11482 #define SDMA4_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED__SHIFT 0x4 11483 #define SDMA4_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x6 11484 #define SDMA4_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x8 11485 #define SDMA4_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED__SHIFT 0xa 11486 #define SDMA4_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED__SHIFT 0xc 11487 #define SDMA4_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED__SHIFT 0xe 11488 #define SDMA4_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 11489 #define SDMA4_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED__SHIFT 0x12 11490 #define SDMA4_EDC_COUNTER2__SDMA_UCODE_BUF_SED_MASK 0x00000003L 11491 #define SDMA4_EDC_COUNTER2__SDMA_RB_CMD_BUF_SED_MASK 0x0000000CL 11492 #define SDMA4_EDC_COUNTER2__SDMA_IB_CMD_BUF_SED_MASK 0x00000030L 11493 #define SDMA4_EDC_COUNTER2__SDMA_UTCL1_RD_FIFO_SED_MASK 0x000000C0L 11494 #define SDMA4_EDC_COUNTER2__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000300L 11495 #define SDMA4_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED_MASK 0x00000C00L 11496 #define SDMA4_EDC_COUNTER2__SDMA_DATA_LUT_FIFO_SED_MASK 0x00003000L 11497 #define SDMA4_EDC_COUNTER2__SDMA_SPLIT_DATA_BUF_SED_MASK 0x0000C000L 11498 #define SDMA4_EDC_COUNTER2__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00030000L 11499 #define SDMA4_EDC_COUNTER2__SDMA_MC_RDRET_BUF_SED_MASK 0x000C0000L 11500 //SDMA4_STATUS2_REG 11501 #define SDMA4_STATUS2_REG__ID__SHIFT 0x0 11502 #define SDMA4_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 11503 #define SDMA4_STATUS2_REG__CMD_OP__SHIFT 0x10 11504 #define SDMA4_STATUS2_REG__ID_MASK 0x00000007L 11505 #define SDMA4_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L 11506 #define SDMA4_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 11507 //SDMA4_ATOMIC_CNTL 11508 #define SDMA4_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 11509 #define SDMA4_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 11510 #define SDMA4_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 11511 #define SDMA4_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 11512 //SDMA4_ATOMIC_PREOP_LO 11513 #define SDMA4_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 11514 #define SDMA4_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 11515 //SDMA4_ATOMIC_PREOP_HI 11516 #define SDMA4_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 11517 #define SDMA4_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 11518 //SDMA4_UTCL1_CNTL 11519 #define SDMA4_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 11520 #define SDMA4_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 11521 #define SDMA4_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 11522 #define SDMA4_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 11523 #define SDMA4_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 11524 #define SDMA4_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 11525 #define SDMA4_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 11526 #define SDMA4_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 11527 #define SDMA4_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 11528 #define SDMA4_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 11529 #define SDMA4_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 11530 #define SDMA4_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 11531 //SDMA4_UTCL1_WATERMK 11532 #define SDMA4_UTCL1_WATERMK__REQ_WATERMK__SHIFT 0x0 11533 #define SDMA4_UTCL1_WATERMK__REQ_DEPTH__SHIFT 0x3 11534 #define SDMA4_UTCL1_WATERMK__PAGE_WATERMK__SHIFT 0x5 11535 #define SDMA4_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x8 11536 #define SDMA4_UTCL1_WATERMK__RESERVED__SHIFT 0x10 11537 #define SDMA4_UTCL1_WATERMK__REQ_WATERMK_MASK 0x00000007L 11538 #define SDMA4_UTCL1_WATERMK__REQ_DEPTH_MASK 0x00000018L 11539 #define SDMA4_UTCL1_WATERMK__PAGE_WATERMK_MASK 0x000000E0L 11540 #define SDMA4_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x0000FF00L 11541 #define SDMA4_UTCL1_WATERMK__RESERVED_MASK 0xFFFF0000L 11542 //SDMA4_UTCL1_RD_STATUS 11543 #define SDMA4_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 11544 #define SDMA4_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 11545 #define SDMA4_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 11546 #define SDMA4_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 11547 #define SDMA4_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 11548 #define SDMA4_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 11549 #define SDMA4_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 11550 #define SDMA4_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 11551 #define SDMA4_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 11552 #define SDMA4_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 11553 #define SDMA4_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 11554 #define SDMA4_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 11555 #define SDMA4_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 11556 #define SDMA4_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 11557 #define SDMA4_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 11558 #define SDMA4_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 11559 #define SDMA4_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 11560 #define SDMA4_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 11561 #define SDMA4_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 11562 #define SDMA4_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 11563 #define SDMA4_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 11564 #define SDMA4_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 11565 #define SDMA4_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 11566 #define SDMA4_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 11567 #define SDMA4_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 11568 #define SDMA4_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 11569 #define SDMA4_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 11570 #define SDMA4_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 11571 #define SDMA4_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 11572 #define SDMA4_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 11573 #define SDMA4_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 11574 #define SDMA4_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 11575 #define SDMA4_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 11576 #define SDMA4_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 11577 #define SDMA4_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 11578 #define SDMA4_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 11579 #define SDMA4_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 11580 #define SDMA4_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 11581 #define SDMA4_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 11582 #define SDMA4_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 11583 #define SDMA4_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 11584 #define SDMA4_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 11585 #define SDMA4_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 11586 #define SDMA4_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 11587 #define SDMA4_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 11588 #define SDMA4_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 11589 #define SDMA4_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 11590 #define SDMA4_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 11591 #define SDMA4_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 11592 #define SDMA4_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 11593 #define SDMA4_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 11594 #define SDMA4_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 11595 #define SDMA4_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 11596 #define SDMA4_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 11597 //SDMA4_UTCL1_WR_STATUS 11598 #define SDMA4_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 11599 #define SDMA4_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 11600 #define SDMA4_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 11601 #define SDMA4_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 11602 #define SDMA4_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 11603 #define SDMA4_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 11604 #define SDMA4_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 11605 #define SDMA4_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 11606 #define SDMA4_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 11607 #define SDMA4_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 11608 #define SDMA4_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 11609 #define SDMA4_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 11610 #define SDMA4_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 11611 #define SDMA4_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 11612 #define SDMA4_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 11613 #define SDMA4_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 11614 #define SDMA4_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 11615 #define SDMA4_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 11616 #define SDMA4_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 11617 #define SDMA4_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 11618 #define SDMA4_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 11619 #define SDMA4_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 11620 #define SDMA4_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 11621 #define SDMA4_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 11622 #define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 11623 #define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 11624 #define SDMA4_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 11625 #define SDMA4_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 11626 #define SDMA4_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 11627 #define SDMA4_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 11628 #define SDMA4_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 11629 #define SDMA4_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 11630 #define SDMA4_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 11631 #define SDMA4_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 11632 #define SDMA4_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 11633 #define SDMA4_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 11634 #define SDMA4_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 11635 #define SDMA4_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 11636 #define SDMA4_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 11637 #define SDMA4_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 11638 #define SDMA4_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 11639 #define SDMA4_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 11640 #define SDMA4_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 11641 #define SDMA4_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 11642 #define SDMA4_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 11643 #define SDMA4_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 11644 #define SDMA4_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 11645 #define SDMA4_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 11646 #define SDMA4_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 11647 #define SDMA4_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 11648 #define SDMA4_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 11649 #define SDMA4_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 11650 #define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 11651 #define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 11652 #define SDMA4_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 11653 #define SDMA4_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 11654 //SDMA4_UTCL1_INV0 11655 #define SDMA4_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 11656 #define SDMA4_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 11657 #define SDMA4_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 11658 #define SDMA4_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 11659 #define SDMA4_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 11660 #define SDMA4_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 11661 #define SDMA4_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 11662 #define SDMA4_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 11663 #define SDMA4_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 11664 #define SDMA4_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 11665 #define SDMA4_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 11666 #define SDMA4_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 11667 #define SDMA4_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 11668 #define SDMA4_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 11669 #define SDMA4_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 11670 #define SDMA4_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 11671 #define SDMA4_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 11672 #define SDMA4_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 11673 #define SDMA4_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 11674 #define SDMA4_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 11675 #define SDMA4_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 11676 #define SDMA4_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 11677 #define SDMA4_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 11678 #define SDMA4_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 11679 #define SDMA4_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 11680 #define SDMA4_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 11681 #define SDMA4_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 11682 #define SDMA4_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 11683 //SDMA4_UTCL1_INV1 11684 #define SDMA4_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 11685 #define SDMA4_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 11686 //SDMA4_UTCL1_INV2 11687 #define SDMA4_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 11688 #define SDMA4_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 11689 //SDMA4_UTCL1_RD_XNACK0 11690 #define SDMA4_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 11691 #define SDMA4_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 11692 //SDMA4_UTCL1_RD_XNACK1 11693 #define SDMA4_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 11694 #define SDMA4_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 11695 #define SDMA4_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 11696 #define SDMA4_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 11697 #define SDMA4_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 11698 #define SDMA4_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 11699 #define SDMA4_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 11700 #define SDMA4_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 11701 //SDMA4_UTCL1_WR_XNACK0 11702 #define SDMA4_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 11703 #define SDMA4_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 11704 //SDMA4_UTCL1_WR_XNACK1 11705 #define SDMA4_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 11706 #define SDMA4_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 11707 #define SDMA4_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 11708 #define SDMA4_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 11709 #define SDMA4_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 11710 #define SDMA4_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 11711 #define SDMA4_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 11712 #define SDMA4_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 11713 //SDMA4_UTCL1_TIMEOUT 11714 #define SDMA4_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 11715 #define SDMA4_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 11716 #define SDMA4_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 11717 #define SDMA4_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 11718 //SDMA4_UTCL1_PAGE 11719 #define SDMA4_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 11720 #define SDMA4_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 11721 #define SDMA4_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 11722 #define SDMA4_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 11723 #define SDMA4_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 11724 #define SDMA4_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 11725 #define SDMA4_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 11726 #define SDMA4_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 11727 //SDMA4_POWER_CNTL_IDLE 11728 #define SDMA4_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 11729 #define SDMA4_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 11730 #define SDMA4_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 11731 #define SDMA4_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 11732 #define SDMA4_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 11733 #define SDMA4_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 11734 //SDMA4_RELAX_ORDERING_LUT 11735 #define SDMA4_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 11736 #define SDMA4_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 11737 #define SDMA4_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 11738 #define SDMA4_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 11739 #define SDMA4_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 11740 #define SDMA4_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 11741 #define SDMA4_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 11742 #define SDMA4_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 11743 #define SDMA4_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 11744 #define SDMA4_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 11745 #define SDMA4_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 11746 #define SDMA4_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 11747 #define SDMA4_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 11748 #define SDMA4_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 11749 #define SDMA4_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 11750 #define SDMA4_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 11751 #define SDMA4_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 11752 #define SDMA4_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 11753 #define SDMA4_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 11754 #define SDMA4_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 11755 #define SDMA4_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 11756 #define SDMA4_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 11757 #define SDMA4_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 11758 #define SDMA4_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 11759 #define SDMA4_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 11760 #define SDMA4_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 11761 #define SDMA4_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 11762 #define SDMA4_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 11763 #define SDMA4_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 11764 #define SDMA4_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 11765 #define SDMA4_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 11766 #define SDMA4_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 11767 #define SDMA4_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 11768 #define SDMA4_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 11769 #define SDMA4_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 11770 #define SDMA4_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 11771 #define SDMA4_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 11772 #define SDMA4_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 11773 //SDMA4_CHICKEN_BITS_2 11774 #define SDMA4_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 11775 #define SDMA4_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x4 11776 #define SDMA4_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 11777 #define SDMA4_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00000010L 11778 //SDMA4_STATUS3_REG 11779 #define SDMA4_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 11780 #define SDMA4_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 11781 #define SDMA4_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 11782 #define SDMA4_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 11783 #define SDMA4_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 11784 #define SDMA4_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 11785 #define SDMA4_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 11786 #define SDMA4_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 11787 #define SDMA4_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L 11788 #define SDMA4_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L 11789 //SDMA4_PHYSICAL_ADDR_LO 11790 #define SDMA4_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 11791 #define SDMA4_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 11792 #define SDMA4_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 11793 #define SDMA4_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 11794 #define SDMA4_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 11795 #define SDMA4_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 11796 #define SDMA4_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 11797 #define SDMA4_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 11798 //SDMA4_PHYSICAL_ADDR_HI 11799 #define SDMA4_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 11800 #define SDMA4_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 11801 //SDMA4_PHASE2_QUANTUM 11802 #define SDMA4_PHASE2_QUANTUM__UNIT__SHIFT 0x0 11803 #define SDMA4_PHASE2_QUANTUM__VALUE__SHIFT 0x8 11804 #define SDMA4_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 11805 #define SDMA4_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 11806 #define SDMA4_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 11807 #define SDMA4_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 11808 //SDMA4_ERROR_LOG 11809 #define SDMA4_ERROR_LOG__OVERRIDE__SHIFT 0x0 11810 #define SDMA4_ERROR_LOG__STATUS__SHIFT 0x10 11811 #define SDMA4_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 11812 #define SDMA4_ERROR_LOG__STATUS_MASK 0xFFFF0000L 11813 //SDMA4_PUB_DUMMY_REG0 11814 #define SDMA4_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 11815 #define SDMA4_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 11816 //SDMA4_PUB_DUMMY_REG1 11817 #define SDMA4_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 11818 #define SDMA4_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 11819 //SDMA4_PUB_DUMMY_REG2 11820 #define SDMA4_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 11821 #define SDMA4_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 11822 //SDMA4_PUB_DUMMY_REG3 11823 #define SDMA4_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 11824 #define SDMA4_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 11825 //SDMA4_F32_COUNTER 11826 #define SDMA4_F32_COUNTER__VALUE__SHIFT 0x0 11827 #define SDMA4_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 11828 //SDMA4_PERFCNT_PERFCOUNTER0_CFG 11829 #define SDMA4_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 11830 #define SDMA4_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 11831 #define SDMA4_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 11832 #define SDMA4_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 11833 #define SDMA4_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 11834 #define SDMA4_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 11835 #define SDMA4_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 11836 #define SDMA4_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 11837 #define SDMA4_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 11838 #define SDMA4_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 11839 //SDMA4_PERFCNT_PERFCOUNTER1_CFG 11840 #define SDMA4_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 11841 #define SDMA4_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 11842 #define SDMA4_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 11843 #define SDMA4_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 11844 #define SDMA4_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 11845 #define SDMA4_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 11846 #define SDMA4_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 11847 #define SDMA4_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 11848 #define SDMA4_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 11849 #define SDMA4_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 11850 //SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL 11851 #define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 11852 #define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 11853 #define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 11854 #define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 11855 #define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 11856 #define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 11857 #define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 11858 #define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 11859 #define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 11860 #define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 11861 #define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 11862 #define SDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 11863 //SDMA4_PERFCNT_MISC_CNTL 11864 #define SDMA4_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 11865 #define SDMA4_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL 11866 //SDMA4_PERFCNT_PERFCOUNTER_LO 11867 #define SDMA4_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 11868 #define SDMA4_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 11869 //SDMA4_PERFCNT_PERFCOUNTER_HI 11870 #define SDMA4_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 11871 #define SDMA4_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 11872 #define SDMA4_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 11873 #define SDMA4_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 11874 //SDMA4_CRD_CNTL 11875 #define SDMA4_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 11876 #define SDMA4_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 11877 #define SDMA4_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 11878 #define SDMA4_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 11879 //SDMA4_ULV_CNTL 11880 #define SDMA4_ULV_CNTL__HYSTERESIS__SHIFT 0x0 11881 #define SDMA4_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b 11882 #define SDMA4_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c 11883 #define SDMA4_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 11884 #define SDMA4_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 11885 #define SDMA4_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 11886 #define SDMA4_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 11887 #define SDMA4_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L 11888 #define SDMA4_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L 11889 #define SDMA4_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 11890 #define SDMA4_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 11891 #define SDMA4_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 11892 //SDMA4_EA_DBIT_ADDR_DATA 11893 #define SDMA4_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 11894 #define SDMA4_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 11895 //SDMA4_EA_DBIT_ADDR_INDEX 11896 #define SDMA4_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 11897 #define SDMA4_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 11898 //SDMA4_STATUS4_REG 11899 #define SDMA4_STATUS4_REG__IDLE__SHIFT 0x0 11900 #define SDMA4_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2 11901 #define SDMA4_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3 11902 #define SDMA4_STATUS4_REG__MMHUB_RD_OUTSTANDING__SHIFT 0x4 11903 #define SDMA4_STATUS4_REG__MMHUB_WR_OUTSTANDING__SHIFT 0x5 11904 #define SDMA4_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x6 11905 #define SDMA4_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x7 11906 #define SDMA4_STATUS4_REG__REG_POLLING__SHIFT 0x8 11907 #define SDMA4_STATUS4_REG__MEM_POLLING__SHIFT 0x9 11908 #define SDMA4_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xa 11909 #define SDMA4_STATUS4_REG__UTCL2_WR_XNACK__SHIFT 0xc 11910 #define SDMA4_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0xe 11911 #define SDMA4_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x12 11912 #define SDMA4_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x13 11913 #define SDMA4_STATUS4_REG__IDLE_MASK 0x00000001L 11914 #define SDMA4_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L 11915 #define SDMA4_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L 11916 #define SDMA4_STATUS4_REG__MMHUB_RD_OUTSTANDING_MASK 0x00000010L 11917 #define SDMA4_STATUS4_REG__MMHUB_WR_OUTSTANDING_MASK 0x00000020L 11918 #define SDMA4_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000040L 11919 #define SDMA4_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000080L 11920 #define SDMA4_STATUS4_REG__REG_POLLING_MASK 0x00000100L 11921 #define SDMA4_STATUS4_REG__MEM_POLLING_MASK 0x00000200L 11922 #define SDMA4_STATUS4_REG__UTCL2_RD_XNACK_MASK 0x00000C00L 11923 #define SDMA4_STATUS4_REG__UTCL2_WR_XNACK_MASK 0x00003000L 11924 #define SDMA4_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x0003C000L 11925 #define SDMA4_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00040000L 11926 #define SDMA4_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00080000L 11927 //SDMA4_SCRATCH_RAM_DATA 11928 #define SDMA4_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 11929 #define SDMA4_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL 11930 //SDMA4_SCRATCH_RAM_ADDR 11931 #define SDMA4_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 11932 #define SDMA4_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL 11933 //SDMA4_CE_CTRL 11934 #define SDMA4_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 11935 #define SDMA4_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 11936 #define SDMA4_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5 11937 #define SDMA4_CE_CTRL__RESERVED__SHIFT 0x8 11938 #define SDMA4_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L 11939 #define SDMA4_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L 11940 #define SDMA4_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L 11941 #define SDMA4_CE_CTRL__RESERVED_MASK 0xFFFFFF00L 11942 //SDMA4_RAS_STATUS 11943 #define SDMA4_RAS_STATUS__RB_FETCH_ECC__SHIFT 0x0 11944 #define SDMA4_RAS_STATUS__IB_FETCH_ECC__SHIFT 0x1 11945 #define SDMA4_RAS_STATUS__F32_DATA_ECC__SHIFT 0x2 11946 #define SDMA4_RAS_STATUS__SEM_WPTR_ATOMIC_ECC__SHIFT 0x3 11947 #define SDMA4_RAS_STATUS__COPY_DATA_ECC__SHIFT 0x4 11948 #define SDMA4_RAS_STATUS__SRAM_ECC__SHIFT 0x5 11949 #define SDMA4_RAS_STATUS__RB_FETCH_NACK_GEN_ERR__SHIFT 0x8 11950 #define SDMA4_RAS_STATUS__IB_FETCH_NACK_GEN_ERR__SHIFT 0x9 11951 #define SDMA4_RAS_STATUS__F32_DATA_NACK_GEN_ERR__SHIFT 0xa 11952 #define SDMA4_RAS_STATUS__COPY_DATA_NACK_GEN_ERR__SHIFT 0xb 11953 #define SDMA4_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR__SHIFT 0xc 11954 #define SDMA4_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR__SHIFT 0xd 11955 #define SDMA4_RAS_STATUS__RB_FETCH_ECC_MASK 0x00000001L 11956 #define SDMA4_RAS_STATUS__IB_FETCH_ECC_MASK 0x00000002L 11957 #define SDMA4_RAS_STATUS__F32_DATA_ECC_MASK 0x00000004L 11958 #define SDMA4_RAS_STATUS__SEM_WPTR_ATOMIC_ECC_MASK 0x00000008L 11959 #define SDMA4_RAS_STATUS__COPY_DATA_ECC_MASK 0x00000010L 11960 #define SDMA4_RAS_STATUS__SRAM_ECC_MASK 0x00000020L 11961 #define SDMA4_RAS_STATUS__RB_FETCH_NACK_GEN_ERR_MASK 0x00000100L 11962 #define SDMA4_RAS_STATUS__IB_FETCH_NACK_GEN_ERR_MASK 0x00000200L 11963 #define SDMA4_RAS_STATUS__F32_DATA_NACK_GEN_ERR_MASK 0x00000400L 11964 #define SDMA4_RAS_STATUS__COPY_DATA_NACK_GEN_ERR_MASK 0x00000800L 11965 #define SDMA4_RAS_STATUS__WRRET_DATA_NACK_GEN_ERR_MASK 0x00001000L 11966 #define SDMA4_RAS_STATUS__WPTR_RPTR_ATOMIC_NACK_GEN_ERR_MASK 0x00002000L 11967 //SDMA4_CLK_STATUS 11968 #define SDMA4_CLK_STATUS__DYN_CLK__SHIFT 0x0 11969 #define SDMA4_CLK_STATUS__PTR_CLK__SHIFT 0x1 11970 #define SDMA4_CLK_STATUS__REG_CLK__SHIFT 0x2 11971 #define SDMA4_CLK_STATUS__F32_CLK__SHIFT 0x3 11972 #define SDMA4_CLK_STATUS__DYN_CLK_MASK 0x00000001L 11973 #define SDMA4_CLK_STATUS__PTR_CLK_MASK 0x00000002L 11974 #define SDMA4_CLK_STATUS__REG_CLK_MASK 0x00000004L 11975 #define SDMA4_CLK_STATUS__F32_CLK_MASK 0x00000008L 11976 //SDMA4_GFX_RB_CNTL 11977 #define SDMA4_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 11978 #define SDMA4_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 11979 #define SDMA4_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 11980 #define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 11981 #define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 11982 #define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 11983 #define SDMA4_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 11984 #define SDMA4_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 11985 #define SDMA4_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 11986 #define SDMA4_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL 11987 #define SDMA4_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 11988 #define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 11989 #define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 11990 #define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 11991 #define SDMA4_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 11992 #define SDMA4_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 11993 //SDMA4_GFX_RB_BASE 11994 #define SDMA4_GFX_RB_BASE__ADDR__SHIFT 0x0 11995 #define SDMA4_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 11996 //SDMA4_GFX_RB_BASE_HI 11997 #define SDMA4_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 11998 #define SDMA4_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 11999 //SDMA4_GFX_RB_RPTR 12000 #define SDMA4_GFX_RB_RPTR__OFFSET__SHIFT 0x0 12001 #define SDMA4_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 12002 //SDMA4_GFX_RB_RPTR_HI 12003 #define SDMA4_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 12004 #define SDMA4_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 12005 //SDMA4_GFX_RB_WPTR 12006 #define SDMA4_GFX_RB_WPTR__OFFSET__SHIFT 0x0 12007 #define SDMA4_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 12008 //SDMA4_GFX_RB_WPTR_HI 12009 #define SDMA4_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 12010 #define SDMA4_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 12011 //SDMA4_GFX_RB_WPTR_POLL_CNTL 12012 #define SDMA4_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 12013 #define SDMA4_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 12014 #define SDMA4_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 12015 #define SDMA4_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 12016 #define SDMA4_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 12017 #define SDMA4_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 12018 #define SDMA4_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 12019 #define SDMA4_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 12020 #define SDMA4_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 12021 #define SDMA4_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 12022 //SDMA4_GFX_RB_RPTR_ADDR_HI 12023 #define SDMA4_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 12024 #define SDMA4_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 12025 //SDMA4_GFX_RB_RPTR_ADDR_LO 12026 #define SDMA4_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 12027 #define SDMA4_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 12028 #define SDMA4_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 12029 #define SDMA4_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 12030 //SDMA4_GFX_IB_CNTL 12031 #define SDMA4_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 12032 #define SDMA4_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 12033 #define SDMA4_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 12034 #define SDMA4_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 12035 #define SDMA4_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 12036 #define SDMA4_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 12037 #define SDMA4_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 12038 #define SDMA4_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 12039 //SDMA4_GFX_IB_RPTR 12040 #define SDMA4_GFX_IB_RPTR__OFFSET__SHIFT 0x2 12041 #define SDMA4_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 12042 //SDMA4_GFX_IB_OFFSET 12043 #define SDMA4_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 12044 #define SDMA4_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 12045 //SDMA4_GFX_IB_BASE_LO 12046 #define SDMA4_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 12047 #define SDMA4_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 12048 //SDMA4_GFX_IB_BASE_HI 12049 #define SDMA4_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 12050 #define SDMA4_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 12051 //SDMA4_GFX_IB_SIZE 12052 #define SDMA4_GFX_IB_SIZE__SIZE__SHIFT 0x0 12053 #define SDMA4_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 12054 //SDMA4_GFX_SKIP_CNTL 12055 #define SDMA4_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 12056 #define SDMA4_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 12057 //SDMA4_GFX_CONTEXT_STATUS 12058 #define SDMA4_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 12059 #define SDMA4_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 12060 #define SDMA4_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 12061 #define SDMA4_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 12062 #define SDMA4_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 12063 #define SDMA4_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 12064 #define SDMA4_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 12065 #define SDMA4_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 12066 #define SDMA4_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 12067 #define SDMA4_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 12068 #define SDMA4_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 12069 #define SDMA4_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 12070 #define SDMA4_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 12071 #define SDMA4_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 12072 #define SDMA4_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 12073 #define SDMA4_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 12074 //SDMA4_GFX_DOORBELL 12075 #define SDMA4_GFX_DOORBELL__ENABLE__SHIFT 0x1c 12076 #define SDMA4_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 12077 #define SDMA4_GFX_DOORBELL__ENABLE_MASK 0x10000000L 12078 #define SDMA4_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 12079 //SDMA4_GFX_CONTEXT_CNTL 12080 #define SDMA4_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 12081 #define SDMA4_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 12082 #define SDMA4_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 12083 #define SDMA4_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0x0F000000L 12084 //SDMA4_GFX_STATUS 12085 #define SDMA4_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 12086 #define SDMA4_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 12087 #define SDMA4_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 12088 #define SDMA4_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 12089 //SDMA4_GFX_DOORBELL_LOG 12090 #define SDMA4_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 12091 #define SDMA4_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 12092 #define SDMA4_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 12093 #define SDMA4_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 12094 //SDMA4_GFX_WATERMARK 12095 #define SDMA4_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 12096 #define SDMA4_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 12097 #define SDMA4_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 12098 #define SDMA4_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 12099 //SDMA4_GFX_DOORBELL_OFFSET 12100 #define SDMA4_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 12101 #define SDMA4_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 12102 //SDMA4_GFX_CSA_ADDR_LO 12103 #define SDMA4_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 12104 #define SDMA4_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 12105 //SDMA4_GFX_CSA_ADDR_HI 12106 #define SDMA4_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 12107 #define SDMA4_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 12108 //SDMA4_GFX_IB_SUB_REMAIN 12109 #define SDMA4_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 12110 #define SDMA4_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 12111 //SDMA4_GFX_PREEMPT 12112 #define SDMA4_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 12113 #define SDMA4_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 12114 //SDMA4_GFX_DUMMY_REG 12115 #define SDMA4_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 12116 #define SDMA4_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 12117 //SDMA4_GFX_RB_WPTR_POLL_ADDR_HI 12118 #define SDMA4_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 12119 #define SDMA4_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 12120 //SDMA4_GFX_RB_WPTR_POLL_ADDR_LO 12121 #define SDMA4_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 12122 #define SDMA4_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 12123 //SDMA4_GFX_RB_AQL_CNTL 12124 #define SDMA4_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 12125 #define SDMA4_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 12126 #define SDMA4_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 12127 #define SDMA4_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 12128 #define SDMA4_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 12129 #define SDMA4_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 12130 //SDMA4_GFX_MINOR_PTR_UPDATE 12131 #define SDMA4_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 12132 #define SDMA4_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 12133 //SDMA4_GFX_MIDCMD_DATA0 12134 #define SDMA4_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 12135 #define SDMA4_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 12136 //SDMA4_GFX_MIDCMD_DATA1 12137 #define SDMA4_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 12138 #define SDMA4_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 12139 //SDMA4_GFX_MIDCMD_DATA2 12140 #define SDMA4_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 12141 #define SDMA4_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 12142 //SDMA4_GFX_MIDCMD_DATA3 12143 #define SDMA4_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 12144 #define SDMA4_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 12145 //SDMA4_GFX_MIDCMD_DATA4 12146 #define SDMA4_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 12147 #define SDMA4_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 12148 //SDMA4_GFX_MIDCMD_DATA5 12149 #define SDMA4_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 12150 #define SDMA4_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 12151 //SDMA4_GFX_MIDCMD_DATA6 12152 #define SDMA4_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 12153 #define SDMA4_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 12154 //SDMA4_GFX_MIDCMD_DATA7 12155 #define SDMA4_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 12156 #define SDMA4_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 12157 //SDMA4_GFX_MIDCMD_DATA8 12158 #define SDMA4_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 12159 #define SDMA4_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 12160 //SDMA4_GFX_MIDCMD_DATA9 12161 #define SDMA4_GFX_MIDCMD_DATA9__DATA9__SHIFT 0x0 12162 #define SDMA4_GFX_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 12163 //SDMA4_GFX_MIDCMD_DATA10 12164 #define SDMA4_GFX_MIDCMD_DATA10__DATA10__SHIFT 0x0 12165 #define SDMA4_GFX_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 12166 //SDMA4_GFX_MIDCMD_CNTL 12167 #define SDMA4_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 12168 #define SDMA4_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 12169 #define SDMA4_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 12170 #define SDMA4_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 12171 #define SDMA4_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 12172 #define SDMA4_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 12173 #define SDMA4_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 12174 #define SDMA4_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 12175 //SDMA4_PAGE_RB_CNTL 12176 #define SDMA4_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 12177 #define SDMA4_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 12178 #define SDMA4_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 12179 #define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 12180 #define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 12181 #define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 12182 #define SDMA4_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 12183 #define SDMA4_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 12184 #define SDMA4_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 12185 #define SDMA4_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL 12186 #define SDMA4_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 12187 #define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 12188 #define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 12189 #define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 12190 #define SDMA4_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 12191 #define SDMA4_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 12192 //SDMA4_PAGE_RB_BASE 12193 #define SDMA4_PAGE_RB_BASE__ADDR__SHIFT 0x0 12194 #define SDMA4_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 12195 //SDMA4_PAGE_RB_BASE_HI 12196 #define SDMA4_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 12197 #define SDMA4_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 12198 //SDMA4_PAGE_RB_RPTR 12199 #define SDMA4_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 12200 #define SDMA4_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 12201 //SDMA4_PAGE_RB_RPTR_HI 12202 #define SDMA4_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 12203 #define SDMA4_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 12204 //SDMA4_PAGE_RB_WPTR 12205 #define SDMA4_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 12206 #define SDMA4_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 12207 //SDMA4_PAGE_RB_WPTR_HI 12208 #define SDMA4_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 12209 #define SDMA4_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 12210 //SDMA4_PAGE_RB_WPTR_POLL_CNTL 12211 #define SDMA4_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 12212 #define SDMA4_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 12213 #define SDMA4_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 12214 #define SDMA4_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 12215 #define SDMA4_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 12216 #define SDMA4_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 12217 #define SDMA4_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 12218 #define SDMA4_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 12219 #define SDMA4_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 12220 #define SDMA4_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 12221 //SDMA4_PAGE_RB_RPTR_ADDR_HI 12222 #define SDMA4_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 12223 #define SDMA4_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 12224 //SDMA4_PAGE_RB_RPTR_ADDR_LO 12225 #define SDMA4_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 12226 #define SDMA4_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 12227 #define SDMA4_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 12228 #define SDMA4_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 12229 //SDMA4_PAGE_IB_CNTL 12230 #define SDMA4_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 12231 #define SDMA4_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 12232 #define SDMA4_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 12233 #define SDMA4_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 12234 #define SDMA4_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 12235 #define SDMA4_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 12236 #define SDMA4_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 12237 #define SDMA4_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 12238 //SDMA4_PAGE_IB_RPTR 12239 #define SDMA4_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 12240 #define SDMA4_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 12241 //SDMA4_PAGE_IB_OFFSET 12242 #define SDMA4_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 12243 #define SDMA4_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 12244 //SDMA4_PAGE_IB_BASE_LO 12245 #define SDMA4_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 12246 #define SDMA4_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 12247 //SDMA4_PAGE_IB_BASE_HI 12248 #define SDMA4_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 12249 #define SDMA4_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 12250 //SDMA4_PAGE_IB_SIZE 12251 #define SDMA4_PAGE_IB_SIZE__SIZE__SHIFT 0x0 12252 #define SDMA4_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 12253 //SDMA4_PAGE_SKIP_CNTL 12254 #define SDMA4_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 12255 #define SDMA4_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 12256 //SDMA4_PAGE_CONTEXT_STATUS 12257 #define SDMA4_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 12258 #define SDMA4_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 12259 #define SDMA4_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 12260 #define SDMA4_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 12261 #define SDMA4_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 12262 #define SDMA4_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 12263 #define SDMA4_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 12264 #define SDMA4_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 12265 #define SDMA4_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 12266 #define SDMA4_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 12267 #define SDMA4_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 12268 #define SDMA4_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 12269 #define SDMA4_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 12270 #define SDMA4_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 12271 #define SDMA4_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 12272 #define SDMA4_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 12273 //SDMA4_PAGE_DOORBELL 12274 #define SDMA4_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 12275 #define SDMA4_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 12276 #define SDMA4_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 12277 #define SDMA4_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 12278 //SDMA4_PAGE_STATUS 12279 #define SDMA4_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 12280 #define SDMA4_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 12281 #define SDMA4_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 12282 #define SDMA4_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 12283 //SDMA4_PAGE_DOORBELL_LOG 12284 #define SDMA4_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 12285 #define SDMA4_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 12286 #define SDMA4_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 12287 #define SDMA4_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 12288 //SDMA4_PAGE_WATERMARK 12289 #define SDMA4_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 12290 #define SDMA4_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 12291 #define SDMA4_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 12292 #define SDMA4_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 12293 //SDMA4_PAGE_DOORBELL_OFFSET 12294 #define SDMA4_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 12295 #define SDMA4_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 12296 //SDMA4_PAGE_CSA_ADDR_LO 12297 #define SDMA4_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 12298 #define SDMA4_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 12299 //SDMA4_PAGE_CSA_ADDR_HI 12300 #define SDMA4_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 12301 #define SDMA4_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 12302 //SDMA4_PAGE_IB_SUB_REMAIN 12303 #define SDMA4_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 12304 #define SDMA4_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 12305 //SDMA4_PAGE_PREEMPT 12306 #define SDMA4_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 12307 #define SDMA4_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 12308 //SDMA4_PAGE_DUMMY_REG 12309 #define SDMA4_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 12310 #define SDMA4_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 12311 //SDMA4_PAGE_RB_WPTR_POLL_ADDR_HI 12312 #define SDMA4_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 12313 #define SDMA4_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 12314 //SDMA4_PAGE_RB_WPTR_POLL_ADDR_LO 12315 #define SDMA4_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 12316 #define SDMA4_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 12317 //SDMA4_PAGE_RB_AQL_CNTL 12318 #define SDMA4_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 12319 #define SDMA4_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 12320 #define SDMA4_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 12321 #define SDMA4_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 12322 #define SDMA4_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 12323 #define SDMA4_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 12324 //SDMA4_PAGE_MINOR_PTR_UPDATE 12325 #define SDMA4_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 12326 #define SDMA4_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 12327 //SDMA4_PAGE_MIDCMD_DATA0 12328 #define SDMA4_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 12329 #define SDMA4_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 12330 //SDMA4_PAGE_MIDCMD_DATA1 12331 #define SDMA4_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 12332 #define SDMA4_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 12333 //SDMA4_PAGE_MIDCMD_DATA2 12334 #define SDMA4_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 12335 #define SDMA4_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 12336 //SDMA4_PAGE_MIDCMD_DATA3 12337 #define SDMA4_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 12338 #define SDMA4_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 12339 //SDMA4_PAGE_MIDCMD_DATA4 12340 #define SDMA4_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 12341 #define SDMA4_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 12342 //SDMA4_PAGE_MIDCMD_DATA5 12343 #define SDMA4_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 12344 #define SDMA4_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 12345 //SDMA4_PAGE_MIDCMD_DATA6 12346 #define SDMA4_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 12347 #define SDMA4_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 12348 //SDMA4_PAGE_MIDCMD_DATA7 12349 #define SDMA4_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 12350 #define SDMA4_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 12351 //SDMA4_PAGE_MIDCMD_DATA8 12352 #define SDMA4_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 12353 #define SDMA4_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 12354 //SDMA4_PAGE_MIDCMD_DATA9 12355 #define SDMA4_PAGE_MIDCMD_DATA9__DATA9__SHIFT 0x0 12356 #define SDMA4_PAGE_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 12357 //SDMA4_PAGE_MIDCMD_DATA10 12358 #define SDMA4_PAGE_MIDCMD_DATA10__DATA10__SHIFT 0x0 12359 #define SDMA4_PAGE_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 12360 //SDMA4_PAGE_MIDCMD_CNTL 12361 #define SDMA4_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 12362 #define SDMA4_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 12363 #define SDMA4_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 12364 #define SDMA4_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 12365 #define SDMA4_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 12366 #define SDMA4_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 12367 #define SDMA4_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 12368 #define SDMA4_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 12369 //SDMA4_RLC0_RB_CNTL 12370 #define SDMA4_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 12371 #define SDMA4_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 12372 #define SDMA4_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 12373 #define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 12374 #define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 12375 #define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 12376 #define SDMA4_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 12377 #define SDMA4_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 12378 #define SDMA4_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 12379 #define SDMA4_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL 12380 #define SDMA4_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 12381 #define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 12382 #define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 12383 #define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 12384 #define SDMA4_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 12385 #define SDMA4_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 12386 //SDMA4_RLC0_RB_BASE 12387 #define SDMA4_RLC0_RB_BASE__ADDR__SHIFT 0x0 12388 #define SDMA4_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 12389 //SDMA4_RLC0_RB_BASE_HI 12390 #define SDMA4_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 12391 #define SDMA4_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 12392 //SDMA4_RLC0_RB_RPTR 12393 #define SDMA4_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 12394 #define SDMA4_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 12395 //SDMA4_RLC0_RB_RPTR_HI 12396 #define SDMA4_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 12397 #define SDMA4_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 12398 //SDMA4_RLC0_RB_WPTR 12399 #define SDMA4_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 12400 #define SDMA4_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 12401 //SDMA4_RLC0_RB_WPTR_HI 12402 #define SDMA4_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 12403 #define SDMA4_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 12404 //SDMA4_RLC0_RB_WPTR_POLL_CNTL 12405 #define SDMA4_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 12406 #define SDMA4_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 12407 #define SDMA4_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 12408 #define SDMA4_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 12409 #define SDMA4_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 12410 #define SDMA4_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 12411 #define SDMA4_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 12412 #define SDMA4_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 12413 #define SDMA4_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 12414 #define SDMA4_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 12415 //SDMA4_RLC0_RB_RPTR_ADDR_HI 12416 #define SDMA4_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 12417 #define SDMA4_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 12418 //SDMA4_RLC0_RB_RPTR_ADDR_LO 12419 #define SDMA4_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 12420 #define SDMA4_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 12421 #define SDMA4_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 12422 #define SDMA4_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 12423 //SDMA4_RLC0_IB_CNTL 12424 #define SDMA4_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 12425 #define SDMA4_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 12426 #define SDMA4_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 12427 #define SDMA4_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 12428 #define SDMA4_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 12429 #define SDMA4_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 12430 #define SDMA4_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 12431 #define SDMA4_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 12432 //SDMA4_RLC0_IB_RPTR 12433 #define SDMA4_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 12434 #define SDMA4_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 12435 //SDMA4_RLC0_IB_OFFSET 12436 #define SDMA4_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 12437 #define SDMA4_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 12438 //SDMA4_RLC0_IB_BASE_LO 12439 #define SDMA4_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 12440 #define SDMA4_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 12441 //SDMA4_RLC0_IB_BASE_HI 12442 #define SDMA4_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 12443 #define SDMA4_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 12444 //SDMA4_RLC0_IB_SIZE 12445 #define SDMA4_RLC0_IB_SIZE__SIZE__SHIFT 0x0 12446 #define SDMA4_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 12447 //SDMA4_RLC0_SKIP_CNTL 12448 #define SDMA4_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 12449 #define SDMA4_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 12450 //SDMA4_RLC0_CONTEXT_STATUS 12451 #define SDMA4_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 12452 #define SDMA4_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 12453 #define SDMA4_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 12454 #define SDMA4_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 12455 #define SDMA4_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 12456 #define SDMA4_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 12457 #define SDMA4_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 12458 #define SDMA4_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 12459 #define SDMA4_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 12460 #define SDMA4_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 12461 #define SDMA4_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 12462 #define SDMA4_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 12463 #define SDMA4_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 12464 #define SDMA4_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 12465 #define SDMA4_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 12466 #define SDMA4_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 12467 //SDMA4_RLC0_DOORBELL 12468 #define SDMA4_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 12469 #define SDMA4_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 12470 #define SDMA4_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 12471 #define SDMA4_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 12472 //SDMA4_RLC0_STATUS 12473 #define SDMA4_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 12474 #define SDMA4_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 12475 #define SDMA4_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 12476 #define SDMA4_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 12477 //SDMA4_RLC0_DOORBELL_LOG 12478 #define SDMA4_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 12479 #define SDMA4_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 12480 #define SDMA4_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 12481 #define SDMA4_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 12482 //SDMA4_RLC0_WATERMARK 12483 #define SDMA4_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 12484 #define SDMA4_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 12485 #define SDMA4_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 12486 #define SDMA4_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 12487 //SDMA4_RLC0_DOORBELL_OFFSET 12488 #define SDMA4_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 12489 #define SDMA4_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 12490 //SDMA4_RLC0_CSA_ADDR_LO 12491 #define SDMA4_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 12492 #define SDMA4_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 12493 //SDMA4_RLC0_CSA_ADDR_HI 12494 #define SDMA4_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 12495 #define SDMA4_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 12496 //SDMA4_RLC0_IB_SUB_REMAIN 12497 #define SDMA4_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 12498 #define SDMA4_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 12499 //SDMA4_RLC0_PREEMPT 12500 #define SDMA4_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 12501 #define SDMA4_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 12502 //SDMA4_RLC0_DUMMY_REG 12503 #define SDMA4_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 12504 #define SDMA4_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 12505 //SDMA4_RLC0_RB_WPTR_POLL_ADDR_HI 12506 #define SDMA4_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 12507 #define SDMA4_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 12508 //SDMA4_RLC0_RB_WPTR_POLL_ADDR_LO 12509 #define SDMA4_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 12510 #define SDMA4_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 12511 //SDMA4_RLC0_RB_AQL_CNTL 12512 #define SDMA4_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 12513 #define SDMA4_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 12514 #define SDMA4_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 12515 #define SDMA4_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 12516 #define SDMA4_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 12517 #define SDMA4_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 12518 //SDMA4_RLC0_MINOR_PTR_UPDATE 12519 #define SDMA4_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 12520 #define SDMA4_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 12521 //SDMA4_RLC0_MIDCMD_DATA0 12522 #define SDMA4_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 12523 #define SDMA4_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 12524 //SDMA4_RLC0_MIDCMD_DATA1 12525 #define SDMA4_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 12526 #define SDMA4_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 12527 //SDMA4_RLC0_MIDCMD_DATA2 12528 #define SDMA4_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 12529 #define SDMA4_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 12530 //SDMA4_RLC0_MIDCMD_DATA3 12531 #define SDMA4_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 12532 #define SDMA4_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 12533 //SDMA4_RLC0_MIDCMD_DATA4 12534 #define SDMA4_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 12535 #define SDMA4_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 12536 //SDMA4_RLC0_MIDCMD_DATA5 12537 #define SDMA4_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 12538 #define SDMA4_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 12539 //SDMA4_RLC0_MIDCMD_DATA6 12540 #define SDMA4_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 12541 #define SDMA4_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 12542 //SDMA4_RLC0_MIDCMD_DATA7 12543 #define SDMA4_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 12544 #define SDMA4_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 12545 //SDMA4_RLC0_MIDCMD_DATA8 12546 #define SDMA4_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 12547 #define SDMA4_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 12548 //SDMA4_RLC0_MIDCMD_DATA9 12549 #define SDMA4_RLC0_MIDCMD_DATA9__DATA9__SHIFT 0x0 12550 #define SDMA4_RLC0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 12551 //SDMA4_RLC0_MIDCMD_DATA10 12552 #define SDMA4_RLC0_MIDCMD_DATA10__DATA10__SHIFT 0x0 12553 #define SDMA4_RLC0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 12554 //SDMA4_RLC0_MIDCMD_CNTL 12555 #define SDMA4_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 12556 #define SDMA4_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 12557 #define SDMA4_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 12558 #define SDMA4_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 12559 #define SDMA4_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 12560 #define SDMA4_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 12561 #define SDMA4_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 12562 #define SDMA4_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 12563 //SDMA4_RLC1_RB_CNTL 12564 #define SDMA4_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 12565 #define SDMA4_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 12566 #define SDMA4_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 12567 #define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 12568 #define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 12569 #define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 12570 #define SDMA4_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 12571 #define SDMA4_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 12572 #define SDMA4_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 12573 #define SDMA4_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL 12574 #define SDMA4_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 12575 #define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 12576 #define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 12577 #define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 12578 #define SDMA4_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 12579 #define SDMA4_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 12580 //SDMA4_RLC1_RB_BASE 12581 #define SDMA4_RLC1_RB_BASE__ADDR__SHIFT 0x0 12582 #define SDMA4_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 12583 //SDMA4_RLC1_RB_BASE_HI 12584 #define SDMA4_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 12585 #define SDMA4_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 12586 //SDMA4_RLC1_RB_RPTR 12587 #define SDMA4_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 12588 #define SDMA4_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 12589 //SDMA4_RLC1_RB_RPTR_HI 12590 #define SDMA4_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 12591 #define SDMA4_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 12592 //SDMA4_RLC1_RB_WPTR 12593 #define SDMA4_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 12594 #define SDMA4_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 12595 //SDMA4_RLC1_RB_WPTR_HI 12596 #define SDMA4_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 12597 #define SDMA4_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 12598 //SDMA4_RLC1_RB_WPTR_POLL_CNTL 12599 #define SDMA4_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 12600 #define SDMA4_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 12601 #define SDMA4_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 12602 #define SDMA4_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 12603 #define SDMA4_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 12604 #define SDMA4_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 12605 #define SDMA4_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 12606 #define SDMA4_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 12607 #define SDMA4_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 12608 #define SDMA4_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 12609 //SDMA4_RLC1_RB_RPTR_ADDR_HI 12610 #define SDMA4_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 12611 #define SDMA4_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 12612 //SDMA4_RLC1_RB_RPTR_ADDR_LO 12613 #define SDMA4_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 12614 #define SDMA4_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 12615 #define SDMA4_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 12616 #define SDMA4_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 12617 //SDMA4_RLC1_IB_CNTL 12618 #define SDMA4_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 12619 #define SDMA4_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 12620 #define SDMA4_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 12621 #define SDMA4_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 12622 #define SDMA4_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 12623 #define SDMA4_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 12624 #define SDMA4_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 12625 #define SDMA4_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 12626 //SDMA4_RLC1_IB_RPTR 12627 #define SDMA4_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 12628 #define SDMA4_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 12629 //SDMA4_RLC1_IB_OFFSET 12630 #define SDMA4_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 12631 #define SDMA4_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 12632 //SDMA4_RLC1_IB_BASE_LO 12633 #define SDMA4_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 12634 #define SDMA4_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 12635 //SDMA4_RLC1_IB_BASE_HI 12636 #define SDMA4_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 12637 #define SDMA4_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 12638 //SDMA4_RLC1_IB_SIZE 12639 #define SDMA4_RLC1_IB_SIZE__SIZE__SHIFT 0x0 12640 #define SDMA4_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 12641 //SDMA4_RLC1_SKIP_CNTL 12642 #define SDMA4_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 12643 #define SDMA4_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 12644 //SDMA4_RLC1_CONTEXT_STATUS 12645 #define SDMA4_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 12646 #define SDMA4_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 12647 #define SDMA4_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 12648 #define SDMA4_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 12649 #define SDMA4_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 12650 #define SDMA4_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 12651 #define SDMA4_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 12652 #define SDMA4_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 12653 #define SDMA4_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 12654 #define SDMA4_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 12655 #define SDMA4_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 12656 #define SDMA4_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 12657 #define SDMA4_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 12658 #define SDMA4_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 12659 #define SDMA4_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 12660 #define SDMA4_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 12661 //SDMA4_RLC1_DOORBELL 12662 #define SDMA4_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 12663 #define SDMA4_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 12664 #define SDMA4_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 12665 #define SDMA4_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 12666 //SDMA4_RLC1_STATUS 12667 #define SDMA4_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 12668 #define SDMA4_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 12669 #define SDMA4_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 12670 #define SDMA4_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 12671 //SDMA4_RLC1_DOORBELL_LOG 12672 #define SDMA4_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 12673 #define SDMA4_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 12674 #define SDMA4_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 12675 #define SDMA4_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 12676 //SDMA4_RLC1_WATERMARK 12677 #define SDMA4_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 12678 #define SDMA4_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 12679 #define SDMA4_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 12680 #define SDMA4_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 12681 //SDMA4_RLC1_DOORBELL_OFFSET 12682 #define SDMA4_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 12683 #define SDMA4_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 12684 //SDMA4_RLC1_CSA_ADDR_LO 12685 #define SDMA4_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 12686 #define SDMA4_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 12687 //SDMA4_RLC1_CSA_ADDR_HI 12688 #define SDMA4_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 12689 #define SDMA4_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 12690 //SDMA4_RLC1_IB_SUB_REMAIN 12691 #define SDMA4_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 12692 #define SDMA4_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 12693 //SDMA4_RLC1_PREEMPT 12694 #define SDMA4_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 12695 #define SDMA4_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 12696 //SDMA4_RLC1_DUMMY_REG 12697 #define SDMA4_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 12698 #define SDMA4_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 12699 //SDMA4_RLC1_RB_WPTR_POLL_ADDR_HI 12700 #define SDMA4_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 12701 #define SDMA4_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 12702 //SDMA4_RLC1_RB_WPTR_POLL_ADDR_LO 12703 #define SDMA4_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 12704 #define SDMA4_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 12705 //SDMA4_RLC1_RB_AQL_CNTL 12706 #define SDMA4_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 12707 #define SDMA4_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 12708 #define SDMA4_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 12709 #define SDMA4_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 12710 #define SDMA4_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 12711 #define SDMA4_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 12712 //SDMA4_RLC1_MINOR_PTR_UPDATE 12713 #define SDMA4_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 12714 #define SDMA4_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 12715 //SDMA4_RLC1_MIDCMD_DATA0 12716 #define SDMA4_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 12717 #define SDMA4_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 12718 //SDMA4_RLC1_MIDCMD_DATA1 12719 #define SDMA4_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 12720 #define SDMA4_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 12721 //SDMA4_RLC1_MIDCMD_DATA2 12722 #define SDMA4_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 12723 #define SDMA4_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 12724 //SDMA4_RLC1_MIDCMD_DATA3 12725 #define SDMA4_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 12726 #define SDMA4_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 12727 //SDMA4_RLC1_MIDCMD_DATA4 12728 #define SDMA4_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 12729 #define SDMA4_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 12730 //SDMA4_RLC1_MIDCMD_DATA5 12731 #define SDMA4_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 12732 #define SDMA4_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 12733 //SDMA4_RLC1_MIDCMD_DATA6 12734 #define SDMA4_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 12735 #define SDMA4_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 12736 //SDMA4_RLC1_MIDCMD_DATA7 12737 #define SDMA4_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 12738 #define SDMA4_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 12739 //SDMA4_RLC1_MIDCMD_DATA8 12740 #define SDMA4_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 12741 #define SDMA4_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 12742 //SDMA4_RLC1_MIDCMD_DATA9 12743 #define SDMA4_RLC1_MIDCMD_DATA9__DATA9__SHIFT 0x0 12744 #define SDMA4_RLC1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 12745 //SDMA4_RLC1_MIDCMD_DATA10 12746 #define SDMA4_RLC1_MIDCMD_DATA10__DATA10__SHIFT 0x0 12747 #define SDMA4_RLC1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 12748 //SDMA4_RLC1_MIDCMD_CNTL 12749 #define SDMA4_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 12750 #define SDMA4_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 12751 #define SDMA4_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 12752 #define SDMA4_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 12753 #define SDMA4_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 12754 #define SDMA4_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 12755 #define SDMA4_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 12756 #define SDMA4_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 12757 //SDMA4_RLC2_RB_CNTL 12758 #define SDMA4_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 12759 #define SDMA4_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 12760 #define SDMA4_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 12761 #define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 12762 #define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 12763 #define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 12764 #define SDMA4_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 12765 #define SDMA4_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 12766 #define SDMA4_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L 12767 #define SDMA4_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL 12768 #define SDMA4_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 12769 #define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 12770 #define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 12771 #define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 12772 #define SDMA4_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L 12773 #define SDMA4_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L 12774 //SDMA4_RLC2_RB_BASE 12775 #define SDMA4_RLC2_RB_BASE__ADDR__SHIFT 0x0 12776 #define SDMA4_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL 12777 //SDMA4_RLC2_RB_BASE_HI 12778 #define SDMA4_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 12779 #define SDMA4_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 12780 //SDMA4_RLC2_RB_RPTR 12781 #define SDMA4_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 12782 #define SDMA4_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 12783 //SDMA4_RLC2_RB_RPTR_HI 12784 #define SDMA4_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 12785 #define SDMA4_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 12786 //SDMA4_RLC2_RB_WPTR 12787 #define SDMA4_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 12788 #define SDMA4_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 12789 //SDMA4_RLC2_RB_WPTR_HI 12790 #define SDMA4_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 12791 #define SDMA4_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 12792 //SDMA4_RLC2_RB_WPTR_POLL_CNTL 12793 #define SDMA4_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 12794 #define SDMA4_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 12795 #define SDMA4_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 12796 #define SDMA4_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 12797 #define SDMA4_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 12798 #define SDMA4_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 12799 #define SDMA4_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 12800 #define SDMA4_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 12801 #define SDMA4_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 12802 #define SDMA4_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 12803 //SDMA4_RLC2_RB_RPTR_ADDR_HI 12804 #define SDMA4_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 12805 #define SDMA4_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 12806 //SDMA4_RLC2_RB_RPTR_ADDR_LO 12807 #define SDMA4_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 12808 #define SDMA4_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 12809 #define SDMA4_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 12810 #define SDMA4_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 12811 //SDMA4_RLC2_IB_CNTL 12812 #define SDMA4_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 12813 #define SDMA4_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 12814 #define SDMA4_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 12815 #define SDMA4_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 12816 #define SDMA4_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L 12817 #define SDMA4_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 12818 #define SDMA4_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 12819 #define SDMA4_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L 12820 //SDMA4_RLC2_IB_RPTR 12821 #define SDMA4_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 12822 #define SDMA4_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL 12823 //SDMA4_RLC2_IB_OFFSET 12824 #define SDMA4_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 12825 #define SDMA4_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 12826 //SDMA4_RLC2_IB_BASE_LO 12827 #define SDMA4_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 12828 #define SDMA4_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 12829 //SDMA4_RLC2_IB_BASE_HI 12830 #define SDMA4_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 12831 #define SDMA4_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 12832 //SDMA4_RLC2_IB_SIZE 12833 #define SDMA4_RLC2_IB_SIZE__SIZE__SHIFT 0x0 12834 #define SDMA4_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL 12835 //SDMA4_RLC2_SKIP_CNTL 12836 #define SDMA4_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 12837 #define SDMA4_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 12838 //SDMA4_RLC2_CONTEXT_STATUS 12839 #define SDMA4_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 12840 #define SDMA4_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 12841 #define SDMA4_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 12842 #define SDMA4_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 12843 #define SDMA4_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 12844 #define SDMA4_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 12845 #define SDMA4_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 12846 #define SDMA4_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 12847 #define SDMA4_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 12848 #define SDMA4_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L 12849 #define SDMA4_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 12850 #define SDMA4_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 12851 #define SDMA4_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 12852 #define SDMA4_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 12853 #define SDMA4_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 12854 #define SDMA4_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 12855 //SDMA4_RLC2_DOORBELL 12856 #define SDMA4_RLC2_DOORBELL__ENABLE__SHIFT 0x1c 12857 #define SDMA4_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e 12858 #define SDMA4_RLC2_DOORBELL__ENABLE_MASK 0x10000000L 12859 #define SDMA4_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L 12860 //SDMA4_RLC2_STATUS 12861 #define SDMA4_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 12862 #define SDMA4_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 12863 #define SDMA4_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 12864 #define SDMA4_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 12865 //SDMA4_RLC2_DOORBELL_LOG 12866 #define SDMA4_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 12867 #define SDMA4_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 12868 #define SDMA4_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 12869 #define SDMA4_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 12870 //SDMA4_RLC2_WATERMARK 12871 #define SDMA4_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 12872 #define SDMA4_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 12873 #define SDMA4_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 12874 #define SDMA4_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 12875 //SDMA4_RLC2_DOORBELL_OFFSET 12876 #define SDMA4_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 12877 #define SDMA4_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 12878 //SDMA4_RLC2_CSA_ADDR_LO 12879 #define SDMA4_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 12880 #define SDMA4_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 12881 //SDMA4_RLC2_CSA_ADDR_HI 12882 #define SDMA4_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 12883 #define SDMA4_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 12884 //SDMA4_RLC2_IB_SUB_REMAIN 12885 #define SDMA4_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 12886 #define SDMA4_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 12887 //SDMA4_RLC2_PREEMPT 12888 #define SDMA4_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 12889 #define SDMA4_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L 12890 //SDMA4_RLC2_DUMMY_REG 12891 #define SDMA4_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 12892 #define SDMA4_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 12893 //SDMA4_RLC2_RB_WPTR_POLL_ADDR_HI 12894 #define SDMA4_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 12895 #define SDMA4_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 12896 //SDMA4_RLC2_RB_WPTR_POLL_ADDR_LO 12897 #define SDMA4_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 12898 #define SDMA4_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 12899 //SDMA4_RLC2_RB_AQL_CNTL 12900 #define SDMA4_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 12901 #define SDMA4_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 12902 #define SDMA4_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 12903 #define SDMA4_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 12904 #define SDMA4_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 12905 #define SDMA4_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 12906 //SDMA4_RLC2_MINOR_PTR_UPDATE 12907 #define SDMA4_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 12908 #define SDMA4_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 12909 //SDMA4_RLC2_MIDCMD_DATA0 12910 #define SDMA4_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 12911 #define SDMA4_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 12912 //SDMA4_RLC2_MIDCMD_DATA1 12913 #define SDMA4_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 12914 #define SDMA4_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 12915 //SDMA4_RLC2_MIDCMD_DATA2 12916 #define SDMA4_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 12917 #define SDMA4_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 12918 //SDMA4_RLC2_MIDCMD_DATA3 12919 #define SDMA4_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 12920 #define SDMA4_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 12921 //SDMA4_RLC2_MIDCMD_DATA4 12922 #define SDMA4_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 12923 #define SDMA4_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 12924 //SDMA4_RLC2_MIDCMD_DATA5 12925 #define SDMA4_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 12926 #define SDMA4_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 12927 //SDMA4_RLC2_MIDCMD_DATA6 12928 #define SDMA4_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 12929 #define SDMA4_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 12930 //SDMA4_RLC2_MIDCMD_DATA7 12931 #define SDMA4_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 12932 #define SDMA4_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 12933 //SDMA4_RLC2_MIDCMD_DATA8 12934 #define SDMA4_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 12935 #define SDMA4_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 12936 //SDMA4_RLC2_MIDCMD_DATA9 12937 #define SDMA4_RLC2_MIDCMD_DATA9__DATA9__SHIFT 0x0 12938 #define SDMA4_RLC2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 12939 //SDMA4_RLC2_MIDCMD_DATA10 12940 #define SDMA4_RLC2_MIDCMD_DATA10__DATA10__SHIFT 0x0 12941 #define SDMA4_RLC2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 12942 //SDMA4_RLC2_MIDCMD_CNTL 12943 #define SDMA4_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 12944 #define SDMA4_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 12945 #define SDMA4_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 12946 #define SDMA4_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 12947 #define SDMA4_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 12948 #define SDMA4_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 12949 #define SDMA4_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 12950 #define SDMA4_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 12951 //SDMA4_RLC3_RB_CNTL 12952 #define SDMA4_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 12953 #define SDMA4_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 12954 #define SDMA4_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 12955 #define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 12956 #define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 12957 #define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 12958 #define SDMA4_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 12959 #define SDMA4_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 12960 #define SDMA4_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L 12961 #define SDMA4_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL 12962 #define SDMA4_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 12963 #define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 12964 #define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 12965 #define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 12966 #define SDMA4_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L 12967 #define SDMA4_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L 12968 //SDMA4_RLC3_RB_BASE 12969 #define SDMA4_RLC3_RB_BASE__ADDR__SHIFT 0x0 12970 #define SDMA4_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL 12971 //SDMA4_RLC3_RB_BASE_HI 12972 #define SDMA4_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 12973 #define SDMA4_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 12974 //SDMA4_RLC3_RB_RPTR 12975 #define SDMA4_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 12976 #define SDMA4_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 12977 //SDMA4_RLC3_RB_RPTR_HI 12978 #define SDMA4_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 12979 #define SDMA4_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 12980 //SDMA4_RLC3_RB_WPTR 12981 #define SDMA4_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 12982 #define SDMA4_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 12983 //SDMA4_RLC3_RB_WPTR_HI 12984 #define SDMA4_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 12985 #define SDMA4_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 12986 //SDMA4_RLC3_RB_WPTR_POLL_CNTL 12987 #define SDMA4_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 12988 #define SDMA4_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 12989 #define SDMA4_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 12990 #define SDMA4_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 12991 #define SDMA4_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 12992 #define SDMA4_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 12993 #define SDMA4_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 12994 #define SDMA4_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 12995 #define SDMA4_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 12996 #define SDMA4_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 12997 //SDMA4_RLC3_RB_RPTR_ADDR_HI 12998 #define SDMA4_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 12999 #define SDMA4_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 13000 //SDMA4_RLC3_RB_RPTR_ADDR_LO 13001 #define SDMA4_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 13002 #define SDMA4_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 13003 #define SDMA4_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 13004 #define SDMA4_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 13005 //SDMA4_RLC3_IB_CNTL 13006 #define SDMA4_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 13007 #define SDMA4_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 13008 #define SDMA4_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 13009 #define SDMA4_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 13010 #define SDMA4_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L 13011 #define SDMA4_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 13012 #define SDMA4_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 13013 #define SDMA4_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L 13014 //SDMA4_RLC3_IB_RPTR 13015 #define SDMA4_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 13016 #define SDMA4_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL 13017 //SDMA4_RLC3_IB_OFFSET 13018 #define SDMA4_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 13019 #define SDMA4_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 13020 //SDMA4_RLC3_IB_BASE_LO 13021 #define SDMA4_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 13022 #define SDMA4_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 13023 //SDMA4_RLC3_IB_BASE_HI 13024 #define SDMA4_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 13025 #define SDMA4_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 13026 //SDMA4_RLC3_IB_SIZE 13027 #define SDMA4_RLC3_IB_SIZE__SIZE__SHIFT 0x0 13028 #define SDMA4_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL 13029 //SDMA4_RLC3_SKIP_CNTL 13030 #define SDMA4_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 13031 #define SDMA4_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 13032 //SDMA4_RLC3_CONTEXT_STATUS 13033 #define SDMA4_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 13034 #define SDMA4_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 13035 #define SDMA4_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 13036 #define SDMA4_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 13037 #define SDMA4_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 13038 #define SDMA4_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 13039 #define SDMA4_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 13040 #define SDMA4_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 13041 #define SDMA4_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 13042 #define SDMA4_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L 13043 #define SDMA4_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 13044 #define SDMA4_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 13045 #define SDMA4_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 13046 #define SDMA4_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 13047 #define SDMA4_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 13048 #define SDMA4_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 13049 //SDMA4_RLC3_DOORBELL 13050 #define SDMA4_RLC3_DOORBELL__ENABLE__SHIFT 0x1c 13051 #define SDMA4_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e 13052 #define SDMA4_RLC3_DOORBELL__ENABLE_MASK 0x10000000L 13053 #define SDMA4_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L 13054 //SDMA4_RLC3_STATUS 13055 #define SDMA4_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 13056 #define SDMA4_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 13057 #define SDMA4_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 13058 #define SDMA4_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 13059 //SDMA4_RLC3_DOORBELL_LOG 13060 #define SDMA4_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 13061 #define SDMA4_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 13062 #define SDMA4_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 13063 #define SDMA4_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 13064 //SDMA4_RLC3_WATERMARK 13065 #define SDMA4_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 13066 #define SDMA4_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 13067 #define SDMA4_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 13068 #define SDMA4_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 13069 //SDMA4_RLC3_DOORBELL_OFFSET 13070 #define SDMA4_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 13071 #define SDMA4_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 13072 //SDMA4_RLC3_CSA_ADDR_LO 13073 #define SDMA4_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 13074 #define SDMA4_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 13075 //SDMA4_RLC3_CSA_ADDR_HI 13076 #define SDMA4_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 13077 #define SDMA4_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 13078 //SDMA4_RLC3_IB_SUB_REMAIN 13079 #define SDMA4_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 13080 #define SDMA4_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 13081 //SDMA4_RLC3_PREEMPT 13082 #define SDMA4_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 13083 #define SDMA4_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L 13084 //SDMA4_RLC3_DUMMY_REG 13085 #define SDMA4_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 13086 #define SDMA4_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 13087 //SDMA4_RLC3_RB_WPTR_POLL_ADDR_HI 13088 #define SDMA4_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 13089 #define SDMA4_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 13090 //SDMA4_RLC3_RB_WPTR_POLL_ADDR_LO 13091 #define SDMA4_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 13092 #define SDMA4_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 13093 //SDMA4_RLC3_RB_AQL_CNTL 13094 #define SDMA4_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 13095 #define SDMA4_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 13096 #define SDMA4_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 13097 #define SDMA4_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 13098 #define SDMA4_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 13099 #define SDMA4_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 13100 //SDMA4_RLC3_MINOR_PTR_UPDATE 13101 #define SDMA4_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 13102 #define SDMA4_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 13103 //SDMA4_RLC3_MIDCMD_DATA0 13104 #define SDMA4_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 13105 #define SDMA4_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 13106 //SDMA4_RLC3_MIDCMD_DATA1 13107 #define SDMA4_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 13108 #define SDMA4_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 13109 //SDMA4_RLC3_MIDCMD_DATA2 13110 #define SDMA4_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 13111 #define SDMA4_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 13112 //SDMA4_RLC3_MIDCMD_DATA3 13113 #define SDMA4_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 13114 #define SDMA4_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 13115 //SDMA4_RLC3_MIDCMD_DATA4 13116 #define SDMA4_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 13117 #define SDMA4_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 13118 //SDMA4_RLC3_MIDCMD_DATA5 13119 #define SDMA4_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 13120 #define SDMA4_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 13121 //SDMA4_RLC3_MIDCMD_DATA6 13122 #define SDMA4_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 13123 #define SDMA4_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 13124 //SDMA4_RLC3_MIDCMD_DATA7 13125 #define SDMA4_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 13126 #define SDMA4_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 13127 //SDMA4_RLC3_MIDCMD_DATA8 13128 #define SDMA4_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 13129 #define SDMA4_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 13130 //SDMA4_RLC3_MIDCMD_DATA9 13131 #define SDMA4_RLC3_MIDCMD_DATA9__DATA9__SHIFT 0x0 13132 #define SDMA4_RLC3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 13133 //SDMA4_RLC3_MIDCMD_DATA10 13134 #define SDMA4_RLC3_MIDCMD_DATA10__DATA10__SHIFT 0x0 13135 #define SDMA4_RLC3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 13136 //SDMA4_RLC3_MIDCMD_CNTL 13137 #define SDMA4_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 13138 #define SDMA4_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 13139 #define SDMA4_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 13140 #define SDMA4_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 13141 #define SDMA4_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 13142 #define SDMA4_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 13143 #define SDMA4_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 13144 #define SDMA4_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 13145 //SDMA4_RLC4_RB_CNTL 13146 #define SDMA4_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 13147 #define SDMA4_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 13148 #define SDMA4_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 13149 #define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 13150 #define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 13151 #define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 13152 #define SDMA4_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 13153 #define SDMA4_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 13154 #define SDMA4_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L 13155 #define SDMA4_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL 13156 #define SDMA4_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 13157 #define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 13158 #define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 13159 #define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 13160 #define SDMA4_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L 13161 #define SDMA4_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L 13162 //SDMA4_RLC4_RB_BASE 13163 #define SDMA4_RLC4_RB_BASE__ADDR__SHIFT 0x0 13164 #define SDMA4_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL 13165 //SDMA4_RLC4_RB_BASE_HI 13166 #define SDMA4_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 13167 #define SDMA4_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 13168 //SDMA4_RLC4_RB_RPTR 13169 #define SDMA4_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 13170 #define SDMA4_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 13171 //SDMA4_RLC4_RB_RPTR_HI 13172 #define SDMA4_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 13173 #define SDMA4_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 13174 //SDMA4_RLC4_RB_WPTR 13175 #define SDMA4_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 13176 #define SDMA4_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 13177 //SDMA4_RLC4_RB_WPTR_HI 13178 #define SDMA4_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 13179 #define SDMA4_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 13180 //SDMA4_RLC4_RB_WPTR_POLL_CNTL 13181 #define SDMA4_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 13182 #define SDMA4_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 13183 #define SDMA4_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 13184 #define SDMA4_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 13185 #define SDMA4_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 13186 #define SDMA4_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 13187 #define SDMA4_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 13188 #define SDMA4_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 13189 #define SDMA4_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 13190 #define SDMA4_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 13191 //SDMA4_RLC4_RB_RPTR_ADDR_HI 13192 #define SDMA4_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 13193 #define SDMA4_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 13194 //SDMA4_RLC4_RB_RPTR_ADDR_LO 13195 #define SDMA4_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 13196 #define SDMA4_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 13197 #define SDMA4_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 13198 #define SDMA4_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 13199 //SDMA4_RLC4_IB_CNTL 13200 #define SDMA4_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 13201 #define SDMA4_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 13202 #define SDMA4_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 13203 #define SDMA4_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 13204 #define SDMA4_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L 13205 #define SDMA4_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 13206 #define SDMA4_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 13207 #define SDMA4_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L 13208 //SDMA4_RLC4_IB_RPTR 13209 #define SDMA4_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 13210 #define SDMA4_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL 13211 //SDMA4_RLC4_IB_OFFSET 13212 #define SDMA4_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 13213 #define SDMA4_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 13214 //SDMA4_RLC4_IB_BASE_LO 13215 #define SDMA4_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 13216 #define SDMA4_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 13217 //SDMA4_RLC4_IB_BASE_HI 13218 #define SDMA4_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 13219 #define SDMA4_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 13220 //SDMA4_RLC4_IB_SIZE 13221 #define SDMA4_RLC4_IB_SIZE__SIZE__SHIFT 0x0 13222 #define SDMA4_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL 13223 //SDMA4_RLC4_SKIP_CNTL 13224 #define SDMA4_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 13225 #define SDMA4_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 13226 //SDMA4_RLC4_CONTEXT_STATUS 13227 #define SDMA4_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 13228 #define SDMA4_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 13229 #define SDMA4_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 13230 #define SDMA4_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 13231 #define SDMA4_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 13232 #define SDMA4_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 13233 #define SDMA4_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 13234 #define SDMA4_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 13235 #define SDMA4_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 13236 #define SDMA4_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L 13237 #define SDMA4_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 13238 #define SDMA4_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 13239 #define SDMA4_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 13240 #define SDMA4_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 13241 #define SDMA4_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 13242 #define SDMA4_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 13243 //SDMA4_RLC4_DOORBELL 13244 #define SDMA4_RLC4_DOORBELL__ENABLE__SHIFT 0x1c 13245 #define SDMA4_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e 13246 #define SDMA4_RLC4_DOORBELL__ENABLE_MASK 0x10000000L 13247 #define SDMA4_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L 13248 //SDMA4_RLC4_STATUS 13249 #define SDMA4_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 13250 #define SDMA4_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 13251 #define SDMA4_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 13252 #define SDMA4_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 13253 //SDMA4_RLC4_DOORBELL_LOG 13254 #define SDMA4_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 13255 #define SDMA4_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 13256 #define SDMA4_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 13257 #define SDMA4_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 13258 //SDMA4_RLC4_WATERMARK 13259 #define SDMA4_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 13260 #define SDMA4_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 13261 #define SDMA4_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 13262 #define SDMA4_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 13263 //SDMA4_RLC4_DOORBELL_OFFSET 13264 #define SDMA4_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 13265 #define SDMA4_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 13266 //SDMA4_RLC4_CSA_ADDR_LO 13267 #define SDMA4_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 13268 #define SDMA4_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 13269 //SDMA4_RLC4_CSA_ADDR_HI 13270 #define SDMA4_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 13271 #define SDMA4_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 13272 //SDMA4_RLC4_IB_SUB_REMAIN 13273 #define SDMA4_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 13274 #define SDMA4_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 13275 //SDMA4_RLC4_PREEMPT 13276 #define SDMA4_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 13277 #define SDMA4_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L 13278 //SDMA4_RLC4_DUMMY_REG 13279 #define SDMA4_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 13280 #define SDMA4_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 13281 //SDMA4_RLC4_RB_WPTR_POLL_ADDR_HI 13282 #define SDMA4_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 13283 #define SDMA4_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 13284 //SDMA4_RLC4_RB_WPTR_POLL_ADDR_LO 13285 #define SDMA4_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 13286 #define SDMA4_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 13287 //SDMA4_RLC4_RB_AQL_CNTL 13288 #define SDMA4_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 13289 #define SDMA4_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 13290 #define SDMA4_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 13291 #define SDMA4_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 13292 #define SDMA4_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 13293 #define SDMA4_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 13294 //SDMA4_RLC4_MINOR_PTR_UPDATE 13295 #define SDMA4_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 13296 #define SDMA4_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 13297 //SDMA4_RLC4_MIDCMD_DATA0 13298 #define SDMA4_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 13299 #define SDMA4_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 13300 //SDMA4_RLC4_MIDCMD_DATA1 13301 #define SDMA4_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 13302 #define SDMA4_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 13303 //SDMA4_RLC4_MIDCMD_DATA2 13304 #define SDMA4_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 13305 #define SDMA4_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 13306 //SDMA4_RLC4_MIDCMD_DATA3 13307 #define SDMA4_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 13308 #define SDMA4_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 13309 //SDMA4_RLC4_MIDCMD_DATA4 13310 #define SDMA4_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 13311 #define SDMA4_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 13312 //SDMA4_RLC4_MIDCMD_DATA5 13313 #define SDMA4_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 13314 #define SDMA4_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 13315 //SDMA4_RLC4_MIDCMD_DATA6 13316 #define SDMA4_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 13317 #define SDMA4_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 13318 //SDMA4_RLC4_MIDCMD_DATA7 13319 #define SDMA4_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 13320 #define SDMA4_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 13321 //SDMA4_RLC4_MIDCMD_DATA8 13322 #define SDMA4_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 13323 #define SDMA4_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 13324 //SDMA4_RLC4_MIDCMD_DATA9 13325 #define SDMA4_RLC4_MIDCMD_DATA9__DATA9__SHIFT 0x0 13326 #define SDMA4_RLC4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 13327 //SDMA4_RLC4_MIDCMD_DATA10 13328 #define SDMA4_RLC4_MIDCMD_DATA10__DATA10__SHIFT 0x0 13329 #define SDMA4_RLC4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 13330 //SDMA4_RLC4_MIDCMD_CNTL 13331 #define SDMA4_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 13332 #define SDMA4_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 13333 #define SDMA4_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 13334 #define SDMA4_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 13335 #define SDMA4_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 13336 #define SDMA4_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 13337 #define SDMA4_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 13338 #define SDMA4_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 13339 //SDMA4_RLC5_RB_CNTL 13340 #define SDMA4_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 13341 #define SDMA4_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 13342 #define SDMA4_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 13343 #define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 13344 #define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 13345 #define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 13346 #define SDMA4_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 13347 #define SDMA4_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 13348 #define SDMA4_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L 13349 #define SDMA4_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL 13350 #define SDMA4_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 13351 #define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 13352 #define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 13353 #define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 13354 #define SDMA4_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L 13355 #define SDMA4_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L 13356 //SDMA4_RLC5_RB_BASE 13357 #define SDMA4_RLC5_RB_BASE__ADDR__SHIFT 0x0 13358 #define SDMA4_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL 13359 //SDMA4_RLC5_RB_BASE_HI 13360 #define SDMA4_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 13361 #define SDMA4_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 13362 //SDMA4_RLC5_RB_RPTR 13363 #define SDMA4_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 13364 #define SDMA4_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 13365 //SDMA4_RLC5_RB_RPTR_HI 13366 #define SDMA4_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 13367 #define SDMA4_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 13368 //SDMA4_RLC5_RB_WPTR 13369 #define SDMA4_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 13370 #define SDMA4_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 13371 //SDMA4_RLC5_RB_WPTR_HI 13372 #define SDMA4_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 13373 #define SDMA4_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 13374 //SDMA4_RLC5_RB_WPTR_POLL_CNTL 13375 #define SDMA4_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 13376 #define SDMA4_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 13377 #define SDMA4_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 13378 #define SDMA4_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 13379 #define SDMA4_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 13380 #define SDMA4_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 13381 #define SDMA4_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 13382 #define SDMA4_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 13383 #define SDMA4_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 13384 #define SDMA4_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 13385 //SDMA4_RLC5_RB_RPTR_ADDR_HI 13386 #define SDMA4_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 13387 #define SDMA4_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 13388 //SDMA4_RLC5_RB_RPTR_ADDR_LO 13389 #define SDMA4_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 13390 #define SDMA4_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 13391 #define SDMA4_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 13392 #define SDMA4_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 13393 //SDMA4_RLC5_IB_CNTL 13394 #define SDMA4_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 13395 #define SDMA4_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 13396 #define SDMA4_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 13397 #define SDMA4_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 13398 #define SDMA4_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L 13399 #define SDMA4_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 13400 #define SDMA4_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 13401 #define SDMA4_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L 13402 //SDMA4_RLC5_IB_RPTR 13403 #define SDMA4_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 13404 #define SDMA4_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL 13405 //SDMA4_RLC5_IB_OFFSET 13406 #define SDMA4_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 13407 #define SDMA4_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 13408 //SDMA4_RLC5_IB_BASE_LO 13409 #define SDMA4_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 13410 #define SDMA4_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 13411 //SDMA4_RLC5_IB_BASE_HI 13412 #define SDMA4_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 13413 #define SDMA4_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 13414 //SDMA4_RLC5_IB_SIZE 13415 #define SDMA4_RLC5_IB_SIZE__SIZE__SHIFT 0x0 13416 #define SDMA4_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL 13417 //SDMA4_RLC5_SKIP_CNTL 13418 #define SDMA4_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 13419 #define SDMA4_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 13420 //SDMA4_RLC5_CONTEXT_STATUS 13421 #define SDMA4_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 13422 #define SDMA4_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 13423 #define SDMA4_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 13424 #define SDMA4_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 13425 #define SDMA4_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 13426 #define SDMA4_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 13427 #define SDMA4_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 13428 #define SDMA4_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 13429 #define SDMA4_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 13430 #define SDMA4_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L 13431 #define SDMA4_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 13432 #define SDMA4_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 13433 #define SDMA4_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 13434 #define SDMA4_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 13435 #define SDMA4_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 13436 #define SDMA4_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 13437 //SDMA4_RLC5_DOORBELL 13438 #define SDMA4_RLC5_DOORBELL__ENABLE__SHIFT 0x1c 13439 #define SDMA4_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e 13440 #define SDMA4_RLC5_DOORBELL__ENABLE_MASK 0x10000000L 13441 #define SDMA4_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L 13442 //SDMA4_RLC5_STATUS 13443 #define SDMA4_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 13444 #define SDMA4_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 13445 #define SDMA4_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 13446 #define SDMA4_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 13447 //SDMA4_RLC5_DOORBELL_LOG 13448 #define SDMA4_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 13449 #define SDMA4_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 13450 #define SDMA4_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 13451 #define SDMA4_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 13452 //SDMA4_RLC5_WATERMARK 13453 #define SDMA4_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 13454 #define SDMA4_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 13455 #define SDMA4_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 13456 #define SDMA4_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 13457 //SDMA4_RLC5_DOORBELL_OFFSET 13458 #define SDMA4_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 13459 #define SDMA4_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 13460 //SDMA4_RLC5_CSA_ADDR_LO 13461 #define SDMA4_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 13462 #define SDMA4_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 13463 //SDMA4_RLC5_CSA_ADDR_HI 13464 #define SDMA4_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 13465 #define SDMA4_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 13466 //SDMA4_RLC5_IB_SUB_REMAIN 13467 #define SDMA4_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 13468 #define SDMA4_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 13469 //SDMA4_RLC5_PREEMPT 13470 #define SDMA4_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 13471 #define SDMA4_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L 13472 //SDMA4_RLC5_DUMMY_REG 13473 #define SDMA4_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 13474 #define SDMA4_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 13475 //SDMA4_RLC5_RB_WPTR_POLL_ADDR_HI 13476 #define SDMA4_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 13477 #define SDMA4_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 13478 //SDMA4_RLC5_RB_WPTR_POLL_ADDR_LO 13479 #define SDMA4_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 13480 #define SDMA4_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 13481 //SDMA4_RLC5_RB_AQL_CNTL 13482 #define SDMA4_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 13483 #define SDMA4_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 13484 #define SDMA4_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 13485 #define SDMA4_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 13486 #define SDMA4_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 13487 #define SDMA4_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 13488 //SDMA4_RLC5_MINOR_PTR_UPDATE 13489 #define SDMA4_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 13490 #define SDMA4_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 13491 //SDMA4_RLC5_MIDCMD_DATA0 13492 #define SDMA4_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 13493 #define SDMA4_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 13494 //SDMA4_RLC5_MIDCMD_DATA1 13495 #define SDMA4_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 13496 #define SDMA4_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 13497 //SDMA4_RLC5_MIDCMD_DATA2 13498 #define SDMA4_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 13499 #define SDMA4_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 13500 //SDMA4_RLC5_MIDCMD_DATA3 13501 #define SDMA4_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 13502 #define SDMA4_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 13503 //SDMA4_RLC5_MIDCMD_DATA4 13504 #define SDMA4_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 13505 #define SDMA4_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 13506 //SDMA4_RLC5_MIDCMD_DATA5 13507 #define SDMA4_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 13508 #define SDMA4_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 13509 //SDMA4_RLC5_MIDCMD_DATA6 13510 #define SDMA4_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 13511 #define SDMA4_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 13512 //SDMA4_RLC5_MIDCMD_DATA7 13513 #define SDMA4_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 13514 #define SDMA4_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 13515 //SDMA4_RLC5_MIDCMD_DATA8 13516 #define SDMA4_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 13517 #define SDMA4_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 13518 //SDMA4_RLC5_MIDCMD_DATA9 13519 #define SDMA4_RLC5_MIDCMD_DATA9__DATA9__SHIFT 0x0 13520 #define SDMA4_RLC5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 13521 //SDMA4_RLC5_MIDCMD_DATA10 13522 #define SDMA4_RLC5_MIDCMD_DATA10__DATA10__SHIFT 0x0 13523 #define SDMA4_RLC5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 13524 //SDMA4_RLC5_MIDCMD_CNTL 13525 #define SDMA4_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 13526 #define SDMA4_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 13527 #define SDMA4_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 13528 #define SDMA4_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 13529 #define SDMA4_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 13530 #define SDMA4_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 13531 #define SDMA4_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 13532 #define SDMA4_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 13533 //SDMA4_RLC6_RB_CNTL 13534 #define SDMA4_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 13535 #define SDMA4_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 13536 #define SDMA4_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 13537 #define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 13538 #define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 13539 #define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 13540 #define SDMA4_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 13541 #define SDMA4_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 13542 #define SDMA4_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L 13543 #define SDMA4_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL 13544 #define SDMA4_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 13545 #define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 13546 #define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 13547 #define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 13548 #define SDMA4_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L 13549 #define SDMA4_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L 13550 //SDMA4_RLC6_RB_BASE 13551 #define SDMA4_RLC6_RB_BASE__ADDR__SHIFT 0x0 13552 #define SDMA4_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL 13553 //SDMA4_RLC6_RB_BASE_HI 13554 #define SDMA4_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 13555 #define SDMA4_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 13556 //SDMA4_RLC6_RB_RPTR 13557 #define SDMA4_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 13558 #define SDMA4_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 13559 //SDMA4_RLC6_RB_RPTR_HI 13560 #define SDMA4_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 13561 #define SDMA4_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 13562 //SDMA4_RLC6_RB_WPTR 13563 #define SDMA4_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 13564 #define SDMA4_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 13565 //SDMA4_RLC6_RB_WPTR_HI 13566 #define SDMA4_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 13567 #define SDMA4_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 13568 //SDMA4_RLC6_RB_WPTR_POLL_CNTL 13569 #define SDMA4_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 13570 #define SDMA4_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 13571 #define SDMA4_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 13572 #define SDMA4_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 13573 #define SDMA4_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 13574 #define SDMA4_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 13575 #define SDMA4_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 13576 #define SDMA4_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 13577 #define SDMA4_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 13578 #define SDMA4_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 13579 //SDMA4_RLC6_RB_RPTR_ADDR_HI 13580 #define SDMA4_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 13581 #define SDMA4_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 13582 //SDMA4_RLC6_RB_RPTR_ADDR_LO 13583 #define SDMA4_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 13584 #define SDMA4_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 13585 #define SDMA4_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 13586 #define SDMA4_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 13587 //SDMA4_RLC6_IB_CNTL 13588 #define SDMA4_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 13589 #define SDMA4_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 13590 #define SDMA4_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 13591 #define SDMA4_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 13592 #define SDMA4_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L 13593 #define SDMA4_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 13594 #define SDMA4_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 13595 #define SDMA4_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L 13596 //SDMA4_RLC6_IB_RPTR 13597 #define SDMA4_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 13598 #define SDMA4_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL 13599 //SDMA4_RLC6_IB_OFFSET 13600 #define SDMA4_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 13601 #define SDMA4_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 13602 //SDMA4_RLC6_IB_BASE_LO 13603 #define SDMA4_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 13604 #define SDMA4_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 13605 //SDMA4_RLC6_IB_BASE_HI 13606 #define SDMA4_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 13607 #define SDMA4_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 13608 //SDMA4_RLC6_IB_SIZE 13609 #define SDMA4_RLC6_IB_SIZE__SIZE__SHIFT 0x0 13610 #define SDMA4_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL 13611 //SDMA4_RLC6_SKIP_CNTL 13612 #define SDMA4_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 13613 #define SDMA4_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 13614 //SDMA4_RLC6_CONTEXT_STATUS 13615 #define SDMA4_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 13616 #define SDMA4_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 13617 #define SDMA4_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 13618 #define SDMA4_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 13619 #define SDMA4_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 13620 #define SDMA4_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 13621 #define SDMA4_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 13622 #define SDMA4_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 13623 #define SDMA4_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 13624 #define SDMA4_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L 13625 #define SDMA4_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 13626 #define SDMA4_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 13627 #define SDMA4_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 13628 #define SDMA4_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 13629 #define SDMA4_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 13630 #define SDMA4_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 13631 //SDMA4_RLC6_DOORBELL 13632 #define SDMA4_RLC6_DOORBELL__ENABLE__SHIFT 0x1c 13633 #define SDMA4_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e 13634 #define SDMA4_RLC6_DOORBELL__ENABLE_MASK 0x10000000L 13635 #define SDMA4_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L 13636 //SDMA4_RLC6_STATUS 13637 #define SDMA4_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 13638 #define SDMA4_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 13639 #define SDMA4_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 13640 #define SDMA4_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 13641 //SDMA4_RLC6_DOORBELL_LOG 13642 #define SDMA4_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 13643 #define SDMA4_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 13644 #define SDMA4_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 13645 #define SDMA4_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 13646 //SDMA4_RLC6_WATERMARK 13647 #define SDMA4_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 13648 #define SDMA4_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 13649 #define SDMA4_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 13650 #define SDMA4_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 13651 //SDMA4_RLC6_DOORBELL_OFFSET 13652 #define SDMA4_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 13653 #define SDMA4_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 13654 //SDMA4_RLC6_CSA_ADDR_LO 13655 #define SDMA4_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 13656 #define SDMA4_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 13657 //SDMA4_RLC6_CSA_ADDR_HI 13658 #define SDMA4_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 13659 #define SDMA4_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 13660 //SDMA4_RLC6_IB_SUB_REMAIN 13661 #define SDMA4_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 13662 #define SDMA4_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 13663 //SDMA4_RLC6_PREEMPT 13664 #define SDMA4_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 13665 #define SDMA4_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L 13666 //SDMA4_RLC6_DUMMY_REG 13667 #define SDMA4_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 13668 #define SDMA4_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 13669 //SDMA4_RLC6_RB_WPTR_POLL_ADDR_HI 13670 #define SDMA4_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 13671 #define SDMA4_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 13672 //SDMA4_RLC6_RB_WPTR_POLL_ADDR_LO 13673 #define SDMA4_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 13674 #define SDMA4_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 13675 //SDMA4_RLC6_RB_AQL_CNTL 13676 #define SDMA4_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 13677 #define SDMA4_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 13678 #define SDMA4_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 13679 #define SDMA4_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 13680 #define SDMA4_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 13681 #define SDMA4_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 13682 //SDMA4_RLC6_MINOR_PTR_UPDATE 13683 #define SDMA4_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 13684 #define SDMA4_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 13685 //SDMA4_RLC6_MIDCMD_DATA0 13686 #define SDMA4_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 13687 #define SDMA4_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 13688 //SDMA4_RLC6_MIDCMD_DATA1 13689 #define SDMA4_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 13690 #define SDMA4_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 13691 //SDMA4_RLC6_MIDCMD_DATA2 13692 #define SDMA4_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 13693 #define SDMA4_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 13694 //SDMA4_RLC6_MIDCMD_DATA3 13695 #define SDMA4_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 13696 #define SDMA4_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 13697 //SDMA4_RLC6_MIDCMD_DATA4 13698 #define SDMA4_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 13699 #define SDMA4_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 13700 //SDMA4_RLC6_MIDCMD_DATA5 13701 #define SDMA4_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 13702 #define SDMA4_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 13703 //SDMA4_RLC6_MIDCMD_DATA6 13704 #define SDMA4_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 13705 #define SDMA4_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 13706 //SDMA4_RLC6_MIDCMD_DATA7 13707 #define SDMA4_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 13708 #define SDMA4_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 13709 //SDMA4_RLC6_MIDCMD_DATA8 13710 #define SDMA4_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 13711 #define SDMA4_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 13712 //SDMA4_RLC6_MIDCMD_DATA9 13713 #define SDMA4_RLC6_MIDCMD_DATA9__DATA9__SHIFT 0x0 13714 #define SDMA4_RLC6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 13715 //SDMA4_RLC6_MIDCMD_DATA10 13716 #define SDMA4_RLC6_MIDCMD_DATA10__DATA10__SHIFT 0x0 13717 #define SDMA4_RLC6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 13718 //SDMA4_RLC6_MIDCMD_CNTL 13719 #define SDMA4_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 13720 #define SDMA4_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 13721 #define SDMA4_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 13722 #define SDMA4_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 13723 #define SDMA4_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 13724 #define SDMA4_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 13725 #define SDMA4_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 13726 #define SDMA4_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 13727 //SDMA4_RLC7_RB_CNTL 13728 #define SDMA4_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 13729 #define SDMA4_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 13730 #define SDMA4_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 13731 #define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 13732 #define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 13733 #define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 13734 #define SDMA4_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 13735 #define SDMA4_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 13736 #define SDMA4_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L 13737 #define SDMA4_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL 13738 #define SDMA4_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 13739 #define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 13740 #define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 13741 #define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 13742 #define SDMA4_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L 13743 #define SDMA4_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L 13744 //SDMA4_RLC7_RB_BASE 13745 #define SDMA4_RLC7_RB_BASE__ADDR__SHIFT 0x0 13746 #define SDMA4_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL 13747 //SDMA4_RLC7_RB_BASE_HI 13748 #define SDMA4_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 13749 #define SDMA4_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 13750 //SDMA4_RLC7_RB_RPTR 13751 #define SDMA4_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 13752 #define SDMA4_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 13753 //SDMA4_RLC7_RB_RPTR_HI 13754 #define SDMA4_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 13755 #define SDMA4_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 13756 //SDMA4_RLC7_RB_WPTR 13757 #define SDMA4_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 13758 #define SDMA4_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 13759 //SDMA4_RLC7_RB_WPTR_HI 13760 #define SDMA4_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 13761 #define SDMA4_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 13762 //SDMA4_RLC7_RB_WPTR_POLL_CNTL 13763 #define SDMA4_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 13764 #define SDMA4_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 13765 #define SDMA4_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 13766 #define SDMA4_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 13767 #define SDMA4_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 13768 #define SDMA4_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 13769 #define SDMA4_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 13770 #define SDMA4_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 13771 #define SDMA4_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 13772 #define SDMA4_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 13773 //SDMA4_RLC7_RB_RPTR_ADDR_HI 13774 #define SDMA4_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 13775 #define SDMA4_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 13776 //SDMA4_RLC7_RB_RPTR_ADDR_LO 13777 #define SDMA4_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 13778 #define SDMA4_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 13779 #define SDMA4_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 13780 #define SDMA4_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 13781 //SDMA4_RLC7_IB_CNTL 13782 #define SDMA4_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 13783 #define SDMA4_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 13784 #define SDMA4_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 13785 #define SDMA4_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 13786 #define SDMA4_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L 13787 #define SDMA4_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 13788 #define SDMA4_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 13789 #define SDMA4_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L 13790 //SDMA4_RLC7_IB_RPTR 13791 #define SDMA4_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 13792 #define SDMA4_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL 13793 //SDMA4_RLC7_IB_OFFSET 13794 #define SDMA4_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 13795 #define SDMA4_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 13796 //SDMA4_RLC7_IB_BASE_LO 13797 #define SDMA4_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 13798 #define SDMA4_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 13799 //SDMA4_RLC7_IB_BASE_HI 13800 #define SDMA4_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 13801 #define SDMA4_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 13802 //SDMA4_RLC7_IB_SIZE 13803 #define SDMA4_RLC7_IB_SIZE__SIZE__SHIFT 0x0 13804 #define SDMA4_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL 13805 //SDMA4_RLC7_SKIP_CNTL 13806 #define SDMA4_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 13807 #define SDMA4_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 13808 //SDMA4_RLC7_CONTEXT_STATUS 13809 #define SDMA4_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 13810 #define SDMA4_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 13811 #define SDMA4_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 13812 #define SDMA4_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 13813 #define SDMA4_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 13814 #define SDMA4_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 13815 #define SDMA4_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 13816 #define SDMA4_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 13817 #define SDMA4_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 13818 #define SDMA4_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L 13819 #define SDMA4_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 13820 #define SDMA4_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 13821 #define SDMA4_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 13822 #define SDMA4_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 13823 #define SDMA4_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 13824 #define SDMA4_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 13825 //SDMA4_RLC7_DOORBELL 13826 #define SDMA4_RLC7_DOORBELL__ENABLE__SHIFT 0x1c 13827 #define SDMA4_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e 13828 #define SDMA4_RLC7_DOORBELL__ENABLE_MASK 0x10000000L 13829 #define SDMA4_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L 13830 //SDMA4_RLC7_STATUS 13831 #define SDMA4_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 13832 #define SDMA4_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 13833 #define SDMA4_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 13834 #define SDMA4_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 13835 //SDMA4_RLC7_DOORBELL_LOG 13836 #define SDMA4_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 13837 #define SDMA4_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 13838 #define SDMA4_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 13839 #define SDMA4_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 13840 //SDMA4_RLC7_WATERMARK 13841 #define SDMA4_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 13842 #define SDMA4_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 13843 #define SDMA4_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 13844 #define SDMA4_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 13845 //SDMA4_RLC7_DOORBELL_OFFSET 13846 #define SDMA4_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 13847 #define SDMA4_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 13848 //SDMA4_RLC7_CSA_ADDR_LO 13849 #define SDMA4_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 13850 #define SDMA4_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 13851 //SDMA4_RLC7_CSA_ADDR_HI 13852 #define SDMA4_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 13853 #define SDMA4_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 13854 //SDMA4_RLC7_IB_SUB_REMAIN 13855 #define SDMA4_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 13856 #define SDMA4_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 13857 //SDMA4_RLC7_PREEMPT 13858 #define SDMA4_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 13859 #define SDMA4_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L 13860 //SDMA4_RLC7_DUMMY_REG 13861 #define SDMA4_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 13862 #define SDMA4_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 13863 //SDMA4_RLC7_RB_WPTR_POLL_ADDR_HI 13864 #define SDMA4_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 13865 #define SDMA4_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 13866 //SDMA4_RLC7_RB_WPTR_POLL_ADDR_LO 13867 #define SDMA4_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 13868 #define SDMA4_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 13869 //SDMA4_RLC7_RB_AQL_CNTL 13870 #define SDMA4_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 13871 #define SDMA4_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 13872 #define SDMA4_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 13873 #define SDMA4_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 13874 #define SDMA4_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 13875 #define SDMA4_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 13876 //SDMA4_RLC7_MINOR_PTR_UPDATE 13877 #define SDMA4_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 13878 #define SDMA4_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 13879 //SDMA4_RLC7_MIDCMD_DATA0 13880 #define SDMA4_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 13881 #define SDMA4_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 13882 //SDMA4_RLC7_MIDCMD_DATA1 13883 #define SDMA4_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 13884 #define SDMA4_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 13885 //SDMA4_RLC7_MIDCMD_DATA2 13886 #define SDMA4_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 13887 #define SDMA4_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 13888 //SDMA4_RLC7_MIDCMD_DATA3 13889 #define SDMA4_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 13890 #define SDMA4_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 13891 //SDMA4_RLC7_MIDCMD_DATA4 13892 #define SDMA4_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 13893 #define SDMA4_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 13894 //SDMA4_RLC7_MIDCMD_DATA5 13895 #define SDMA4_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 13896 #define SDMA4_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 13897 //SDMA4_RLC7_MIDCMD_DATA6 13898 #define SDMA4_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 13899 #define SDMA4_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 13900 //SDMA4_RLC7_MIDCMD_DATA7 13901 #define SDMA4_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 13902 #define SDMA4_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 13903 //SDMA4_RLC7_MIDCMD_DATA8 13904 #define SDMA4_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 13905 #define SDMA4_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 13906 //SDMA4_RLC7_MIDCMD_DATA9 13907 #define SDMA4_RLC7_MIDCMD_DATA9__DATA9__SHIFT 0x0 13908 #define SDMA4_RLC7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 13909 //SDMA4_RLC7_MIDCMD_DATA10 13910 #define SDMA4_RLC7_MIDCMD_DATA10__DATA10__SHIFT 0x0 13911 #define SDMA4_RLC7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 13912 //SDMA4_RLC7_MIDCMD_CNTL 13913 #define SDMA4_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 13914 #define SDMA4_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 13915 #define SDMA4_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 13916 #define SDMA4_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 13917 #define SDMA4_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 13918 #define SDMA4_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 13919 #define SDMA4_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 13920 #define SDMA4_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 13921 13922 #endif 13923