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Searched refs:SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_0_sh_mask.h1493 #define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 macro
H A Dsdma1_4_2_2_sh_mask.h1509 #define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT macro
H A Dsdma1_4_2_sh_mask.h1501 #define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_sh_mask.h1884 #define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 macro
H A Doss_2_0_sh_mask.h1684 #define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 macro
H A Doss_3_0_1_sh_mask.h2832 #define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 macro
H A Doss_3_0_sh_mask.h2946 #define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_0_sh_mask.h4111 #define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_sh_mask.h4057 #define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT macro
H A Dgc_10_3_0_sh_mask.h4230 #define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT macro