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Searched refs:SDMA1_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_sh_mask.h4498 #define SDMA1_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h4618 #define SDMA1_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT … macro