Home
last modified time | relevance | path

Searched refs:SDMA0_QUEUE3_MIDCMD_DATA5__DATA5__SHIFT (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_sh_mask.h1740 #define SDMA0_QUEUE3_MIDCMD_DATA5__DATA5__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h1795 #define SDMA0_QUEUE3_MIDCMD_DATA5__DATA5__SHIFT … macro