| /openbmc/linux/arch/sh/kernel/cpu/sh4a/ |
| H A D | setup-sh7366.c | 265 SDHI, CMT, TSIF, SIU, enumerator
296 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
297 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
356 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
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| H A D | setup-sh7343.c | 323 IRDA, SDHI, CMT, TSIF, SIU, enumerator
358 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
359 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
417 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
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| H A D | setup-sh7722.c | 544 SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI, enumerator
571 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
572 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
633 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
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| H A D | setup-sh7734.c | 362 SDHI, enumerator
437 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2),
467 SDHI, /* SDHI 0-2 */
503 { TMU30, TMU60, RTC, SDHI } },
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| H A D | setup-sh7757.c | 791 SDHI, DVC, enumerator
842 INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0),
843 INTC_VECT(SDHI, 0x4c0),
968 HUDI, 0, 0, SCIF3, SCIF2, SDHI, TMU345, TMU012
1062 { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } },
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| /openbmc/linux/Documentation/devicetree/bindings/mmc/ |
| H A D | renesas,sdhi.yaml | 7 title: Renesas SDHI SD/MMC controller
44 - const: renesas,sdhi-mmc-r8a77470 # RZ/G1C (SDHI/MMC IP)
130 - description: IMCLK, SDHI channel main clock1.
131 - description: CLK_HS, SDHI channel High speed clock which operates
132 4 times that of SDHI channel main clock1.
133 - description: IMCLK2, SDHI channel main clock2. When this clock is
136 - description: ACLK, SDHI channel bus clock.
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| /openbmc/linux/arch/sh/kernel/cpu/sh2a/ |
| H A D | setup-sh7203.c | 37 ROMDEC, FLCTL, SDHI, RTC, RCAN0, RCAN1, enumerator
122 INTC_IRQ(SDHI, 228), INTC_IRQ(SDHI, 229),
123 INTC_IRQ(SDHI, 230),
160 { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, SDHI, RTC, RCAN0 } },
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| H A D | setup-sh7264.c | 42 NFMC, SDHI, RTC, enumerator
160 INTC_IRQ(SDHI, 292), INTC_IRQ(SDHI, 293),
161 INTC_IRQ(SDHI, 294),
213 { 0xfffe0c1e, 0, 16, 4, /* IPR21 */ { NFMC, SDHI, RTC, 0 } },
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| /openbmc/linux/arch/arm64/boot/dts/renesas/ |
| H A D | rzg2l-smarc-som.dtsi | 20 #define SDHI (!EMMC) macro
332 #if SDHI
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| H A D | rzg2l-smarc.dtsi | 124 /* SDHI cd pin is muxed with counter Z phase signal */
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| /openbmc/linux/arch/arm/boot/dts/renesas/ |
| H A D | r7s72100-rskrza1.dts | 171 /* SDHI ch1 on CN1 */
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| /openbmc/linux/drivers/mmc/host/ |
| H A D | Kconfig | 669 tristate "Renesas SDHI SD/SDIO controller support"
674 This provides support for the SDHI SD/SDIO controller found in
678 tristate "DMA for SDHI SD/SDIO controllers using SYS-DMAC"
682 This provides DMA support for SDHI SD/SDIO controllers
687 tristate "DMA for SDHI SD/SDIO controllers using on-chip bus mastering"
692 This provides DMA support for SDHI SD/SDIO controllers
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| /openbmc/u-boot/drivers/mmc/ |
| H A D | Kconfig | 294 bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support"
297 Support for the on-chip SDHI host controller on SuperH/Renesas ARM SoCs platform
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| /openbmc/linux/ |
| H A D | MAINTAINERS | 21724 TMIO/SDHI MMC DRIVER
|