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Searched refs:SC_VPLL27BCTRL2 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/arm/mach-uniphier/clk/
H A Dpll-ld4.c82 tmp = readl(SC_VPLL27BCTRL2); in vpll_init()
84 writel(tmp, SC_VPLL27BCTRL2); in vpll_init()
91 tmp = readl(SC_VPLL27BCTRL2); in vpll_init()
94 writel(tmp, SC_VPLL27BCTRL2); in vpll_init()
134 tmp = readl(SC_VPLL27BCTRL2); in vpll_init()
136 writel(tmp, SC_VPLL27BCTRL2); in vpll_init()
H A Dpll-pro4.c49 tmp = readl(SC_VPLL27BCTRL2); in vpll_init()
52 writel(tmp, SC_VPLL27BCTRL2); in vpll_init()
92 tmp = readl(SC_VPLL27BCTRL2); in vpll_init()
94 writel(tmp, SC_VPLL27BCTRL2); in vpll_init()
/openbmc/u-boot/arch/arm/mach-uniphier/
H A Dsc-regs.h38 #define SC_VPLL27BCTRL2 (SC_BASE_ADDR | 0x1294) macro