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Searched refs:SC_DPLL1CTRL (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-uniphier/clk/
H A Dpll-ld20.c21 #define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* DDR memory 1 */ macro
49 uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL); in uniphier_ld20_pll_init()
H A Dpll-pxs3.c22 #define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1490) /* DDR memory 1 */ macro
55 uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL); in uniphier_pxs3_pll_init()