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Searched refs:SCU_MPLL_POST_MASK (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/drivers/clk/aspeed/
H A Dclk_ast2500.c70 const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK) in ast2500_get_mpll_rate()
336 .post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT), in ast2500_configure_ddr()
342 mpll_reg &= ~(SCU_MPLL_POST_MASK | SCU_MPLL_NUM_MASK in ast2500_configure_ddr()
H A Dclk_ast2400.c362 .post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT), in ast2400_configure_ddr()
368 mpll_reg &= ~(SCU_MPLL_POST_MASK | SCU_MPLL_NUM_MASK in ast2400_configure_ddr()
/openbmc/u-boot/arch/arm/include/asm/arch-aspeed/
H A Dscu_ast2400.h20 #define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT) macro
H A Dscu_ast2500.h23 #define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT) macro
/openbmc/u-boot/drivers/ram/aspeed/
H A Dsdram_ast2500.c27 #define SCU_MPLL_FREQ_MASK (SCU_MPLL_DENUM_MASK | SCU_MPLL_NUM_MASK | SCU_MPLL_POST_MASK)