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Searched refs:SCR (Results 1 – 23 of 23) sorted by relevance

/openbmc/linux/Documentation/arch/s390/
H A Dconfig3270.sh22 SCR=$ROOT/tmp/mkdev3270
23 SCRTMP=$SCR.a
37 echo "#!/bin/sh" > $SCR || exit 1
38 echo " " >> $SCR
39 echo "# Script built by /sbin/config3270" >> $SCR
41 echo rm -rf "$D/$SUBD/*" >> $SCR
46 echo mkdir -p $D/$SUBD >> $SCR
56 echo mknod $D/$TUB c $fsmaj 0 >> $SCR
57 echo chmod 666 $D/$TUB >> $SCR
61 echo mknod $D/$TUB$devno c $fsmaj $min >> $SCR
[all …]
/openbmc/qemu/hw/char/
H A Drenesas_sci.c43 REG8(SCR, 2)
44 FIELD(SCR, CKE, 0, 2)
45 FIELD(SCR, TEIE, 2, 1)
46 FIELD(SCR, MPIE, 3, 1)
47 FIELD(SCR, RE, 4, 1)
48 FIELD(SCR, TE, 5, 1)
49 FIELD(SCR, RIE, 6, 1)
50 FIELD(SCR, TIE, 7, 1)
78 return FIELD_EX8(sci->scr, SCR, RE); in can_receive()
88 if (FIELD_EX8(sci->scr, SCR, RIE)) { in receive()
[all …]
/openbmc/linux/drivers/net/wan/
H A Dhdlc_ppp.c86 enum {INV = 0x10, IRC = 0x20, ZRC = 0x40, SCR = 0x80, SCA = 0x100, enumerator
280 {IRC|SCR|3, INV , INV , INV , INV , INV , INV }, /* START */
282 { INV , INV ,STR|2, SCR|3 ,SCR|3, SCR|5 , INV }, /* TO+ */
284 { STA|0 ,IRC|SCR|SCA|5, 2 , SCA|5 ,SCA|6, SCA|5 ,SCR|SCA|5}, /* RCR+ */
285 { STA|0 ,IRC|SCR|SCN|3, 2 , SCN|3 ,SCN|4, SCN|3 ,SCR|SCN|3}, /* RCR- */
286 { STA|0 , STA|1 , 2 , IRC|4 ,SCR|3, 6 , SCR|3 }, /* RCA */
287 { STA|0 , STA|1 , 2 ,IRC|SCR|3,SCR|3,IRC|SCR|5, SCR|3 }, /* RCN */
289 { 0 , 1 , 1 , 3 , 3 , 5 , SCR|3 }, /* RTA */
318 if (action & (SCR | STR)) /* set Configure-Req/Terminate-Req timer */ in ppp_cp_event()
327 if (action & SCR) /* send Configure-Request */ in ppp_cp_event()
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dpsci.S41 mrc p15, 0, r5, c1, c1, 0 @ Read SCR
43 mcr p15, 0, r5, c1, c1, 0 @ Write SCR
/openbmc/linux/drivers/net/hamradio/
H A Dbaycom_ser_fdx.c101 #define SCR(iobase) (iobase+7) macro
362 outb(0x5a, SCR(iobase)); in ser12_check_uart()
363 b1 = inb(SCR(iobase)); in ser12_check_uart()
364 outb(0xa5, SCR(iobase)); in ser12_check_uart()
365 b2 = inb(SCR(iobase)); in ser12_check_uart()
H A Dbaycom_ser_hdx.c87 #define SCR(iobase) (iobase+7) macro
444 outb(0x5a, SCR(iobase)); in ser12_check_uart()
445 b1 = inb(SCR(iobase)); in ser12_check_uart()
446 outb(0xa5, SCR(iobase)); in ser12_check_uart()
447 b2 = inb(SCR(iobase)); in ser12_check_uart()
H A Dyam.c158 #define SCR(iobase) (iobase+7) macro
515 outb(0x5a, SCR(iobase)); in yam_check_uart()
516 b1 = inb(SCR(iobase)); in yam_check_uart()
517 outb(0xa5, SCR(iobase)); in yam_check_uart()
518 b2 = inb(SCR(iobase)); in yam_check_uart()
/openbmc/linux/Documentation/userspace-api/media/v4l/
H A Dmetafmt-uvc.rst26 SCR field or with that field identical to the previous header), or generally to
51 - The rest of the header, possibly including UVC PTS and SCR fields
/openbmc/linux/arch/m68k/68000/
H A Ddragen2.c45 SCR = 0x10; /* allow user access to internal registers */ in init_dragen2()
/openbmc/linux/drivers/clk/meson/
H A Dgxbb.h17 #define SCR 0x2C /* 0x0b offset in data sheet */ macro
/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dclock-gx.h16 #define SCR 0x2C /* 0x0b offset in data sheet */ macro
/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dnonsec_virt.S74 mrc p15, 0, r5, c1, c1, 0 @ read SCR
87 mcr p15, 0, r5, c1, c1, 0 @ write SCR (with NS bit set)
/openbmc/linux/Documentation/driver-api/mmc/
H A Dmmc-tools.rst37 - Print and parse SCR data.
/openbmc/linux/drivers/tty/
H A Dsynclink_gt.c370 #define SCR 0x8c /* serial control */ macro
396 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
398 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
2684 unsigned short val = rd_reg16(info, SCR); in wait_mgsl_event()
2686 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE)); in wait_mgsl_event()
2749 wr_reg16(info, SCR, in wait_mgsl_event()
2750 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE)); in wait_mgsl_event()
3803 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2)); in enable_loopback()
3885 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14)); in rx_start()
3893 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14)); in rx_start()
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A DMC68EZ328.h35 #define SCR BYTE_REF(SCR_ADDR) macro
H A DMC68328.h34 #define SCR BYTE_REF(SCR_ADDR) macro
H A DMC68VZ328.h37 #define SCR BYTE_REF(SCR_ADDR) macro
/openbmc/linux/drivers/video/fbdev/
H A Dimsttfb.c86 SCR = 35, /* 0x8C */ enumerator
740 write_reg_le32(par->dc_regs, SCR, scr); in set_imstt_regvals()
/openbmc/linux/drivers/scsi/lpfc/
H A Dlpfc_hw.h896 } SCR; typedef
1053 SCR scr; /* Payload for SCR/ACC */
H A Dlpfc_els.c3499 cmdsize = (sizeof(uint32_t) + sizeof(SCR)); in lpfc_issue_els_scr()
3530 memset(pcmd, 0, sizeof(SCR)); in lpfc_issue_els_scr()
3531 ((SCR *) pcmd)->Function = SCR_FUNC_FULL; in lpfc_issue_els_scr()
/openbmc/linux/Documentation/driver-api/media/drivers/
H A Dcx2341x-devel.rst2173 1=set initial SCR value when starting encoding (works).
2599 SCR bits 0:31 by display order
2604 SCR bit 32 by display order
/openbmc/linux/Documentation/admin-guide/media/
H A Dvivid.rst582 The Metadata capture generates UVC format metadata. The PTS and SCR are
1129 - Generate SCR
/openbmc/linux/Documentation/driver-api/
H A Dlibata.rst924 with the standard SCR Control register. As such, it's usually easier