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Searched refs:SCLK_EMMC_DIV50 (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dpx30-cru.h85 #define SCLK_EMMC_DIV50 83 macro
H A Drk3308-cru.h61 #define SCLK_EMMC_DIV50 57 macro
/openbmc/linux/drivers/clk/rockchip/
H A Dclk-px30.c495 COMPOSITE_DIV_OFFSET(SCLK_EMMC_DIV50, "clk_emmc_div50", mux_gpll_cpll_npll_xin24m_p, 0,
H A Dclk-rk3308.c514 COMPOSITE(SCLK_EMMC_DIV50, "clk_emmc_div50", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,