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Searched refs:SCG_PLL_CFG_PLLSEL_SHIFT (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-mx7ulp/
H A Dscg.h183 #define SCG_PLL_CFG_PLLSEL_SHIFT (1) macro
185 #define SCG_PLL_CFG_PLLSEL_MASK ((0x1UL) << SCG_PLL_CFG_PLLSEL_SHIFT)
/openbmc/u-boot/arch/arm/mach-imx/mx7ulp/
H A Dscg.c271 val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT; in scg_apll_get_rate()
299 val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT; in scg_spll_get_rate()
833 #define SCG1_SPLL_CFG_PLLSEL_NUM ((0x1) << SCG_PLL_CFG_PLLSEL_SHIFT)
934 #define SCG1_APLL_CFG_PLLSEL_NUM ((0x0) << SCG_PLL_CFG_PLLSEL_SHIFT)