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Searched refs:SCG_PLL_CFG_PFDSEL_MASK (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-imx/mx7ulp/
H A Dscg.c286 val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >> in scg_apll_get_rate()
319 val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >> in scg_spll_get_rate()
342 val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >> in scg_ddr_get_rate()
/openbmc/u-boot/arch/arm/include/asm/arch-mx7ulp/
H A Dscg.h177 #define SCG_PLL_CFG_PFDSEL_MASK ((0x3UL) << SCG_PLL_CFG_PFDSEL_SHIFT) macro