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/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga_arria10_socdk_sdmmc_handoff.dtsi128 nocclk = <0x0384000b>; /* Register: nocclk */
129 mpuclk = <0x03840001>; /* Register: mpuclk */
153 <0x00000000 0x00000008>, /* Register: pinmux_shared_io_q1_1 */
154 <0x00000004 0x00000008>, /* Register: pinmux_shared_io_q1_2 */
155 <0x00000008 0x00000008>, /* Register: pinmux_shared_io_q1_3 */
156 <0x0000000c 0x00000008>, /* Register: pinmux_shared_io_q1_4 */
157 <0x00000010 0x00000008>, /* Register: pinmux_shared_io_q1_5 */
158 <0x00000014 0x00000008>, /* Register: pinmux_shared_io_q1_6 */
159 <0x00000018 0x00000008>, /* Register: pinmux_shared_io_q1_7 */
160 <0x0000001c 0x00000008>, /* Register: pinmux_shared_io_q1_8 */
[all …]
/openbmc/u-boot/board/Synology/ds109/
H A Dopenocd.cfg44 mww 0xD0001400 0x43000C30 ;# DDR SDRAM Configuration Register
45 mww 0xD0001404 0x39743000 ;# Dunit Control Low Register
46 mww 0xD0001408 0x22125551 ;# DDR SDRAM Timing (Low) Register
47 mww 0xD000140C 0x00000833 ;# DDR SDRAM Timing (High) Register
48 mww 0xD0001410 0x0000000d ;# DDR SDRAM Address Control Register
49 mww 0xD0001414 0x00000000 ;# DDR SDRAM Open Pages Control Register
50 mww 0xD0001418 0x00000000 ;# DDR SDRAM Operation Register
51 mww 0xD000141C 0x00000C62 ;# DDR SDRAM Mode Register
52 mww 0xD0001420 0x00000042 ;# DDR SDRAM Extended Mode Register
53 mww 0xD0001424 0x0000F1FF ;# Dunit Control High Register
[all …]
/openbmc/ipmitool/contrib/
H A Doem_ibm_sel_map88 …evice ID (MSB)","Vendor ID (LSB)","Vendor ID (MSB)","Status Register (LSB)","Status Register (MSB)…
89 …evice ID (MSB)","Vendor ID (LSB)","Vendor ID (MSB)","Status Register (LSB)","Status Register (MSB)…
90 …evice ID (MSB)","Vendor ID (LSB)","Vendor ID (MSB)","Status Register (LSB)","Status Register (MSB)…
91 …evice ID (MSB)","Vendor ID (LSB)","Vendor ID (MSB)","Status Register (LSB)","Status Register (MSB)…
92 …evice ID (MSB)","Vendor ID (LSB)","Vendor ID (MSB)","Status Register (LSB)","Status Register (MSB)…
93 …evice ID (MSB)","Vendor ID (LSB)","Vendor ID (MSB)","Status Register (LSB)","Status Register (MSB)…
94 …evice ID (MSB)","Vendor ID (LSB)","Vendor ID (MSB)","Status Register (LSB)","Status Register (MSB)…
95 …evice ID (MSB)","Vendor ID (LSB)","Vendor ID (MSB)","Status Register (LSB)","Status Register (MSB)…
96 …evice ID (MSB)","Vendor ID (LSB)","Vendor ID (MSB)","Status Register (LSB)","Status Register (MSB)…
97 …evice ID (MSB)","Vendor ID (LSB)","Vendor ID (MSB)","Status Register (LSB)","Status Register (MSB)…
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/pxaregs/pxaregs-1.14/
H A Dserial.patch8 { "ISAR", 0x403016A0, 0, 0xffffffff, 'x', "I2C Slave Address Register" },
11 +{ "HW_MCR", 0x41600010, 0, 0xffffffff, 'x', "HWUART Modem Control Register" },
12 +{ "HW_MSR", 0x41600018, 0, 0xffffffff, 'x', "HWUART Modem Status Register" },
14 { "PMCR", 0x40F00000, 0, 0xffffffff, 'x', "Power Manager Control Register (3-23)" },
H A Dusb.patch8 { "ISAR", 0x403016A0, 0, 0xffffffff, 'x', "I2C Slave Address Register" },
11 +{ "UP2OCR", 0x40600020, 0, 0xffffffff, 'x', "USB Port 2 Output Control Register" },
17 { "HW_MCR", 0x41600010, 0, 0xffffffff, 'x', "HWUART Modem Control Register" },
18 { "HW_MSR", 0x41600018, 0, 0xffffffff, 'x', "HWUART Modem Status Register" },
/openbmc/u-boot/board/renesas/MigoR/
H A Dlowlevel_init.S31 write32 CCR_A, CCR_D ! Address of Cache Control Register
34 write32 MMUCR_A, MMUCR_D ! Address of MMU Control Register
37 write32 MSTPCR0_A, MSTPCR0_D ! Address of Power Control Register 0
39 write32 MSTPCR2_A, MSTPCR2_D ! Address of Power Control Register 2
49 write16 RWTCSR_A, RWTCSR_D_1 ! 0xA4520004 (Watchdog Control / Status Register)
52 write16 RWTCNT_A, RWTCNT_D ! 0xA4520000 (Watchdog Count Register)
55 write16 RWTCSR_A, RWTCSR_D_2 ! 0xA4520004 (Watchdog Control / Status Register)
64 write32 CCR_A, CCR_D_2 ! Address of Cache Control Register
/openbmc/u-boot/arch/arm/cpu/armv7/sunxi/
H A Dfel_utils.S19 mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register
23 mrc p15, 0, lr, c1, c0, 0 @ Read CP15 Control Register
33 mcr p15, 0, r1, c1, c0, 0 @ Write CP15 Control Register
37 mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR Register
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-devtools/nodejs/nodejs/
H A D0001-liftoff-Correct-function-signatures.patch37 - inline void Move(Register dst, Register src, ValueKind);
39 + inline void Move(Register dst, Register src, ValueKind kind);
48 @@ -672,7 +672,7 @@ void LiftoffAssembler::Store(Register dst_addr, Register offset_reg,
61 @@ -452,7 +452,7 @@ void LiftoffAssembler::Store(Register dst_addr, Register offset_reg,
/openbmc/openpower-hw-diags/analyzer/plugins/
H A Dp10-tod-plugins.cpp123 enum class Register enum
133 bool readRegister(pdbg_target* i_chip, Register i_addr, in readRegister()
195 if (readRegister(i_chip, Register::TOD_ERROR, errorReg)) in collectTodFaultData()
201 if (readRegister(i_chip, Register::TOD_PSS_MSS_STATUS, statusReg)) in collectTodFaultData()
266 ? (isPriTop ? Register::TOD_PRI_PORT_0_CTRL in collectTodFaultData()
267 : Register::TOD_SEC_PORT_0_CTRL) in collectTodFaultData()
268 : (isPriTop ? Register::TOD_PRI_PORT_1_CTRL in collectTodFaultData()
269 : Register::TOD_SEC_PORT_1_CTRL); in collectTodFaultData()
/openbmc/qemu/target/hexagon/
H A Dhex_common.py335 class Register: class
447 class GprDest(Register, Single, Dest):
463 class GprSource(Register, Single, OldSource):
474 class GprNewSource(Register, Single, NewSource):
484 class GprReadWrite(Register, Single, ReadWrite):
511 class ControlDest(Register, Single, Dest):
531 class ControlSource(Register, Single, OldSource):
547 class ModifierSource(Register, Single, OldSource):
567 class PredDest(Register, Single, Dest):
582 class PredSource(Register, Single, OldSource):
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/arm32/
H A Dlowlevel_init.S23 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
42 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
53 mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
65 mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
74 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
/openbmc/openbmc/meta-amd/meta-ethanolx/recipes-amd/amd-fpga/
H A Damd-fpga.bb2 SUMMARY = "AMD FPGA Register Dump Utility"
3 DESCRIPTION = "AMD FPGA Register Dump Utility"
/openbmc/openbmc/meta-amd/meta-daytonax/recipes-amd/amd-fpga/
H A Damd-fpga.bb2 SUMMARY = "AMD FPGA Register Dump Utility"
3 DESCRIPTION = "AMD FPGA Register Dump Utility"
/openbmc/qemu/docs/system/openrisc/
H A Dcpu-features.rst14 the contents of the Unit Presence Register (``UPR``) and CPU Configuration
15 Register (``CPUCFGR``).
/openbmc/libcper/specification/document/
H A Dcper-json-specification.tex563 registerArray & object & Register data, formatted as object fields. If the \texttt{registerContextT…
566 % IA32/x64 IA32 Register State structure
567 \subsection{IA32/x64 IA32 Register State Structure}
620 \jsontableend{IA32/x64 IA32 Register State structure field table.}
622 % IA32/x64 x64 Register State structure
623 \subsection{IA32/x64 x64 Register State Structure}
698 \jsontableend{IA32/x64 x64 Register State structure field table.}
700 % IA32/x64 IA32 Register State structure
701 \subsection{IA32/x64 Unformatted Register State Structure}
706 \jsontableend{IA32/x64 Unformatted Register State structure field table.}
[all …]
/openbmc/u-boot/doc/device-tree-bindings/video/osd/
H A Dgdsys,ihs_video_out.txt6 - Register base for the video registers
7 - Register base for the OSD registers
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage.cfg12 DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
24 DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
34 DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
35 DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
36 DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
42 DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register
H A Dkwbimage-memphis.cfg15 DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
27 DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
37 DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
38 DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
39 DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
45 DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
H A Dkwbimage_256M8_1.cfg19 DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
29 DATA 0xFFD10004 0x03303300 # MPP Control 1 Register
39 DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
49 # MPP Control 3-6 Register untouched (MPP24-49)
51 DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
62 DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
79 DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
89 DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
H A Dkwbimage_128M16_1.cfg19 DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
29 DATA 0xFFD10004 0x03303300 # MPP Control 1 Register
39 DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
49 # MPP Control 3-6 Register untouched (MPP24-49)
51 DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
62 DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
79 DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
89 DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
/openbmc/qemu/contrib/plugins/
H A Dexeclog.c23 } Register; typedef
93 Register *reg = cpu->registers->pdata[n]; in insn_check_regs()
301 static Register *init_vcpu_register(qemu_plugin_reg_descriptor *desc) in init_vcpu_register()
303 Register *reg = g_new0(Register, 1); in init_vcpu_register()
354 Register *reg = init_vcpu_register(rd); in registers_init()
/openbmc/smbios-mdr/include/
H A Dspeed_select.hpp180 struct fn##Register \
182 fn##Register() \
/openbmc/phosphor-modbus/rtu/inventory/
H A Dmodbus_inventory.hpp29 struct Register struct
51 std::vector<Register> registers = {};
/openbmc/qemu/tests/functional/acpi-bits/bits-tests/
H A Dtestcpuid.py258 desc.append("Register values have been shifted by {}".format(shift))
60 desc.append("Register values have been masked:")
68 desc.append('Register values are not unique across all logical processors')
74 …desc.append("Register value: eax={eax:#010x} ebx={ebx:#010x} ecx={ecx:#010x} edx={edx:#010x}".for…
/openbmc/openbmc/meta-phosphor/dynamic-layers/aspeed-layer/recipes-bsp/u-boot/files/
H A D0001-aspeed-Disable-unnecessary-features.patch43 + * Register for LPC
49 +/* AST_LPC_HICR5 : 0x80 Host Interface Control Register 5 */
52 +/* AST_LPC_HICRB : 0x100 Host Interface Control Register B */
87 /* AST_SCU_PCIE_CONFIG_SET 0x180 - PCI-E Configuration Setting Control Register */
93 /* AST_SCU_BMC_MMIO_DEC 0x184 - BMC MMIO Decode Setting Register */
107 * Register for SDMC

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