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Searched refs:R_STATUS (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/hw/misc/
H A Daspeed_sbc.c23 #define R_STATUS (0x014 / 4) macro
191 s->regs[R_STATUS] &= ~(OTP_MEM_IDLE | OTP_IDLE); in aspeed_sbc_handle_command()
212 s->regs[R_STATUS] |= (OTP_MEM_IDLE | OTP_IDLE); in aspeed_sbc_handle_command()
230 case R_STATUS: in aspeed_sbc_write()
263 s->regs[R_STATUS] = OTP_IDLE | OTP_MEM_IDLE; in aspeed_sbc_reset()
266 s->regs[R_STATUS] &= ABR_EN; in aspeed_sbc_reset()
270 s->regs[R_STATUS] &= SECURE_BOOT_EN; in aspeed_sbc_reset()
H A Daspeed_hace.c27 #define R_STATUS (0x1c / 4) macro
474 case R_STATUS: in aspeed_hace_write()
532 s->regs[R_STATUS] |= HASH_IRQ; in aspeed_hace_write()
543 s->regs[R_STATUS] |= CRYPT_IRQ; in aspeed_hace_write()
/openbmc/qemu/hw/char/
H A Descc.c152 #define R_STATUS 0 macro
265 (s->rregs[R_STATUS] & STATUS_BRK)))) { in escc_update_irq_chn()
314 s->rregs[R_STATUS] &= STATUS_DCD | STATUS_SYNC | STATUS_CTS | STATUS_BRK; in escc_soft_reset_chn()
315 s->rregs[R_STATUS] |= STATUS_TXEMPTY | STATUS_TXUNDRN; in escc_soft_reset_chn()
317 s->rregs[R_STATUS] |= STATUS_DCD | STATUS_SYNC | STATUS_CTS; in escc_soft_reset_chn()
370 cs->rregs[R_STATUS] |= STATUS_TXEMPTY; in escc_reset()
583 s->rregs[R_STATUS] |= STATUS_SYNC; in escc_mem_write()
669 s->rregs[R_STATUS] |= STATUS_TXEMPTY; /* Tx buffer empty */ in escc_mem_write()
697 s->rregs[R_STATUS] &= ~STATUS_RXAV; in escc_mem_read()
729 || ((s->rregs[R_STATUS] & STATUS_RXAV) == STATUS_RXAV)) { in serial_can_receive()
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H A Dibex_uart.c286 case R_STATUS: in ibex_uart_read()
401 case R_STATUS: in ibex_uart_write()
/openbmc/qemu/hw/dma/
H A Dxlnx_csu_dma.c254 s->regs[R_STATUS] &= ~R_STATUS_BUSY_MASK; in xlnx_csu_dma_done()
367 s->regs[R_STATUS] |= R_STATUS_BUSY_MASK; in size_post_write()