Searched refs:R_INTR_STATUS (Results 1 – 2 of 2) sorted by relevance
71 #define R_INTR_STATUS (0x04 / 4) macro317 s->regs[R_INTR_STATUS] &= ~IXR_SELF_CLEAR; in xilinx_spips_update_ixr()318 s->regs[R_INTR_STATUS] |= in xilinx_spips_update_ixr()326 int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] & in xilinx_spips_update_ixr()402 s->regs[R_INTR_STATUS] = R_INTR_STATUS_RESET; in xlnx_zynqmp_qspips_reset()661 s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW; in xilinx_spips_flush_txfifo()887 case R_INTR_STATUS: in xilinx_spips_read()985 case R_INTR_STATUS: in xilinx_spips_write()987 s->regs[R_INTR_STATUS] &= ~(mask & value); in xilinx_spips_write()
397 [R_INTR_STATUS] = 0xffff809f,476 bool level = !!(s->regs[R_INTR_SIGNAL_EN] & s->regs[R_INTR_STATUS]); in aspeed_i3c_device_update_irq()910 return s->regs[R_INTR_STATUS] & s->regs[R_INTR_STATUS_EN]; in aspeed_i3c_device_intr_status_r()917 s->regs[R_INTR_STATUS] &= ~val; in aspeed_i3c_device_intr_status_w()937 s->regs[R_INTR_STATUS] = val; in aspeed_i3c_device_intr_force_w()1127 case R_INTR_STATUS: in aspeed_i3c_device_read()1800 case R_INTR_STATUS: in aspeed_i3c_device_write()