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Searched refs:R_CISR (Results 1 – 1 of 1) sorted by relevance

/openbmc/qemu/hw/char/
H A Dcadence_uart.c110 #define R_CISR (0x14/4) macro
139 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; in uart_update_status()
140 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0; in uart_update_status()
141 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); in uart_update_status()
149 s->r[R_CISR] |= UART_INTR_TIMEOUT; in fifo_trigger_update()
288 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_rx_fifo()
352 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_tx_fifo()
439 case R_CISR: /* cisr (wtc) */ in uart_write()
440 s->r[R_CISR] &= ~value; in uart_write()
521 s->r[R_CISR] = 0; in cadence_uart_reset_init()