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Searched refs:RVV (Results 1 – 7 of 7) sorted by relevance

/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c375 if (riscv_has_ext(env, RVV)) { in riscv_cpu_validate_set_extensions()
792 MISA_CFG(RVV, false),
968 riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); in riscv_init_max_cpu_extensions()
/openbmc/qemu/target/riscv/
H A Dgdbstub.c322 if (env->misa_ext & RVV) { in riscv_cpu_register_gdb_regs_for_features()
H A Dmachine.c133 return riscv_has_ext(env, RVV); in vector_needed()
H A Dcpu.c42 const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
755 if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) { in riscv_cpu_dump_state()
1255 MISA_EXT_INFO(RVV, "v", "Vector operations"),
H A Dcpu.h65 #define RVV RV('V') macro
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc581 * In cpu_get_tb_cpu_state(), set VILL if RVV was not present.
582 * So RVV is also be checked in this function.
1955 (!has_ext(s, RVV) ? s->sew != MO_64 : true);
1968 (!has_ext(s, RVV) ? s->sew != MO_64 : true);
2177 (!has_ext(s, RVV) ? s->sew != MO_64 : true);
2188 (!has_ext(s, RVV) ? s->sew != MO_64 : true);
/openbmc/qemu/linux-user/
H A Dsyscall.c8852 value |= riscv_has_ext(env, RVV) ? in risc_hwprobe_fill_pairs()