Searched refs:RVV (Results 1 – 7 of 7) sorted by relevance
/openbmc/qemu/target/riscv/tcg/ |
H A D | tcg-cpu.c | 375 if (riscv_has_ext(env, RVV)) { in riscv_cpu_validate_set_extensions() 792 MISA_CFG(RVV, false), 968 riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); in riscv_init_max_cpu_extensions()
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/openbmc/qemu/target/riscv/ |
H A D | gdbstub.c | 322 if (env->misa_ext & RVV) { in riscv_cpu_register_gdb_regs_for_features()
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H A D | machine.c | 133 return riscv_has_ext(env, RVV); in vector_needed()
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H A D | cpu.c | 42 const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV, 755 if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) { in riscv_cpu_dump_state() 1255 MISA_EXT_INFO(RVV, "v", "Vector operations"),
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H A D | cpu.h | 65 #define RVV RV('V') macro
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/openbmc/qemu/target/riscv/insn_trans/ |
H A D | trans_rvv.c.inc | 581 * In cpu_get_tb_cpu_state(), set VILL if RVV was not present. 582 * So RVV is also be checked in this function. 1955 (!has_ext(s, RVV) ? s->sew != MO_64 : true); 1968 (!has_ext(s, RVV) ? s->sew != MO_64 : true); 2177 (!has_ext(s, RVV) ? s->sew != MO_64 : true); 2188 (!has_ext(s, RVV) ? s->sew != MO_64 : true);
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/openbmc/qemu/linux-user/ |
H A D | syscall.c | 8852 value |= riscv_has_ext(env, RVV) ? in risc_hwprobe_fill_pairs()
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