Home
last modified time | relevance | path

Searched refs:RVV (Results 1 – 12 of 12) sorted by relevance

/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/highway/highway/
H A D0001-Add-cmake-check-for-deducing-32bit-or-64bit-RISCV.patch6 Currently its only compilable for RV64 when RVV is
8 RVV as well
58 set(HWY_CMAKE_RVV ON CACHE BOOL "Set copts for RISCV with RVV?")
/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/dav1d/
H A Ddav1d_1.4.3.bb19 # RVV assembler routines are not yet available for RISCV32
/openbmc/openbmc/poky/meta/recipes-devtools/qemu/qemu/
H A Dfix-strerrorname_np.patch27 if (riscv_has_ext(&cpu->env, RVV)) {
/openbmc/qemu/target/riscv/kvm/
H A Dkvm-cpu.c186 KVM_MISA_CFG(RVV, KVM_RISCV_ISA_EXT_V),
778 if (!riscv_has_ext(env, RVV)) { in kvm_riscv_get_regs_vector()
834 if (!riscv_has_ext(env, RVV)) { in kvm_riscv_put_regs_vector()
1175 if (riscv_has_ext(&cpu->env, RVV)) { in kvm_riscv_init_multiext_cfg()
1870 if (riscv_has_ext(&cpu->env, RVV)) { in kvm_cpu_realize()
1892 !riscv_has_ext(env, RVV)) { in riscv_kvm_cpu_finalize_features()
1940 if (riscv_has_ext(env, RVV) && riscv_cpu_option_set("vlen")) { in riscv_kvm_cpu_finalize_features()
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c492 if (riscv_has_ext(env, RVV)) { in riscv_cpu_validate_set_extensions()
1090 MISA_CFG(RVV, false),
1377 riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV); in riscv_init_max_cpu_extensions()
/openbmc/qemu/target/riscv/
H A Dmachine.c133 return riscv_has_ext(env, RVV); in vector_needed()
H A Dcpu.c44 const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
844 if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) { in riscv_cpu_dump_state()
1410 MISA_EXT_INFO(RVV, "v", "Vector operations"),
2305 .ext = RVV,
H A Dcpu.h69 #define RVV RV('V') macro
H A Dcsr.c1621 if (riscv_has_ext(env, RVV)) { in write_mstatus()
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc595 * In cpu_get_tb_cpu_state(), set VILL if RVV was not present.
596 * So RVV is also be checked in this function.
1942 (!has_ext(s, RVV) ? s->sew != MO_64 : true);
1955 (!has_ext(s, RVV) ? s->sew != MO_64 : true);
2153 (!has_ext(s, RVV) ? s->sew != MO_64 : true);
2164 (!has_ext(s, RVV) ? s->sew != MO_64 : true);
/openbmc/qemu/tcg/riscv/
H A Dtcg-target.c.inc689 * With RVV 1.0, vs2 is the first operand, while rs1/imm is the
/openbmc/qemu/linux-user/
H A Dsyscall.c9014 value |= riscv_has_ext(env, RVV) ? in risc_hwprobe_fill_pairs()