Searched refs:RVS (Results 1 – 8 of 8) sorted by relevance
/openbmc/qemu/target/riscv/insn_trans/ |
H A D | trans_svinval.c.inc | 29 REQUIRE_EXT(ctx, RVS); 41 REQUIRE_EXT(ctx, RVS); 49 REQUIRE_EXT(ctx, RVS);
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H A D | trans_privileged.c.inc | 78 if (has_ext(ctx, RVS)) {
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/openbmc/qemu/target/riscv/ |
H A D | cpu.c | 43 RVC, RVS, RVU, RVH, RVJ, RVG, 0}; 437 RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv64_sifive_u_cpu_init() 472 riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); in rv64_thead_c906_cpu_init() 503 riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); in rv64_veyron_v1_cpu_init() 573 RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv32_sifive_u_cpu_init() 1251 MISA_EXT_INFO(RVS, "s", "Supervisor-level instructions"),
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H A D | op_helper.c | 366 bool rvs = riscv_has_ext(env, RVS); in helper_wfi()
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H A D | cpu.h | 67 #define RVS RV('S') macro
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H A D | csr.c | 69 if (env->priv == PRV_U && riscv_has_ext(env, RVS)) { in smstateen_acc_ok() 154 if (riscv_has_ext(env, RVS) && env->priv == PRV_U && in ctr() 262 if (riscv_has_ext(env, RVS)) { in smode() 1296 valid = riscv_has_ext(env, RVS); in legalize_mpp()
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/openbmc/qemu/target/riscv/tcg/ |
H A D | tcg-cpu.c | 324 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { in riscv_cpu_validate_set_extensions() 336 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { in riscv_cpu_validate_set_extensions() 788 MISA_CFG(RVS, true),
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/openbmc/qemu/hw/riscv/ |
H A D | boot.c | 57 } else if (riscv_has_ext(env, RVS)) { in riscv_plic_hart_config_string()
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