Home
last modified time | relevance | path

Searched refs:RVI (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/comedi/drivers/tests/
H A Dni_routes_test.c26 #define RVI(table, src, dest) ((table)[(dest) * NI_NUM_NAMES + (src)]) macro
245 unittest(RVI(table, B(PXI_Star), B(NI_AI_SampleClock)) == V(17) && in test_ni_assign_device_routes()
246 RVI(table, B(NI_10MHzRefClock), B(TRIGGER_LINE(0))) == 0 && in test_ni_assign_device_routes()
247 RVI(table, B(NI_AI_ConvertClock), B(NI_PFI(0))) == 0 && in test_ni_assign_device_routes()
248 RVI(table, B(NI_AI_ConvertClock), B(NI_PFI(2))) == V(NI_PFI_OUTPUT_AI_CONVERT), in test_ni_assign_device_routes()
262 unittest(RVI(table, B(PXI_Star), B(NI_AI_SampleClock)) == V(20) && in test_ni_assign_device_routes()
263 RVI(table, B(NI_10MHzRefClock), B(TRIGGER_LINE(0))) == V(12) && in test_ni_assign_device_routes()
264 RVI(table, B(NI_AI_ConvertClock), B(NI_PFI(0))) == V(3) && in test_ni_assign_device_routes()
265 RVI(table, B(NI_AI_ConvertClock), B(NI_PFI(2))) == V(3), in test_ni_assign_device_routes()
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c287 !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) && in riscv_cpu_validate_set_extensions()
308 env->misa_ext |= RVI | RVM | RVA | RVF | RVD; in riscv_cpu_validate_set_extensions()
309 env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD; in riscv_cpu_validate_set_extensions()
312 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { in riscv_cpu_validate_set_extensions()
318 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { in riscv_cpu_validate_set_extensions()
330 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { in riscv_cpu_validate_set_extensions()
785 MISA_CFG(RVI, true),
/openbmc/qemu/target/riscv/
H A Dcpu.c42 const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
382 riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); in riscv_any_cpu_init()
384 riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); in riscv_any_cpu_init()
437 RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv64_sifive_u_cpu_init()
455 riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); in rv64_sifive_e_cpu_init()
573 RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv32_sifive_u_cpu_init()
591 riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); in rv32_sifive_e_cpu_init()
608 riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); in rv32_ibex_cpu_init()
625 riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); in rv32_imafcu_nommu_cpu_init()
1248 MISA_EXT_INFO(RVI, "i", "Base integer instruction set"),
H A Dxthead.decode50 # the regular RVI `add` instruction.
H A Dcpu.h59 #define RVI RV('I') macro
H A Dcsr.c1441 if (!(val & RVI && val & RVM && val & RVA && in write_misa()
/openbmc/qemu/target/riscv/kvm/
H A Dkvm-cpu.c139 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I),
/openbmc/qemu/linux-user/
H A Dsyscall.c8840 value = riscv_has_ext(env, RVI) && in risc_hwprobe_fill_pairs()