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Searched refs:RVH (Results 1 – 10 of 10) sorted by relevance

/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvh.c.inc67 REQUIRE_EXT(ctx, RVH);
73 REQUIRE_EXT(ctx, RVH);
79 REQUIRE_EXT(ctx, RVH);
85 REQUIRE_EXT(ctx, RVH);
91 REQUIRE_EXT(ctx, RVH);
97 REQUIRE_EXT(ctx, RVH);
103 REQUIRE_EXT(ctx, RVH);
109 REQUIRE_EXT(ctx, RVH);
116 REQUIRE_EXT(ctx, RVH);
123 REQUIRE_EXT(ctx, RVH);
[all …]
H A Dtrans_svinval.c.inc58 REQUIRE_EXT(ctx, RVH);
71 REQUIRE_EXT(ctx, RVH);
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c145 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { in riscv_cpu_validate_misa_priv()
330 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { in riscv_cpu_validate_set_extensions()
336 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { in riscv_cpu_validate_set_extensions()
714 if (riscv_has_ext(env, RVH)) { in tcg_cpu_realize()
790 MISA_CFG(RVH, true),
/openbmc/qemu/target/riscv/
H A Dcpu.c43 RVC, RVS, RVU, RVH, RVJ, RVG, 0};
503 riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); in rv64_veyron_v1_cpu_init()
674 if (riscv_has_ext(env, RVH)) { in riscv_cpu_dump_state()
858 if (riscv_has_ext(env, RVH)) { in riscv_cpu_reset_hold()
1179 if (!riscv_has_ext(env, RVH)) { in riscv_cpu_set_irq()
1253 MISA_EXT_INFO(RVH, "h", "Hypervisor"),
H A Dcpu_helper.c545 g_assert(riscv_has_ext(env, RVH)); in riscv_cpu_swap_hypervisor_regs()
598 if (!riscv_has_ext(env, RVH)) { in riscv_cpu_get_geilen()
607 if (!riscv_has_ext(env, RVH)) { in riscv_cpu_set_geilen()
1742 if (riscv_has_ext(env, RVH)) { in riscv_cpu_do_interrupt()
1790 if (riscv_has_ext(env, RVH)) { in riscv_cpu_do_interrupt()
H A Dop_helper.c297 if (riscv_has_ext(env, RVH) && !env->virt_enabled) { in helper_sret()
352 if (riscv_has_ext(env, RVH)) { in helper_mret()
H A Dmachine.c77 return riscv_has_ext(env, RVH); in hyper_needed()
H A Dcpu.h69 #define RVH RV('H') macro
H A Dcsr.c298 if (riscv_has_ext(env, RVH)) { in hmode()
1338 if (riscv_has_ext(env, RVH)) { in write_mstatus()
1373 uint64_t mask = riscv_has_ext(env, RVH) ? MSTATUS_MPV | MSTATUS_GVA : 0; in write_mstatush()
1500 if (riscv_has_ext(env, RVH)) { in rmw_mideleg64()
1551 if (!riscv_has_ext(env, RVH)) { in rmw_mie64()
4288 if (riscv_has_ext(env, RVH) && env->priv == PRV_S && in riscv_csrrw_check()
/openbmc/qemu/target/riscv/kvm/
H A Dkvm-cpu.c138 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H),