Searched refs:RVG (Results 1 – 4 of 4) sorted by relevance
| /openbmc/qemu/target/riscv/tcg/ |
| H A D | tcg-cpu.c | 286 if (riscv_has_ext(env, RVG) && in riscv_cpu_validate_set_extensions()
793 MISA_CFG(RVG, false),
968 riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); in riscv_init_max_cpu_extensions()
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| /openbmc/qemu/target/riscv/ |
| H A D | cpu.c | 43 RVC, RVS, RVU, RVH, RVJ, RVG, 0};
472 riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); in rv64_thead_c906_cpu_init()
503 riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); in rv64_veyron_v1_cpu_init()
1256 MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
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| H A D | cpu.h | 71 #define RVG RV('G') macro
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| H A D | csr.c | 1443 val &= ~RVG; in write_misa()
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