Searched refs:RVG (Results 1 – 4 of 4) sorted by relevance
| /openbmc/qemu/target/riscv/tcg/ |
| H A D | tcg-cpu.c | 532 const char *warn_msg = "RVG mandates disabled extension %s"; in riscv_cpu_validate_g()
534 bool send_warn = cpu_misa_ext_is_user_set(RVG); in riscv_cpu_validate_g()
609 if (riscv_has_ext(env, RVG)) { in riscv_cpu_validate_set_extensions()
1381 MISA_CFG(RVG, false),
1388 * change MISA bits during realize() (RVG enables MISA
1585 /* Enable RVG and RVV that are disabled by default */ in riscv_init_max_cpu_extensions()
1586 riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVV); in riscv_init_max_cpu_extensions()
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| /openbmc/qemu/target/riscv/ |
| H A D | cpu.c | 44 RVC, RVS, RVU, RVH, RVG, RVB, 0};
1173 MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
3107 .misa_ext = RVG | RVC | RVS | RVU,
3135 .misa_ext = RVG | RVC | RVS | RVU | RVH | RVV,
3195 .misa_ext = RVG | RVC | RVS | RVU | RVH,
3230 .misa_ext = RVG | RVC | RVB | RVS | RVU,
3253 .misa_ext = RVG | RVC | RVB | RVS | RVU | RVH | RVV,
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| H A D | cpu.h | 70 #define RVG RV('G') macro
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| H A D | csr.c | 2150 /* Disable RVG if any of its dependencies are disabled */ in write_misa()
2153 val &= ~RVG; in write_misa()
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