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Searched refs:RVF (Results 1 – 13 of 13) sorted by relevance

/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c308 env->misa_ext |= RVI | RVM | RVA | RVF | RVD; in riscv_cpu_validate_set_extensions()
309 env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD; in riscv_cpu_validate_set_extensions()
341 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) { in riscv_cpu_validate_set_extensions()
351 if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions()
360 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions()
365 if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions()
370 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions()
401 if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions()
450 if (riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions()
483 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { in riscv_cpu_validate_set_extensions()
[all …]
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvzfa.c.inc35 REQUIRE_EXT(ctx, RVF);
184 REQUIRE_EXT(ctx, RVF);
201 REQUIRE_EXT(ctx, RVF);
286 REQUIRE_EXT(ctx, RVF);
303 REQUIRE_EXT(ctx, RVF);
437 REQUIRE_EXT(ctx, RVF);
452 REQUIRE_EXT(ctx, RVF);
H A Dtrans_rvf.c.inc30 REQUIRE_EXT(ctx, RVF); \
36 if (!has_ext(ctx, RVF) || !has_ext(ctx, RVC)) { \
48 REQUIRE_EXT(ctx, RVF);
65 REQUIRE_EXT(ctx, RVF);
H A Dtrans_xthead.c.inc389 REQUIRE_EXT(ctx, RVF);
405 REQUIRE_EXT(ctx, RVF);
421 REQUIRE_EXT(ctx, RVF);
437 REQUIRE_EXT(ctx, RVF);
H A Dtrans_rvv.c.inc2215 * As RVF-only cpus always have values NaN-boxed to 64-bits,
2216 * RVF and RVD can be treated equally.
/openbmc/qemu/target/riscv/
H A Dgdbstub.c115 if (env->misa_ext & RVF) { in riscv_gdb_get_fpu()
318 } else if (env->misa_ext & RVF) { in riscv_cpu_register_gdb_regs_for_features()
H A Dcpu.c42 const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
382 riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); in riscv_any_cpu_init()
384 riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); in riscv_any_cpu_init()
437 RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv64_sifive_u_cpu_init()
573 RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv32_sifive_u_cpu_init()
625 riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); in rv32_imafcu_nommu_cpu_init()
1247 MISA_EXT_INFO(RVF, "f", "Single-precision float point"),
H A Dcsr.c608 if (riscv_has_ext(env, RVF)) { in write_fflags()
627 if (riscv_has_ext(env, RVF)) { in write_frm()
647 if (riscv_has_ext(env, RVF)) { in write_fcsr()
1333 if (riscv_has_ext(env, RVF)) { in write_mstatus()
1442 val & RVF && val & RVD)) { in write_misa()
1464 if (!(env->misa_ext & RVF)) { in write_misa()
2194 if (!riscv_has_ext(env, RVF)) { in write_mstateen0()
2270 if (!riscv_has_ext(env, RVF)) { in write_hstateen0()
2360 if (!riscv_has_ext(env, RVF)) { in write_sstateen0()
H A Dcpu.h63 #define RVF RV('F') macro
H A Dcpu_helper.c124 if (!riscv_has_ext(env, RVF)) { in cpu_get_tb_cpu_state()
540 if (riscv_has_ext(env, RVF)) { in riscv_cpu_swap_hypervisor_regs()
H A Dtranslate.c624 if (!has_ext(ctx, RVF)) { in mark_fs_dirty()
/openbmc/qemu/target/riscv/kvm/
H A Dkvm-cpu.c137 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F),
586 if (riscv_has_ext(env, RVF)) { in kvm_riscv_get_regs_fp()
619 if (riscv_has_ext(env, RVF)) { in kvm_riscv_put_regs_fp()
/openbmc/qemu/linux-user/
H A Dsyscall.c8847 value = riscv_has_ext(env, RVF) && in risc_hwprobe_fill_pairs()