Searched refs:RVE (Results 1 – 5 of 5) sorted by relevance
| /openbmc/qemu/linux-user/riscv/ |
| H A D | cpu_loop.c | 107 if ((env->misa_ext & RVE) && !(env->elf_flags & EF_RISCV_RVE)) { in target_cpu_copy_regs()
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| /openbmc/qemu/target/riscv/tcg/ |
| H A D | tcg-cpu.c | 312 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { in riscv_cpu_validate_set_extensions()
318 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { in riscv_cpu_validate_set_extensions()
786 MISA_CFG(RVE, false),
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| /openbmc/qemu/target/riscv/insn_trans/ |
| H A D | trans_rvzce.c.inc | 120 if (has_ext(ctx, RVE) && rlist > 6) {
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| /openbmc/qemu/target/riscv/ |
| H A D | cpu.h | 60 #define RVE RV('E') /* E and I are mutually exclusive */ macro
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| H A D | cpu.c | 42 const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
1249 MISA_EXT_INFO(RVE, "e", "Base integer instruction set (embedded)"),
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