Searched refs:RVB (Results 1 – 3 of 3) sorted by relevance
| /openbmc/qemu/target/riscv/tcg/ |
| H A D | tcg-cpu.c | 423 if (riscv_has_ext(env, RVB)) { in riscv_cpu_validate_set_extensions()
1056 MISA_CFG(RVB, false),
1341 riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV); in riscv_init_max_cpu_extensions()
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| /openbmc/qemu/target/riscv/ |
| H A D | cpu.h | 71 #define RVB RV('B') macro
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| H A D | cpu.c | 45 RVC, RVS, RVU, RVH, RVJ, RVG, RVB, 0};
1412 MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
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