1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8366RB ethernet switch
3 *
4 * This is a sparsely documented chip, the only viable documentation seems
5 * to be a patched up code drop from the vendor that appear in various
6 * GPL source trees.
7 *
8 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
9 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
10 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
11 * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
12 * Copyright (C) 2011 Colin Leitner <colin.leitner@googlemail.com>
13 */
14
15 #include <linux/bitops.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_bridge.h>
18 #include <linux/interrupt.h>
19 #include <linux/irqdomain.h>
20 #include <linux/irqchip/chained_irq.h>
21 #include <linux/of_irq.h>
22 #include <linux/regmap.h>
23
24 #include "realtek.h"
25
26 #define RTL8366RB_PORT_NUM_CPU 5
27 #define RTL8366RB_NUM_PORTS 6
28 #define RTL8366RB_PHY_NO_MAX 4
29 #define RTL8366RB_PHY_ADDR_MAX 31
30
31 /* Switch Global Configuration register */
32 #define RTL8366RB_SGCR 0x0000
33 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
34 #define RTL8366RB_SGCR_MAX_LENGTH(a) ((a) << 4)
35 #define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
36 #define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
37 #define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
38 #define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
39 #define RTL8366RB_SGCR_MAX_LENGTH_16000 RTL8366RB_SGCR_MAX_LENGTH(0x3)
40 #define RTL8366RB_SGCR_EN_VLAN BIT(13)
41 #define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14)
42
43 /* Port Enable Control register */
44 #define RTL8366RB_PECR 0x0001
45
46 /* Switch per-port learning disablement register */
47 #define RTL8366RB_PORT_LEARNDIS_CTRL 0x0002
48
49 /* Security control, actually aging register */
50 #define RTL8366RB_SECURITY_CTRL 0x0003
51
52 #define RTL8366RB_SSCR2 0x0004
53 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
54
55 /* Port Mode Control registers */
56 #define RTL8366RB_PMC0 0x0005
57 #define RTL8366RB_PMC0_SPI BIT(0)
58 #define RTL8366RB_PMC0_EN_AUTOLOAD BIT(1)
59 #define RTL8366RB_PMC0_PROBE BIT(2)
60 #define RTL8366RB_PMC0_DIS_BISR BIT(3)
61 #define RTL8366RB_PMC0_ADCTEST BIT(4)
62 #define RTL8366RB_PMC0_SRAM_DIAG BIT(5)
63 #define RTL8366RB_PMC0_EN_SCAN BIT(6)
64 #define RTL8366RB_PMC0_P4_IOMODE_SHIFT 7
65 #define RTL8366RB_PMC0_P4_IOMODE_MASK GENMASK(9, 7)
66 #define RTL8366RB_PMC0_P5_IOMODE_SHIFT 10
67 #define RTL8366RB_PMC0_P5_IOMODE_MASK GENMASK(12, 10)
68 #define RTL8366RB_PMC0_SDSMODE_SHIFT 13
69 #define RTL8366RB_PMC0_SDSMODE_MASK GENMASK(15, 13)
70 #define RTL8366RB_PMC1 0x0006
71
72 /* Port Mirror Control Register */
73 #define RTL8366RB_PMCR 0x0007
74 #define RTL8366RB_PMCR_SOURCE_PORT(a) (a)
75 #define RTL8366RB_PMCR_SOURCE_PORT_MASK 0x000f
76 #define RTL8366RB_PMCR_MONITOR_PORT(a) ((a) << 4)
77 #define RTL8366RB_PMCR_MONITOR_PORT_MASK 0x00f0
78 #define RTL8366RB_PMCR_MIRROR_RX BIT(8)
79 #define RTL8366RB_PMCR_MIRROR_TX BIT(9)
80 #define RTL8366RB_PMCR_MIRROR_SPC BIT(10)
81 #define RTL8366RB_PMCR_MIRROR_ISO BIT(11)
82
83 /* bits 0..7 = port 0, bits 8..15 = port 1 */
84 #define RTL8366RB_PAACR0 0x0010
85 /* bits 0..7 = port 2, bits 8..15 = port 3 */
86 #define RTL8366RB_PAACR1 0x0011
87 /* bits 0..7 = port 4, bits 8..15 = port 5 */
88 #define RTL8366RB_PAACR2 0x0012
89 #define RTL8366RB_PAACR_SPEED_10M 0
90 #define RTL8366RB_PAACR_SPEED_100M 1
91 #define RTL8366RB_PAACR_SPEED_1000M 2
92 #define RTL8366RB_PAACR_FULL_DUPLEX BIT(2)
93 #define RTL8366RB_PAACR_LINK_UP BIT(4)
94 #define RTL8366RB_PAACR_TX_PAUSE BIT(5)
95 #define RTL8366RB_PAACR_RX_PAUSE BIT(6)
96 #define RTL8366RB_PAACR_AN BIT(7)
97
98 #define RTL8366RB_PAACR_CPU_PORT (RTL8366RB_PAACR_SPEED_1000M | \
99 RTL8366RB_PAACR_FULL_DUPLEX | \
100 RTL8366RB_PAACR_LINK_UP | \
101 RTL8366RB_PAACR_TX_PAUSE | \
102 RTL8366RB_PAACR_RX_PAUSE)
103
104 /* bits 0..7 = port 0, bits 8..15 = port 1 */
105 #define RTL8366RB_PSTAT0 0x0014
106 /* bits 0..7 = port 2, bits 8..15 = port 3 */
107 #define RTL8366RB_PSTAT1 0x0015
108 /* bits 0..7 = port 4, bits 8..15 = port 5 */
109 #define RTL8366RB_PSTAT2 0x0016
110
111 #define RTL8366RB_POWER_SAVING_REG 0x0021
112
113 /* Spanning tree status (STP) control, two bits per port per FID */
114 #define RTL8366RB_STP_STATE_BASE 0x0050 /* 0x0050..0x0057 */
115 #define RTL8366RB_STP_STATE_DISABLED 0x0
116 #define RTL8366RB_STP_STATE_BLOCKING 0x1
117 #define RTL8366RB_STP_STATE_LEARNING 0x2
118 #define RTL8366RB_STP_STATE_FORWARDING 0x3
119 #define RTL8366RB_STP_MASK GENMASK(1, 0)
120 #define RTL8366RB_STP_STATE(port, state) \
121 ((state) << ((port) * 2))
122 #define RTL8366RB_STP_STATE_MASK(port) \
123 RTL8366RB_STP_STATE((port), RTL8366RB_STP_MASK)
124
125 /* CPU port control reg */
126 #define RTL8368RB_CPU_CTRL_REG 0x0061
127 #define RTL8368RB_CPU_PORTS_MSK 0x00FF
128 /* Disables inserting custom tag length/type 0x8899 */
129 #define RTL8368RB_CPU_NO_TAG BIT(15)
130
131 #define RTL8366RB_SMAR0 0x0070 /* bits 0..15 */
132 #define RTL8366RB_SMAR1 0x0071 /* bits 16..31 */
133 #define RTL8366RB_SMAR2 0x0072 /* bits 32..47 */
134
135 #define RTL8366RB_RESET_CTRL_REG 0x0100
136 #define RTL8366RB_CHIP_CTRL_RESET_HW BIT(0)
137 #define RTL8366RB_CHIP_CTRL_RESET_SW BIT(1)
138
139 #define RTL8366RB_CHIP_ID_REG 0x0509
140 #define RTL8366RB_CHIP_ID_8366 0x5937
141 #define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
142 #define RTL8366RB_CHIP_VERSION_MASK 0xf
143
144 /* PHY registers control */
145 #define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
146 #define RTL8366RB_PHY_CTRL_READ BIT(0)
147 #define RTL8366RB_PHY_CTRL_WRITE 0
148 #define RTL8366RB_PHY_ACCESS_BUSY_REG 0x8001
149 #define RTL8366RB_PHY_INT_BUSY BIT(0)
150 #define RTL8366RB_PHY_EXT_BUSY BIT(4)
151 #define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
152 #define RTL8366RB_PHY_EXT_CTRL_REG 0x8010
153 #define RTL8366RB_PHY_EXT_WRDATA_REG 0x8011
154 #define RTL8366RB_PHY_EXT_RDDATA_REG 0x8012
155
156 #define RTL8366RB_PHY_REG_MASK 0x1f
157 #define RTL8366RB_PHY_PAGE_OFFSET 5
158 #define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
159 #define RTL8366RB_PHY_NO_OFFSET 9
160 #define RTL8366RB_PHY_NO_MASK (0x1f << 9)
161
162 /* VLAN Ingress Control Register 1, one bit per port.
163 * bit 0 .. 5 will make the switch drop ingress frames without
164 * VID such as untagged or priority-tagged frames for respective
165 * port.
166 * bit 6 .. 11 will make the switch drop ingress frames carrying
167 * a C-tag with VID != 0 for respective port.
168 */
169 #define RTL8366RB_VLAN_INGRESS_CTRL1_REG 0x037E
170 #define RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) (BIT((port)) | BIT((port) + 6))
171
172 /* VLAN Ingress Control Register 2, one bit per port.
173 * bit0 .. bit5 will make the switch drop all ingress frames with
174 * a VLAN classification that does not include the port is in its
175 * member set.
176 */
177 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f
178
179 /* LED control registers */
180 #define RTL8366RB_LED_BLINKRATE_REG 0x0430
181 #define RTL8366RB_LED_BLINKRATE_MASK 0x0007
182 #define RTL8366RB_LED_BLINKRATE_28MS 0x0000
183 #define RTL8366RB_LED_BLINKRATE_56MS 0x0001
184 #define RTL8366RB_LED_BLINKRATE_84MS 0x0002
185 #define RTL8366RB_LED_BLINKRATE_111MS 0x0003
186 #define RTL8366RB_LED_BLINKRATE_222MS 0x0004
187 #define RTL8366RB_LED_BLINKRATE_446MS 0x0005
188
189 /* LED trigger event for each group */
190 #define RTL8366RB_LED_CTRL_REG 0x0431
191 #define RTL8366RB_LED_CTRL_OFFSET(led_group) \
192 (4 * (led_group))
193 #define RTL8366RB_LED_CTRL_MASK(led_group) \
194 (0xf << RTL8366RB_LED_CTRL_OFFSET(led_group))
195 #define RTL8366RB_LED_OFF 0x0
196 #define RTL8366RB_LED_DUP_COL 0x1
197 #define RTL8366RB_LED_LINK_ACT 0x2
198 #define RTL8366RB_LED_SPD1000 0x3
199 #define RTL8366RB_LED_SPD100 0x4
200 #define RTL8366RB_LED_SPD10 0x5
201 #define RTL8366RB_LED_SPD1000_ACT 0x6
202 #define RTL8366RB_LED_SPD100_ACT 0x7
203 #define RTL8366RB_LED_SPD10_ACT 0x8
204 #define RTL8366RB_LED_SPD100_10_ACT 0x9
205 #define RTL8366RB_LED_FIBER 0xa
206 #define RTL8366RB_LED_AN_FAULT 0xb
207 #define RTL8366RB_LED_LINK_RX 0xc
208 #define RTL8366RB_LED_LINK_TX 0xd
209 #define RTL8366RB_LED_MASTER 0xe
210 #define RTL8366RB_LED_FORCE 0xf
211
212 /* The RTL8366RB_LED_X_X registers are used to manually set the LED state only
213 * when the corresponding LED group in RTL8366RB_LED_CTRL_REG is
214 * RTL8366RB_LED_FORCE. Otherwise, it is ignored.
215 */
216 #define RTL8366RB_LED_0_1_CTRL_REG 0x0432
217 #define RTL8366RB_LED_1_OFFSET 6
218 #define RTL8366RB_LED_2_3_CTRL_REG 0x0433
219 #define RTL8366RB_LED_3_OFFSET 6
220
221 #define RTL8366RB_MIB_COUNT 33
222 #define RTL8366RB_GLOBAL_MIB_COUNT 1
223 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
224 #define RTL8366RB_MIB_COUNTER_BASE 0x1000
225 #define RTL8366RB_MIB_CTRL_REG 0x13F0
226 #define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
227 #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
228 #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
229 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
230 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
231
232 #define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
233 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
234 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
235 #define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
236 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
237
238 #define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
239 #define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
240
241 #define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
242 #define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
243 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
244
245 #define RTL8366RB_VLAN_MC_BASE(_x) (0x0020 + (_x) * 3)
246
247 #define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
248 #define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
249 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
250 #define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
251 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
252 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
253 #define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
254
255 #define RTL8366RB_NUM_VLANS 16
256 #define RTL8366RB_NUM_LEDGROUPS 4
257 #define RTL8366RB_NUM_VIDS 4096
258 #define RTL8366RB_PRIORITYMAX 7
259 #define RTL8366RB_NUM_FIDS 8
260 #define RTL8366RB_FIDMAX 7
261
262 #define RTL8366RB_PORT_1 BIT(0) /* In userspace port 0 */
263 #define RTL8366RB_PORT_2 BIT(1) /* In userspace port 1 */
264 #define RTL8366RB_PORT_3 BIT(2) /* In userspace port 2 */
265 #define RTL8366RB_PORT_4 BIT(3) /* In userspace port 3 */
266 #define RTL8366RB_PORT_5 BIT(4) /* In userspace port 4 */
267
268 #define RTL8366RB_PORT_CPU BIT(5) /* CPU port */
269
270 #define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
271 RTL8366RB_PORT_2 | \
272 RTL8366RB_PORT_3 | \
273 RTL8366RB_PORT_4 | \
274 RTL8366RB_PORT_5 | \
275 RTL8366RB_PORT_CPU)
276
277 #define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
278 RTL8366RB_PORT_2 | \
279 RTL8366RB_PORT_3 | \
280 RTL8366RB_PORT_4 | \
281 RTL8366RB_PORT_5)
282
283 #define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
284 RTL8366RB_PORT_2 | \
285 RTL8366RB_PORT_3 | \
286 RTL8366RB_PORT_4)
287
288 #define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
289
290 /* First configuration word per member config, VID and prio */
291 #define RTL8366RB_VLAN_VID_MASK 0xfff
292 #define RTL8366RB_VLAN_PRIORITY_SHIFT 12
293 #define RTL8366RB_VLAN_PRIORITY_MASK 0x7
294 /* Second configuration word per member config, member and untagged */
295 #define RTL8366RB_VLAN_UNTAG_SHIFT 8
296 #define RTL8366RB_VLAN_UNTAG_MASK 0xff
297 #define RTL8366RB_VLAN_MEMBER_MASK 0xff
298 /* Third config word per member config, STAG currently unused */
299 #define RTL8366RB_VLAN_STAG_MBR_MASK 0xff
300 #define RTL8366RB_VLAN_STAG_MBR_SHIFT 8
301 #define RTL8366RB_VLAN_STAG_IDX_MASK 0x7
302 #define RTL8366RB_VLAN_STAG_IDX_SHIFT 5
303 #define RTL8366RB_VLAN_FID_MASK 0x7
304
305 /* Port ingress bandwidth control */
306 #define RTL8366RB_IB_BASE 0x0200
307 #define RTL8366RB_IB_REG(pnum) (RTL8366RB_IB_BASE + (pnum))
308 #define RTL8366RB_IB_BDTH_MASK 0x3fff
309 #define RTL8366RB_IB_PREIFG BIT(14)
310
311 /* Port egress bandwidth control */
312 #define RTL8366RB_EB_BASE 0x02d1
313 #define RTL8366RB_EB_REG(pnum) (RTL8366RB_EB_BASE + (pnum))
314 #define RTL8366RB_EB_BDTH_MASK 0x3fff
315 #define RTL8366RB_EB_PREIFG_REG 0x02f8
316 #define RTL8366RB_EB_PREIFG BIT(9)
317
318 #define RTL8366RB_BDTH_SW_MAX 1048512 /* 1048576? */
319 #define RTL8366RB_BDTH_UNIT 64
320 #define RTL8366RB_BDTH_REG_DEFAULT 16383
321
322 /* QOS */
323 #define RTL8366RB_QOS BIT(15)
324 /* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */
325 #define RTL8366RB_QOS_DEFAULT_PREIFG 1
326
327 /* Interrupt handling */
328 #define RTL8366RB_INTERRUPT_CONTROL_REG 0x0440
329 #define RTL8366RB_INTERRUPT_POLARITY BIT(0)
330 #define RTL8366RB_P4_RGMII_LED BIT(2)
331 #define RTL8366RB_INTERRUPT_MASK_REG 0x0441
332 #define RTL8366RB_INTERRUPT_LINK_CHGALL GENMASK(11, 0)
333 #define RTL8366RB_INTERRUPT_ACLEXCEED BIT(8)
334 #define RTL8366RB_INTERRUPT_STORMEXCEED BIT(9)
335 #define RTL8366RB_INTERRUPT_P4_FIBER BIT(12)
336 #define RTL8366RB_INTERRUPT_P4_UTP BIT(13)
337 #define RTL8366RB_INTERRUPT_VALID (RTL8366RB_INTERRUPT_LINK_CHGALL | \
338 RTL8366RB_INTERRUPT_ACLEXCEED | \
339 RTL8366RB_INTERRUPT_STORMEXCEED | \
340 RTL8366RB_INTERRUPT_P4_FIBER | \
341 RTL8366RB_INTERRUPT_P4_UTP)
342 #define RTL8366RB_INTERRUPT_STATUS_REG 0x0442
343 #define RTL8366RB_NUM_INTERRUPT 14 /* 0..13 */
344
345 /* Port isolation registers */
346 #define RTL8366RB_PORT_ISO_BASE 0x0F08
347 #define RTL8366RB_PORT_ISO(pnum) (RTL8366RB_PORT_ISO_BASE + (pnum))
348 #define RTL8366RB_PORT_ISO_EN BIT(0)
349 #define RTL8366RB_PORT_ISO_PORTS_MASK GENMASK(7, 1)
350 #define RTL8366RB_PORT_ISO_PORTS(pmask) ((pmask) << 1)
351
352 /* bits 0..5 enable force when cleared */
353 #define RTL8366RB_MAC_FORCE_CTRL_REG 0x0F11
354
355 #define RTL8366RB_OAM_PARSER_REG 0x0F14
356 #define RTL8366RB_OAM_MULTIPLEXER_REG 0x0F15
357
358 #define RTL8366RB_GREEN_FEATURE_REG 0x0F51
359 #define RTL8366RB_GREEN_FEATURE_MSK 0x0007
360 #define RTL8366RB_GREEN_FEATURE_TX BIT(0)
361 #define RTL8366RB_GREEN_FEATURE_RX BIT(2)
362
363 /**
364 * struct rtl8366rb - RTL8366RB-specific data
365 * @max_mtu: per-port max MTU setting
366 * @pvid_enabled: if PVID is set for respective port
367 */
368 struct rtl8366rb {
369 unsigned int max_mtu[RTL8366RB_NUM_PORTS];
370 bool pvid_enabled[RTL8366RB_NUM_PORTS];
371 };
372
373 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
374 { 0, 0, 4, "IfInOctets" },
375 { 0, 4, 4, "EtherStatsOctets" },
376 { 0, 8, 2, "EtherStatsUnderSizePkts" },
377 { 0, 10, 2, "EtherFragments" },
378 { 0, 12, 2, "EtherStatsPkts64Octets" },
379 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
380 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
381 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
382 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
383 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
384 { 0, 24, 2, "EtherOversizeStats" },
385 { 0, 26, 2, "EtherStatsJabbers" },
386 { 0, 28, 2, "IfInUcastPkts" },
387 { 0, 30, 2, "EtherStatsMulticastPkts" },
388 { 0, 32, 2, "EtherStatsBroadcastPkts" },
389 { 0, 34, 2, "EtherStatsDropEvents" },
390 { 0, 36, 2, "Dot3StatsFCSErrors" },
391 { 0, 38, 2, "Dot3StatsSymbolErrors" },
392 { 0, 40, 2, "Dot3InPauseFrames" },
393 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
394 { 0, 44, 4, "IfOutOctets" },
395 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
396 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
397 { 0, 52, 2, "Dot3sDeferredTransmissions" },
398 { 0, 54, 2, "Dot3StatsLateCollisions" },
399 { 0, 56, 2, "EtherStatsCollisions" },
400 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
401 { 0, 60, 2, "Dot3OutPauseFrames" },
402 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
403 { 0, 64, 2, "Dot1dTpPortInDiscards" },
404 { 0, 66, 2, "IfOutUcastPkts" },
405 { 0, 68, 2, "IfOutMulticastPkts" },
406 { 0, 70, 2, "IfOutBroadcastPkts" },
407 };
408
rtl8366rb_get_mib_counter(struct realtek_priv * priv,int port,struct rtl8366_mib_counter * mib,u64 * mibvalue)409 static int rtl8366rb_get_mib_counter(struct realtek_priv *priv,
410 int port,
411 struct rtl8366_mib_counter *mib,
412 u64 *mibvalue)
413 {
414 u32 addr, val;
415 int ret;
416 int i;
417
418 addr = RTL8366RB_MIB_COUNTER_BASE +
419 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
420 mib->offset;
421
422 /* Writing access counter address first
423 * then ASIC will prepare 64bits counter wait for being retrived
424 */
425 ret = regmap_write(priv->map, addr, 0); /* Write whatever */
426 if (ret)
427 return ret;
428
429 /* Read MIB control register */
430 ret = regmap_read(priv->map, RTL8366RB_MIB_CTRL_REG, &val);
431 if (ret)
432 return -EIO;
433
434 if (val & RTL8366RB_MIB_CTRL_BUSY_MASK)
435 return -EBUSY;
436
437 if (val & RTL8366RB_MIB_CTRL_RESET_MASK)
438 return -EIO;
439
440 /* Read each individual MIB 16 bits at the time */
441 *mibvalue = 0;
442 for (i = mib->length; i > 0; i--) {
443 ret = regmap_read(priv->map, addr + (i - 1), &val);
444 if (ret)
445 return ret;
446 *mibvalue = (*mibvalue << 16) | (val & 0xFFFF);
447 }
448 return 0;
449 }
450
rtl8366rb_get_irqmask(struct irq_data * d)451 static u32 rtl8366rb_get_irqmask(struct irq_data *d)
452 {
453 int line = irqd_to_hwirq(d);
454 u32 val;
455
456 /* For line interrupts we combine link down in bits
457 * 6..11 with link up in bits 0..5 into one interrupt.
458 */
459 if (line < 12)
460 val = BIT(line) | BIT(line + 6);
461 else
462 val = BIT(line);
463 return val;
464 }
465
rtl8366rb_mask_irq(struct irq_data * d)466 static void rtl8366rb_mask_irq(struct irq_data *d)
467 {
468 struct realtek_priv *priv = irq_data_get_irq_chip_data(d);
469 int ret;
470
471 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG,
472 rtl8366rb_get_irqmask(d), 0);
473 if (ret)
474 dev_err(priv->dev, "could not mask IRQ\n");
475 }
476
rtl8366rb_unmask_irq(struct irq_data * d)477 static void rtl8366rb_unmask_irq(struct irq_data *d)
478 {
479 struct realtek_priv *priv = irq_data_get_irq_chip_data(d);
480 int ret;
481
482 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG,
483 rtl8366rb_get_irqmask(d),
484 rtl8366rb_get_irqmask(d));
485 if (ret)
486 dev_err(priv->dev, "could not unmask IRQ\n");
487 }
488
rtl8366rb_irq(int irq,void * data)489 static irqreturn_t rtl8366rb_irq(int irq, void *data)
490 {
491 struct realtek_priv *priv = data;
492 u32 stat;
493 int ret;
494
495 /* This clears the IRQ status register */
496 ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG,
497 &stat);
498 if (ret) {
499 dev_err(priv->dev, "can't read interrupt status\n");
500 return IRQ_NONE;
501 }
502 stat &= RTL8366RB_INTERRUPT_VALID;
503 if (!stat)
504 return IRQ_NONE;
505 while (stat) {
506 int line = __ffs(stat);
507 int child_irq;
508
509 stat &= ~BIT(line);
510 /* For line interrupts we combine link down in bits
511 * 6..11 with link up in bits 0..5 into one interrupt.
512 */
513 if (line < 12 && line > 5)
514 line -= 5;
515 child_irq = irq_find_mapping(priv->irqdomain, line);
516 handle_nested_irq(child_irq);
517 }
518 return IRQ_HANDLED;
519 }
520
521 static struct irq_chip rtl8366rb_irq_chip = {
522 .name = "RTL8366RB",
523 .irq_mask = rtl8366rb_mask_irq,
524 .irq_unmask = rtl8366rb_unmask_irq,
525 };
526
rtl8366rb_irq_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)527 static int rtl8366rb_irq_map(struct irq_domain *domain, unsigned int irq,
528 irq_hw_number_t hwirq)
529 {
530 irq_set_chip_data(irq, domain->host_data);
531 irq_set_chip_and_handler(irq, &rtl8366rb_irq_chip, handle_simple_irq);
532 irq_set_nested_thread(irq, 1);
533 irq_set_noprobe(irq);
534
535 return 0;
536 }
537
rtl8366rb_irq_unmap(struct irq_domain * d,unsigned int irq)538 static void rtl8366rb_irq_unmap(struct irq_domain *d, unsigned int irq)
539 {
540 irq_set_nested_thread(irq, 0);
541 irq_set_chip_and_handler(irq, NULL, NULL);
542 irq_set_chip_data(irq, NULL);
543 }
544
545 static const struct irq_domain_ops rtl8366rb_irqdomain_ops = {
546 .map = rtl8366rb_irq_map,
547 .unmap = rtl8366rb_irq_unmap,
548 .xlate = irq_domain_xlate_onecell,
549 };
550
rtl8366rb_setup_cascaded_irq(struct realtek_priv * priv)551 static int rtl8366rb_setup_cascaded_irq(struct realtek_priv *priv)
552 {
553 struct device_node *intc;
554 unsigned long irq_trig;
555 int irq;
556 int ret;
557 u32 val;
558 int i;
559
560 intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller");
561 if (!intc) {
562 dev_err(priv->dev, "missing child interrupt-controller node\n");
563 return -EINVAL;
564 }
565 /* RB8366RB IRQs cascade off this one */
566 irq = of_irq_get(intc, 0);
567 if (irq <= 0) {
568 dev_err(priv->dev, "failed to get parent IRQ\n");
569 ret = irq ? irq : -EINVAL;
570 goto out_put_node;
571 }
572
573 /* This clears the IRQ status register */
574 ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG,
575 &val);
576 if (ret) {
577 dev_err(priv->dev, "can't read interrupt status\n");
578 goto out_put_node;
579 }
580
581 /* Fetch IRQ edge information from the descriptor */
582 irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq));
583 switch (irq_trig) {
584 case IRQF_TRIGGER_RISING:
585 case IRQF_TRIGGER_HIGH:
586 dev_info(priv->dev, "active high/rising IRQ\n");
587 val = 0;
588 break;
589 case IRQF_TRIGGER_FALLING:
590 case IRQF_TRIGGER_LOW:
591 dev_info(priv->dev, "active low/falling IRQ\n");
592 val = RTL8366RB_INTERRUPT_POLARITY;
593 break;
594 }
595 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_CONTROL_REG,
596 RTL8366RB_INTERRUPT_POLARITY,
597 val);
598 if (ret) {
599 dev_err(priv->dev, "could not configure IRQ polarity\n");
600 goto out_put_node;
601 }
602
603 ret = devm_request_threaded_irq(priv->dev, irq, NULL,
604 rtl8366rb_irq, IRQF_ONESHOT,
605 "RTL8366RB", priv);
606 if (ret) {
607 dev_err(priv->dev, "unable to request irq: %d\n", ret);
608 goto out_put_node;
609 }
610 priv->irqdomain = irq_domain_add_linear(intc,
611 RTL8366RB_NUM_INTERRUPT,
612 &rtl8366rb_irqdomain_ops,
613 priv);
614 if (!priv->irqdomain) {
615 dev_err(priv->dev, "failed to create IRQ domain\n");
616 ret = -EINVAL;
617 goto out_put_node;
618 }
619 for (i = 0; i < priv->num_ports; i++)
620 irq_set_parent(irq_create_mapping(priv->irqdomain, i), irq);
621
622 out_put_node:
623 of_node_put(intc);
624 return ret;
625 }
626
rtl8366rb_set_addr(struct realtek_priv * priv)627 static int rtl8366rb_set_addr(struct realtek_priv *priv)
628 {
629 u8 addr[ETH_ALEN];
630 u16 val;
631 int ret;
632
633 eth_random_addr(addr);
634
635 dev_info(priv->dev, "set MAC: %02X:%02X:%02X:%02X:%02X:%02X\n",
636 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
637 val = addr[0] << 8 | addr[1];
638 ret = regmap_write(priv->map, RTL8366RB_SMAR0, val);
639 if (ret)
640 return ret;
641 val = addr[2] << 8 | addr[3];
642 ret = regmap_write(priv->map, RTL8366RB_SMAR1, val);
643 if (ret)
644 return ret;
645 val = addr[4] << 8 | addr[5];
646 ret = regmap_write(priv->map, RTL8366RB_SMAR2, val);
647 if (ret)
648 return ret;
649
650 return 0;
651 }
652
653 /* Found in a vendor driver */
654
655 /* Struct for handling the jam tables' entries */
656 struct rtl8366rb_jam_tbl_entry {
657 u16 reg;
658 u16 val;
659 };
660
661 /* For the "version 0" early silicon, appear in most source releases */
662 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_0[] = {
663 {0x000B, 0x0001}, {0x03A6, 0x0100}, {0x03A7, 0x0001}, {0x02D1, 0x3FFF},
664 {0x02D2, 0x3FFF}, {0x02D3, 0x3FFF}, {0x02D4, 0x3FFF}, {0x02D5, 0x3FFF},
665 {0x02D6, 0x3FFF}, {0x02D7, 0x3FFF}, {0x02D8, 0x3FFF}, {0x022B, 0x0688},
666 {0x022C, 0x0FAC}, {0x03D0, 0x4688}, {0x03D1, 0x01F5}, {0x0000, 0x0830},
667 {0x02F9, 0x0200}, {0x02F7, 0x7FFF}, {0x02F8, 0x03FF}, {0x0080, 0x03E8},
668 {0x0081, 0x00CE}, {0x0082, 0x00DA}, {0x0083, 0x0230}, {0xBE0F, 0x2000},
669 {0x0231, 0x422A}, {0x0232, 0x422A}, {0x0233, 0x422A}, {0x0234, 0x422A},
670 {0x0235, 0x422A}, {0x0236, 0x422A}, {0x0237, 0x422A}, {0x0238, 0x422A},
671 {0x0239, 0x422A}, {0x023A, 0x422A}, {0x023B, 0x422A}, {0x023C, 0x422A},
672 {0x023D, 0x422A}, {0x023E, 0x422A}, {0x023F, 0x422A}, {0x0240, 0x422A},
673 {0x0241, 0x422A}, {0x0242, 0x422A}, {0x0243, 0x422A}, {0x0244, 0x422A},
674 {0x0245, 0x422A}, {0x0246, 0x422A}, {0x0247, 0x422A}, {0x0248, 0x422A},
675 {0x0249, 0x0146}, {0x024A, 0x0146}, {0x024B, 0x0146}, {0xBE03, 0xC961},
676 {0x024D, 0x0146}, {0x024E, 0x0146}, {0x024F, 0x0146}, {0x0250, 0x0146},
677 {0xBE64, 0x0226}, {0x0252, 0x0146}, {0x0253, 0x0146}, {0x024C, 0x0146},
678 {0x0251, 0x0146}, {0x0254, 0x0146}, {0xBE62, 0x3FD0}, {0x0084, 0x0320},
679 {0x0255, 0x0146}, {0x0256, 0x0146}, {0x0257, 0x0146}, {0x0258, 0x0146},
680 {0x0259, 0x0146}, {0x025A, 0x0146}, {0x025B, 0x0146}, {0x025C, 0x0146},
681 {0x025D, 0x0146}, {0x025E, 0x0146}, {0x025F, 0x0146}, {0x0260, 0x0146},
682 {0x0261, 0xA23F}, {0x0262, 0x0294}, {0x0263, 0xA23F}, {0x0264, 0x0294},
683 {0x0265, 0xA23F}, {0x0266, 0x0294}, {0x0267, 0xA23F}, {0x0268, 0x0294},
684 {0x0269, 0xA23F}, {0x026A, 0x0294}, {0x026B, 0xA23F}, {0x026C, 0x0294},
685 {0x026D, 0xA23F}, {0x026E, 0x0294}, {0x026F, 0xA23F}, {0x0270, 0x0294},
686 {0x02F5, 0x0048}, {0xBE09, 0x0E00}, {0xBE1E, 0x0FA0}, {0xBE14, 0x8448},
687 {0xBE15, 0x1007}, {0xBE4A, 0xA284}, {0xC454, 0x3F0B}, {0xC474, 0x3F0B},
688 {0xBE48, 0x3672}, {0xBE4B, 0x17A7}, {0xBE4C, 0x0B15}, {0xBE52, 0x0EDD},
689 {0xBE49, 0x8C00}, {0xBE5B, 0x785C}, {0xBE5C, 0x785C}, {0xBE5D, 0x785C},
690 {0xBE61, 0x368A}, {0xBE63, 0x9B84}, {0xC456, 0xCC13}, {0xC476, 0xCC13},
691 {0xBE65, 0x307D}, {0xBE6D, 0x0005}, {0xBE6E, 0xE120}, {0xBE2E, 0x7BAF},
692 };
693
694 /* This v1 init sequence is from Belkin F5D8235 U-Boot release */
695 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_1[] = {
696 {0x0000, 0x0830}, {0x0001, 0x8000}, {0x0400, 0x8130}, {0xBE78, 0x3C3C},
697 {0x0431, 0x5432}, {0xBE37, 0x0CE4}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0},
698 {0xC44C, 0x1585}, {0xC44C, 0x1185}, {0xC44C, 0x1585}, {0xC46C, 0x1585},
699 {0xC46C, 0x1185}, {0xC46C, 0x1585}, {0xC451, 0x2135}, {0xC471, 0x2135},
700 {0xBE10, 0x8140}, {0xBE15, 0x0007}, {0xBE6E, 0xE120}, {0xBE69, 0xD20F},
701 {0xBE6B, 0x0320}, {0xBE24, 0xB000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF20},
702 {0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800}, {0xBE24, 0x0000},
703 {0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60}, {0xBE21, 0x0140},
704 {0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000}, {0xBE2E, 0x7B7A},
705 {0xBE36, 0x0CE4}, {0x02F5, 0x0048}, {0xBE77, 0x2940}, {0x000A, 0x83E0},
706 {0xBE79, 0x3C3C}, {0xBE00, 0x1340},
707 };
708
709 /* This v2 init sequence is from Belkin F5D8235 U-Boot release */
710 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_2[] = {
711 {0x0450, 0x0000}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432},
712 {0xC44F, 0x6250}, {0xC46F, 0x6250}, {0xC456, 0x0C14}, {0xC476, 0x0C14},
713 {0xC44C, 0x1C85}, {0xC44C, 0x1885}, {0xC44C, 0x1C85}, {0xC46C, 0x1C85},
714 {0xC46C, 0x1885}, {0xC46C, 0x1C85}, {0xC44C, 0x0885}, {0xC44C, 0x0881},
715 {0xC44C, 0x0885}, {0xC46C, 0x0885}, {0xC46C, 0x0881}, {0xC46C, 0x0885},
716 {0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001},
717 {0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6E, 0x0320},
718 {0xBE77, 0x2940}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120},
719 {0x8000, 0x0001}, {0xBE15, 0x1007}, {0x8000, 0x0000}, {0xBE15, 0x1007},
720 {0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160}, {0xBE10, 0x8140},
721 {0xBE00, 0x1340}, {0x0F51, 0x0010},
722 };
723
724 /* Appears in a DDWRT code dump */
725 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_3[] = {
726 {0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432},
727 {0x0F51, 0x0017}, {0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0},
728 {0xC456, 0x0C14}, {0xC476, 0x0C14}, {0xC454, 0x3F8B}, {0xC474, 0x3F8B},
729 {0xC450, 0x2071}, {0xC470, 0x2071}, {0xC451, 0x226B}, {0xC471, 0x226B},
730 {0xC452, 0xA293}, {0xC472, 0xA293}, {0xC44C, 0x1585}, {0xC44C, 0x1185},
731 {0xC44C, 0x1585}, {0xC46C, 0x1585}, {0xC46C, 0x1185}, {0xC46C, 0x1585},
732 {0xC44C, 0x0185}, {0xC44C, 0x0181}, {0xC44C, 0x0185}, {0xC46C, 0x0185},
733 {0xC46C, 0x0181}, {0xC46C, 0x0185}, {0xBE24, 0xB000}, {0xBE23, 0xFF51},
734 {0xBE22, 0xDF20}, {0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800},
735 {0xBE24, 0x0000}, {0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60},
736 {0xBE21, 0x0140}, {0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000},
737 {0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001},
738 {0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6B, 0x0320},
739 {0xBE77, 0x2800}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120},
740 {0x8000, 0x0001}, {0xBE10, 0x8140}, {0x8000, 0x0000}, {0xBE10, 0x8140},
741 {0xBE15, 0x1007}, {0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160},
742 {0xBE10, 0x8140}, {0xBE00, 0x1340}, {0x0450, 0x0000}, {0x0401, 0x0000},
743 };
744
745 /* Belkin F5D8235 v1, "belkin,f5d8235-v1" */
746 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_f5d8235[] = {
747 {0x0242, 0x02BF}, {0x0245, 0x02BF}, {0x0248, 0x02BF}, {0x024B, 0x02BF},
748 {0x024E, 0x02BF}, {0x0251, 0x02BF}, {0x0254, 0x0A3F}, {0x0256, 0x0A3F},
749 {0x0258, 0x0A3F}, {0x025A, 0x0A3F}, {0x025C, 0x0A3F}, {0x025E, 0x0A3F},
750 {0x0263, 0x007C}, {0x0100, 0x0004}, {0xBE5B, 0x3500}, {0x800E, 0x200F},
751 {0xBE1D, 0x0F00}, {0x8001, 0x5011}, {0x800A, 0xA2F4}, {0x800B, 0x17A3},
752 {0xBE4B, 0x17A3}, {0xBE41, 0x5011}, {0xBE17, 0x2100}, {0x8000, 0x8304},
753 {0xBE40, 0x8304}, {0xBE4A, 0xA2F4}, {0x800C, 0xA8D5}, {0x8014, 0x5500},
754 {0x8015, 0x0004}, {0xBE4C, 0xA8D5}, {0xBE59, 0x0008}, {0xBE09, 0x0E00},
755 {0xBE36, 0x1036}, {0xBE37, 0x1036}, {0x800D, 0x00FF}, {0xBE4D, 0x00FF},
756 };
757
758 /* DGN3500, "netgear,dgn3500", "netgear,dgn3500b" */
759 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_dgn3500[] = {
760 {0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0F51, 0x0017},
761 {0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0}, {0x0450, 0x0000},
762 {0x0401, 0x0000}, {0x0431, 0x0960},
763 };
764
765 /* This jam table activates "green ethernet", which means low power mode
766 * and is claimed to detect the cable length and not use more power than
767 * necessary, and the ports should enter power saving mode 10 seconds after
768 * a cable is disconnected. Seems to always be the same.
769 */
770 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_green_jam[] = {
771 {0xBE78, 0x323C}, {0xBE77, 0x5000}, {0xBE2E, 0x7BA7},
772 {0xBE59, 0x3459}, {0xBE5A, 0x745A}, {0xBE5B, 0x785C},
773 {0xBE5C, 0x785C}, {0xBE6E, 0xE120}, {0xBE79, 0x323C},
774 };
775
776 /* Function that jams the tables in the proper registers */
rtl8366rb_jam_table(const struct rtl8366rb_jam_tbl_entry * jam_table,int jam_size,struct realtek_priv * priv,bool write_dbg)777 static int rtl8366rb_jam_table(const struct rtl8366rb_jam_tbl_entry *jam_table,
778 int jam_size, struct realtek_priv *priv,
779 bool write_dbg)
780 {
781 u32 val;
782 int ret;
783 int i;
784
785 for (i = 0; i < jam_size; i++) {
786 if ((jam_table[i].reg & 0xBE00) == 0xBE00) {
787 ret = regmap_read(priv->map,
788 RTL8366RB_PHY_ACCESS_BUSY_REG,
789 &val);
790 if (ret)
791 return ret;
792 if (!(val & RTL8366RB_PHY_INT_BUSY)) {
793 ret = regmap_write(priv->map,
794 RTL8366RB_PHY_ACCESS_CTRL_REG,
795 RTL8366RB_PHY_CTRL_WRITE);
796 if (ret)
797 return ret;
798 }
799 }
800 if (write_dbg)
801 dev_dbg(priv->dev, "jam %04x into register %04x\n",
802 jam_table[i].val,
803 jam_table[i].reg);
804 ret = regmap_write(priv->map,
805 jam_table[i].reg,
806 jam_table[i].val);
807 if (ret)
808 return ret;
809 }
810 return 0;
811 }
812
rtl8366rb_setup(struct dsa_switch * ds)813 static int rtl8366rb_setup(struct dsa_switch *ds)
814 {
815 struct realtek_priv *priv = ds->priv;
816 const struct rtl8366rb_jam_tbl_entry *jam_table;
817 struct rtl8366rb *rb;
818 u32 chip_ver = 0;
819 u32 chip_id = 0;
820 int jam_size;
821 u32 val;
822 int ret;
823 int i;
824
825 rb = priv->chip_data;
826
827 ret = regmap_read(priv->map, RTL8366RB_CHIP_ID_REG, &chip_id);
828 if (ret) {
829 dev_err(priv->dev, "unable to read chip id\n");
830 return ret;
831 }
832
833 switch (chip_id) {
834 case RTL8366RB_CHIP_ID_8366:
835 break;
836 default:
837 dev_err(priv->dev, "unknown chip id (%04x)\n", chip_id);
838 return -ENODEV;
839 }
840
841 ret = regmap_read(priv->map, RTL8366RB_CHIP_VERSION_CTRL_REG,
842 &chip_ver);
843 if (ret) {
844 dev_err(priv->dev, "unable to read chip version\n");
845 return ret;
846 }
847
848 dev_info(priv->dev, "RTL%04x ver %u chip found\n",
849 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
850
851 /* Do the init dance using the right jam table */
852 switch (chip_ver) {
853 case 0:
854 jam_table = rtl8366rb_init_jam_ver_0;
855 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_0);
856 break;
857 case 1:
858 jam_table = rtl8366rb_init_jam_ver_1;
859 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_1);
860 break;
861 case 2:
862 jam_table = rtl8366rb_init_jam_ver_2;
863 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_2);
864 break;
865 default:
866 jam_table = rtl8366rb_init_jam_ver_3;
867 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_3);
868 break;
869 }
870
871 /* Special jam tables for special routers
872 * TODO: are these necessary? Maintainers, please test
873 * without them, using just the off-the-shelf tables.
874 */
875 if (of_machine_is_compatible("belkin,f5d8235-v1")) {
876 jam_table = rtl8366rb_init_jam_f5d8235;
877 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_f5d8235);
878 }
879 if (of_machine_is_compatible("netgear,dgn3500") ||
880 of_machine_is_compatible("netgear,dgn3500b")) {
881 jam_table = rtl8366rb_init_jam_dgn3500;
882 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_dgn3500);
883 }
884
885 ret = rtl8366rb_jam_table(jam_table, jam_size, priv, true);
886 if (ret)
887 return ret;
888
889 /* Isolate all user ports so they can only send packets to itself and the CPU port */
890 for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {
891 ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(i),
892 RTL8366RB_PORT_ISO_PORTS(BIT(RTL8366RB_PORT_NUM_CPU)) |
893 RTL8366RB_PORT_ISO_EN);
894 if (ret)
895 return ret;
896 }
897 /* CPU port can send packets to all ports */
898 ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(RTL8366RB_PORT_NUM_CPU),
899 RTL8366RB_PORT_ISO_PORTS(dsa_user_ports(ds)) |
900 RTL8366RB_PORT_ISO_EN);
901 if (ret)
902 return ret;
903
904 /* Set up the "green ethernet" feature */
905 ret = rtl8366rb_jam_table(rtl8366rb_green_jam,
906 ARRAY_SIZE(rtl8366rb_green_jam), priv, false);
907 if (ret)
908 return ret;
909
910 ret = regmap_write(priv->map,
911 RTL8366RB_GREEN_FEATURE_REG,
912 (chip_ver == 1) ? 0x0007 : 0x0003);
913 if (ret)
914 return ret;
915
916 /* Vendor driver sets 0x240 in registers 0xc and 0xd (undocumented) */
917 ret = regmap_write(priv->map, 0x0c, 0x240);
918 if (ret)
919 return ret;
920 ret = regmap_write(priv->map, 0x0d, 0x240);
921 if (ret)
922 return ret;
923
924 /* Set some random MAC address */
925 ret = rtl8366rb_set_addr(priv);
926 if (ret)
927 return ret;
928
929 /* Enable CPU port with custom DSA tag 8899.
930 *
931 * If you set RTL8368RB_CPU_NO_TAG (bit 15) in this registers
932 * the custom tag is turned off.
933 */
934 ret = regmap_update_bits(priv->map, RTL8368RB_CPU_CTRL_REG,
935 0xFFFF,
936 BIT(priv->cpu_port));
937 if (ret)
938 return ret;
939
940 /* Make sure we default-enable the fixed CPU port */
941 ret = regmap_update_bits(priv->map, RTL8366RB_PECR,
942 BIT(priv->cpu_port),
943 0);
944 if (ret)
945 return ret;
946
947 /* Set maximum packet length to 1536 bytes */
948 ret = regmap_update_bits(priv->map, RTL8366RB_SGCR,
949 RTL8366RB_SGCR_MAX_LENGTH_MASK,
950 RTL8366RB_SGCR_MAX_LENGTH_1536);
951 if (ret)
952 return ret;
953 for (i = 0; i < RTL8366RB_NUM_PORTS; i++)
954 /* layer 2 size, see rtl8366rb_change_mtu() */
955 rb->max_mtu[i] = 1532;
956
957 /* Disable learning for all ports */
958 ret = regmap_write(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL,
959 RTL8366RB_PORT_ALL);
960 if (ret)
961 return ret;
962
963 /* Enable auto ageing for all ports */
964 ret = regmap_write(priv->map, RTL8366RB_SECURITY_CTRL, 0);
965 if (ret)
966 return ret;
967
968 /* Port 4 setup: this enables Port 4, usually the WAN port,
969 * common PHY IO mode is apparently mode 0, and this is not what
970 * the port is initialized to. There is no explanation of the
971 * IO modes in the Realtek source code, if your WAN port is
972 * connected to something exotic such as fiber, then this might
973 * be worth experimenting with.
974 */
975 ret = regmap_update_bits(priv->map, RTL8366RB_PMC0,
976 RTL8366RB_PMC0_P4_IOMODE_MASK,
977 0 << RTL8366RB_PMC0_P4_IOMODE_SHIFT);
978 if (ret)
979 return ret;
980
981 /* Accept all packets by default, we enable filtering on-demand */
982 ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG,
983 0);
984 if (ret)
985 return ret;
986 ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,
987 0);
988 if (ret)
989 return ret;
990
991 /* Don't drop packets whose DA has not been learned */
992 ret = regmap_update_bits(priv->map, RTL8366RB_SSCR2,
993 RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
994 if (ret)
995 return ret;
996
997 /* Set blinking, TODO: make this configurable */
998 ret = regmap_update_bits(priv->map, RTL8366RB_LED_BLINKRATE_REG,
999 RTL8366RB_LED_BLINKRATE_MASK,
1000 RTL8366RB_LED_BLINKRATE_56MS);
1001 if (ret)
1002 return ret;
1003
1004 /* Set up LED activity:
1005 * Each port has 4 LEDs, we configure all ports to the same
1006 * behaviour (no individual config) but we can set up each
1007 * LED separately.
1008 */
1009 if (priv->leds_disabled) {
1010 /* Turn everything off */
1011 regmap_update_bits(priv->map,
1012 RTL8366RB_INTERRUPT_CONTROL_REG,
1013 RTL8366RB_P4_RGMII_LED,
1014 0);
1015
1016 for (i = 0; i < RTL8366RB_NUM_LEDGROUPS; i++) {
1017 val = RTL8366RB_LED_OFF << RTL8366RB_LED_CTRL_OFFSET(i);
1018 ret = regmap_update_bits(priv->map,
1019 RTL8366RB_LED_CTRL_REG,
1020 RTL8366RB_LED_CTRL_MASK(i),
1021 val);
1022 if (ret)
1023 return ret;
1024 }
1025 }
1026
1027 ret = rtl8366_reset_vlan(priv);
1028 if (ret)
1029 return ret;
1030
1031 ret = rtl8366rb_setup_cascaded_irq(priv);
1032 if (ret)
1033 dev_info(priv->dev, "no interrupt support\n");
1034
1035 if (priv->setup_interface) {
1036 ret = priv->setup_interface(ds);
1037 if (ret) {
1038 dev_err(priv->dev, "could not set up MDIO bus\n");
1039 return -ENODEV;
1040 }
1041 }
1042
1043 return 0;
1044 }
1045
rtl8366_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)1046 static enum dsa_tag_protocol rtl8366_get_tag_protocol(struct dsa_switch *ds,
1047 int port,
1048 enum dsa_tag_protocol mp)
1049 {
1050 /* This switch uses the 4 byte protocol A Realtek DSA tag */
1051 return DSA_TAG_PROTO_RTL4_A;
1052 }
1053
rtl8366rb_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)1054 static void rtl8366rb_phylink_get_caps(struct dsa_switch *ds, int port,
1055 struct phylink_config *config)
1056 {
1057 unsigned long *interfaces = config->supported_interfaces;
1058 struct realtek_priv *priv = ds->priv;
1059
1060 if (port == priv->cpu_port) {
1061 __set_bit(PHY_INTERFACE_MODE_MII, interfaces);
1062 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces);
1063 /* REVMII only supports 100M FD */
1064 __set_bit(PHY_INTERFACE_MODE_REVMII, interfaces);
1065 /* RGMII only supports 1G FD */
1066 phy_interface_set_rgmii(interfaces);
1067
1068 config->mac_capabilities = MAC_1000 | MAC_100 |
1069 MAC_SYM_PAUSE;
1070 } else {
1071 /* RSGMII port, but we don't have that, and we don't
1072 * specify in DT, so phylib uses the default of GMII
1073 */
1074 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces);
1075 config->mac_capabilities = MAC_1000 | MAC_100 | MAC_10 |
1076 MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
1077 }
1078 }
1079
1080 static void
rtl8366rb_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)1081 rtl8366rb_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode,
1082 phy_interface_t interface, struct phy_device *phydev,
1083 int speed, int duplex, bool tx_pause, bool rx_pause)
1084 {
1085 struct realtek_priv *priv = ds->priv;
1086 int ret;
1087
1088 if (port != priv->cpu_port)
1089 return;
1090
1091 dev_dbg(priv->dev, "MAC link up on CPU port (%d)\n", port);
1092
1093 /* Force the fixed CPU port into 1Gbit mode, no autonegotiation */
1094 ret = regmap_update_bits(priv->map, RTL8366RB_MAC_FORCE_CTRL_REG,
1095 BIT(port), BIT(port));
1096 if (ret) {
1097 dev_err(priv->dev, "failed to force 1Gbit on CPU port\n");
1098 return;
1099 }
1100
1101 ret = regmap_update_bits(priv->map, RTL8366RB_PAACR2,
1102 0xFF00U,
1103 RTL8366RB_PAACR_CPU_PORT << 8);
1104 if (ret) {
1105 dev_err(priv->dev, "failed to set PAACR on CPU port\n");
1106 return;
1107 }
1108
1109 /* Enable the CPU port */
1110 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1111 0);
1112 if (ret) {
1113 dev_err(priv->dev, "failed to enable the CPU port\n");
1114 return;
1115 }
1116 }
1117
1118 static void
rtl8366rb_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)1119 rtl8366rb_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode,
1120 phy_interface_t interface)
1121 {
1122 struct realtek_priv *priv = ds->priv;
1123 int ret;
1124
1125 if (port != priv->cpu_port)
1126 return;
1127
1128 dev_dbg(priv->dev, "MAC link down on CPU port (%d)\n", port);
1129
1130 /* Disable the CPU port */
1131 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1132 BIT(port));
1133 if (ret) {
1134 dev_err(priv->dev, "failed to disable the CPU port\n");
1135 return;
1136 }
1137 }
1138
1139 static int
rtl8366rb_port_enable(struct dsa_switch * ds,int port,struct phy_device * phy)1140 rtl8366rb_port_enable(struct dsa_switch *ds, int port,
1141 struct phy_device *phy)
1142 {
1143 struct realtek_priv *priv = ds->priv;
1144 int ret;
1145
1146 dev_dbg(priv->dev, "enable port %d\n", port);
1147 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1148 0);
1149 if (ret)
1150 return ret;
1151
1152 return 0;
1153 }
1154
1155 static void
rtl8366rb_port_disable(struct dsa_switch * ds,int port)1156 rtl8366rb_port_disable(struct dsa_switch *ds, int port)
1157 {
1158 struct realtek_priv *priv = ds->priv;
1159 int ret;
1160
1161 dev_dbg(priv->dev, "disable port %d\n", port);
1162 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1163 BIT(port));
1164 if (ret)
1165 return;
1166 }
1167
1168 static int
rtl8366rb_port_bridge_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)1169 rtl8366rb_port_bridge_join(struct dsa_switch *ds, int port,
1170 struct dsa_bridge bridge,
1171 bool *tx_fwd_offload,
1172 struct netlink_ext_ack *extack)
1173 {
1174 struct realtek_priv *priv = ds->priv;
1175 unsigned int port_bitmap = 0;
1176 int ret, i;
1177
1178 /* Loop over all other ports than the current one */
1179 for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {
1180 /* Current port handled last */
1181 if (i == port)
1182 continue;
1183 /* Not on this bridge */
1184 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1185 continue;
1186 /* Join this port to each other port on the bridge */
1187 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i),
1188 RTL8366RB_PORT_ISO_PORTS(BIT(port)),
1189 RTL8366RB_PORT_ISO_PORTS(BIT(port)));
1190 if (ret)
1191 dev_err(priv->dev, "failed to join port %d\n", port);
1192
1193 port_bitmap |= BIT(i);
1194 }
1195
1196 /* Set the bits for the ports we can access */
1197 return regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port),
1198 RTL8366RB_PORT_ISO_PORTS(port_bitmap),
1199 RTL8366RB_PORT_ISO_PORTS(port_bitmap));
1200 }
1201
1202 static void
rtl8366rb_port_bridge_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)1203 rtl8366rb_port_bridge_leave(struct dsa_switch *ds, int port,
1204 struct dsa_bridge bridge)
1205 {
1206 struct realtek_priv *priv = ds->priv;
1207 unsigned int port_bitmap = 0;
1208 int ret, i;
1209
1210 /* Loop over all other ports than this one */
1211 for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {
1212 /* Current port handled last */
1213 if (i == port)
1214 continue;
1215 /* Not on this bridge */
1216 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1217 continue;
1218 /* Remove this port from any other port on the bridge */
1219 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i),
1220 RTL8366RB_PORT_ISO_PORTS(BIT(port)), 0);
1221 if (ret)
1222 dev_err(priv->dev, "failed to leave port %d\n", port);
1223
1224 port_bitmap |= BIT(i);
1225 }
1226
1227 /* Clear the bits for the ports we can not access, leave ourselves */
1228 regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port),
1229 RTL8366RB_PORT_ISO_PORTS(port_bitmap), 0);
1230 }
1231
1232 /**
1233 * rtl8366rb_drop_untagged() - make the switch drop untagged and C-tagged frames
1234 * @priv: SMI state container
1235 * @port: the port to drop untagged and C-tagged frames on
1236 * @drop: whether to drop or pass untagged and C-tagged frames
1237 *
1238 * Return: zero for success, a negative number on error.
1239 */
rtl8366rb_drop_untagged(struct realtek_priv * priv,int port,bool drop)1240 static int rtl8366rb_drop_untagged(struct realtek_priv *priv, int port, bool drop)
1241 {
1242 return regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG,
1243 RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port),
1244 drop ? RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) : 0);
1245 }
1246
rtl8366rb_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct netlink_ext_ack * extack)1247 static int rtl8366rb_vlan_filtering(struct dsa_switch *ds, int port,
1248 bool vlan_filtering,
1249 struct netlink_ext_ack *extack)
1250 {
1251 struct realtek_priv *priv = ds->priv;
1252 struct rtl8366rb *rb;
1253 int ret;
1254
1255 rb = priv->chip_data;
1256
1257 dev_dbg(priv->dev, "port %d: %s VLAN filtering\n", port,
1258 vlan_filtering ? "enable" : "disable");
1259
1260 /* If the port is not in the member set, the frame will be dropped */
1261 ret = regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,
1262 BIT(port), vlan_filtering ? BIT(port) : 0);
1263 if (ret)
1264 return ret;
1265
1266 /* If VLAN filtering is enabled and PVID is also enabled, we must
1267 * not drop any untagged or C-tagged frames. If we turn off VLAN
1268 * filtering on a port, we need to accept any frames.
1269 */
1270 if (vlan_filtering)
1271 ret = rtl8366rb_drop_untagged(priv, port, !rb->pvid_enabled[port]);
1272 else
1273 ret = rtl8366rb_drop_untagged(priv, port, false);
1274
1275 return ret;
1276 }
1277
1278 static int
rtl8366rb_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)1279 rtl8366rb_port_pre_bridge_flags(struct dsa_switch *ds, int port,
1280 struct switchdev_brport_flags flags,
1281 struct netlink_ext_ack *extack)
1282 {
1283 /* We support enabling/disabling learning */
1284 if (flags.mask & ~(BR_LEARNING))
1285 return -EINVAL;
1286
1287 return 0;
1288 }
1289
1290 static int
rtl8366rb_port_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)1291 rtl8366rb_port_bridge_flags(struct dsa_switch *ds, int port,
1292 struct switchdev_brport_flags flags,
1293 struct netlink_ext_ack *extack)
1294 {
1295 struct realtek_priv *priv = ds->priv;
1296 int ret;
1297
1298 if (flags.mask & BR_LEARNING) {
1299 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL,
1300 BIT(port),
1301 (flags.val & BR_LEARNING) ? 0 : BIT(port));
1302 if (ret)
1303 return ret;
1304 }
1305
1306 return 0;
1307 }
1308
1309 static void
rtl8366rb_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)1310 rtl8366rb_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1311 {
1312 struct realtek_priv *priv = ds->priv;
1313 u32 val;
1314 int i;
1315
1316 switch (state) {
1317 case BR_STATE_DISABLED:
1318 val = RTL8366RB_STP_STATE_DISABLED;
1319 break;
1320 case BR_STATE_BLOCKING:
1321 case BR_STATE_LISTENING:
1322 val = RTL8366RB_STP_STATE_BLOCKING;
1323 break;
1324 case BR_STATE_LEARNING:
1325 val = RTL8366RB_STP_STATE_LEARNING;
1326 break;
1327 case BR_STATE_FORWARDING:
1328 val = RTL8366RB_STP_STATE_FORWARDING;
1329 break;
1330 default:
1331 dev_err(priv->dev, "unknown bridge state requested\n");
1332 return;
1333 }
1334
1335 /* Set the same status for the port on all the FIDs */
1336 for (i = 0; i < RTL8366RB_NUM_FIDS; i++) {
1337 regmap_update_bits(priv->map, RTL8366RB_STP_STATE_BASE + i,
1338 RTL8366RB_STP_STATE_MASK(port),
1339 RTL8366RB_STP_STATE(port, val));
1340 }
1341 }
1342
1343 static void
rtl8366rb_port_fast_age(struct dsa_switch * ds,int port)1344 rtl8366rb_port_fast_age(struct dsa_switch *ds, int port)
1345 {
1346 struct realtek_priv *priv = ds->priv;
1347
1348 /* This will age out any learned L2 entries */
1349 regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL,
1350 BIT(port), BIT(port));
1351 /* Restore the normal state of things */
1352 regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL,
1353 BIT(port), 0);
1354 }
1355
rtl8366rb_change_mtu(struct dsa_switch * ds,int port,int new_mtu)1356 static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1357 {
1358 struct realtek_priv *priv = ds->priv;
1359 struct rtl8366rb *rb;
1360 unsigned int max_mtu;
1361 u32 len;
1362 int i;
1363
1364 /* Cache the per-port MTU setting */
1365 rb = priv->chip_data;
1366 rb->max_mtu[port] = new_mtu;
1367
1368 /* Roof out the MTU for the entire switch to the greatest
1369 * common denominator: the biggest set for any one port will
1370 * be the biggest MTU for the switch.
1371 *
1372 * The first setting, 1522 bytes, is max IP packet 1500 bytes,
1373 * plus ethernet header, 1518 bytes, plus CPU tag, 4 bytes.
1374 * This function should consider the parameter an SDU, so the
1375 * MTU passed for this setting is 1518 bytes. The same logic
1376 * of subtracting the DSA tag of 4 bytes apply to the other
1377 * settings.
1378 */
1379 max_mtu = 1518;
1380 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
1381 if (rb->max_mtu[i] > max_mtu)
1382 max_mtu = rb->max_mtu[i];
1383 }
1384 if (max_mtu <= 1518)
1385 len = RTL8366RB_SGCR_MAX_LENGTH_1522;
1386 else if (max_mtu > 1518 && max_mtu <= 1532)
1387 len = RTL8366RB_SGCR_MAX_LENGTH_1536;
1388 else if (max_mtu > 1532 && max_mtu <= 1548)
1389 len = RTL8366RB_SGCR_MAX_LENGTH_1552;
1390 else
1391 len = RTL8366RB_SGCR_MAX_LENGTH_16000;
1392
1393 return regmap_update_bits(priv->map, RTL8366RB_SGCR,
1394 RTL8366RB_SGCR_MAX_LENGTH_MASK,
1395 len);
1396 }
1397
rtl8366rb_max_mtu(struct dsa_switch * ds,int port)1398 static int rtl8366rb_max_mtu(struct dsa_switch *ds, int port)
1399 {
1400 /* The max MTU is 16000 bytes, so we subtract the CPU tag
1401 * and the max presented to the system is 15996 bytes.
1402 */
1403 return 15996;
1404 }
1405
rtl8366rb_get_vlan_4k(struct realtek_priv * priv,u32 vid,struct rtl8366_vlan_4k * vlan4k)1406 static int rtl8366rb_get_vlan_4k(struct realtek_priv *priv, u32 vid,
1407 struct rtl8366_vlan_4k *vlan4k)
1408 {
1409 u32 data[3];
1410 int ret;
1411 int i;
1412
1413 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
1414
1415 if (vid >= RTL8366RB_NUM_VIDS)
1416 return -EINVAL;
1417
1418 /* write VID */
1419 ret = regmap_write(priv->map, RTL8366RB_VLAN_TABLE_WRITE_BASE,
1420 vid & RTL8366RB_VLAN_VID_MASK);
1421 if (ret)
1422 return ret;
1423
1424 /* write table access control word */
1425 ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1426 RTL8366RB_TABLE_VLAN_READ_CTRL);
1427 if (ret)
1428 return ret;
1429
1430 for (i = 0; i < 3; i++) {
1431 ret = regmap_read(priv->map,
1432 RTL8366RB_VLAN_TABLE_READ_BASE + i,
1433 &data[i]);
1434 if (ret)
1435 return ret;
1436 }
1437
1438 vlan4k->vid = vid;
1439 vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1440 RTL8366RB_VLAN_UNTAG_MASK;
1441 vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1442 vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1443
1444 return 0;
1445 }
1446
rtl8366rb_set_vlan_4k(struct realtek_priv * priv,const struct rtl8366_vlan_4k * vlan4k)1447 static int rtl8366rb_set_vlan_4k(struct realtek_priv *priv,
1448 const struct rtl8366_vlan_4k *vlan4k)
1449 {
1450 u32 data[3];
1451 int ret;
1452 int i;
1453
1454 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
1455 vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||
1456 vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1457 vlan4k->fid > RTL8366RB_FIDMAX)
1458 return -EINVAL;
1459
1460 data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
1461 data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
1462 ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1463 RTL8366RB_VLAN_UNTAG_SHIFT);
1464 data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
1465
1466 for (i = 0; i < 3; i++) {
1467 ret = regmap_write(priv->map,
1468 RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
1469 data[i]);
1470 if (ret)
1471 return ret;
1472 }
1473
1474 /* write table access control word */
1475 ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1476 RTL8366RB_TABLE_VLAN_WRITE_CTRL);
1477
1478 return ret;
1479 }
1480
rtl8366rb_get_vlan_mc(struct realtek_priv * priv,u32 index,struct rtl8366_vlan_mc * vlanmc)1481 static int rtl8366rb_get_vlan_mc(struct realtek_priv *priv, u32 index,
1482 struct rtl8366_vlan_mc *vlanmc)
1483 {
1484 u32 data[3];
1485 int ret;
1486 int i;
1487
1488 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
1489
1490 if (index >= RTL8366RB_NUM_VLANS)
1491 return -EINVAL;
1492
1493 for (i = 0; i < 3; i++) {
1494 ret = regmap_read(priv->map,
1495 RTL8366RB_VLAN_MC_BASE(index) + i,
1496 &data[i]);
1497 if (ret)
1498 return ret;
1499 }
1500
1501 vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
1502 vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
1503 RTL8366RB_VLAN_PRIORITY_MASK;
1504 vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1505 RTL8366RB_VLAN_UNTAG_MASK;
1506 vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1507 vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1508
1509 return 0;
1510 }
1511
rtl8366rb_set_vlan_mc(struct realtek_priv * priv,u32 index,const struct rtl8366_vlan_mc * vlanmc)1512 static int rtl8366rb_set_vlan_mc(struct realtek_priv *priv, u32 index,
1513 const struct rtl8366_vlan_mc *vlanmc)
1514 {
1515 u32 data[3];
1516 int ret;
1517 int i;
1518
1519 if (index >= RTL8366RB_NUM_VLANS ||
1520 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
1521 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
1522 vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||
1523 vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1524 vlanmc->fid > RTL8366RB_FIDMAX)
1525 return -EINVAL;
1526
1527 data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
1528 ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
1529 RTL8366RB_VLAN_PRIORITY_SHIFT);
1530 data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
1531 ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1532 RTL8366RB_VLAN_UNTAG_SHIFT);
1533 data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
1534
1535 for (i = 0; i < 3; i++) {
1536 ret = regmap_write(priv->map,
1537 RTL8366RB_VLAN_MC_BASE(index) + i,
1538 data[i]);
1539 if (ret)
1540 return ret;
1541 }
1542
1543 return 0;
1544 }
1545
rtl8366rb_get_mc_index(struct realtek_priv * priv,int port,int * val)1546 static int rtl8366rb_get_mc_index(struct realtek_priv *priv, int port, int *val)
1547 {
1548 u32 data;
1549 int ret;
1550
1551 if (port >= priv->num_ports)
1552 return -EINVAL;
1553
1554 ret = regmap_read(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1555 &data);
1556 if (ret)
1557 return ret;
1558
1559 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
1560 RTL8366RB_PORT_VLAN_CTRL_MASK;
1561
1562 return 0;
1563 }
1564
rtl8366rb_set_mc_index(struct realtek_priv * priv,int port,int index)1565 static int rtl8366rb_set_mc_index(struct realtek_priv *priv, int port, int index)
1566 {
1567 struct rtl8366rb *rb;
1568 bool pvid_enabled;
1569 int ret;
1570
1571 rb = priv->chip_data;
1572 pvid_enabled = !!index;
1573
1574 if (port >= priv->num_ports || index >= RTL8366RB_NUM_VLANS)
1575 return -EINVAL;
1576
1577 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1578 RTL8366RB_PORT_VLAN_CTRL_MASK <<
1579 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
1580 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
1581 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
1582 if (ret)
1583 return ret;
1584
1585 rb->pvid_enabled[port] = pvid_enabled;
1586
1587 /* If VLAN filtering is enabled and PVID is also enabled, we must
1588 * not drop any untagged or C-tagged frames. Make sure to update the
1589 * filtering setting.
1590 */
1591 if (dsa_port_is_vlan_filtering(dsa_to_port(priv->ds, port)))
1592 ret = rtl8366rb_drop_untagged(priv, port, !pvid_enabled);
1593
1594 return ret;
1595 }
1596
rtl8366rb_is_vlan_valid(struct realtek_priv * priv,unsigned int vlan)1597 static bool rtl8366rb_is_vlan_valid(struct realtek_priv *priv, unsigned int vlan)
1598 {
1599 unsigned int max = RTL8366RB_NUM_VLANS - 1;
1600
1601 if (priv->vlan4k_enabled)
1602 max = RTL8366RB_NUM_VIDS - 1;
1603
1604 if (vlan > max)
1605 return false;
1606
1607 return true;
1608 }
1609
rtl8366rb_enable_vlan(struct realtek_priv * priv,bool enable)1610 static int rtl8366rb_enable_vlan(struct realtek_priv *priv, bool enable)
1611 {
1612 dev_dbg(priv->dev, "%s VLAN\n", enable ? "enable" : "disable");
1613 return regmap_update_bits(priv->map,
1614 RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
1615 enable ? RTL8366RB_SGCR_EN_VLAN : 0);
1616 }
1617
rtl8366rb_enable_vlan4k(struct realtek_priv * priv,bool enable)1618 static int rtl8366rb_enable_vlan4k(struct realtek_priv *priv, bool enable)
1619 {
1620 dev_dbg(priv->dev, "%s VLAN 4k\n", enable ? "enable" : "disable");
1621 return regmap_update_bits(priv->map, RTL8366RB_SGCR,
1622 RTL8366RB_SGCR_EN_VLAN_4KTB,
1623 enable ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
1624 }
1625
rtl8366rb_phy_read(struct realtek_priv * priv,int phy,int regnum)1626 static int rtl8366rb_phy_read(struct realtek_priv *priv, int phy, int regnum)
1627 {
1628 u32 val;
1629 u32 reg;
1630 int ret;
1631
1632 if (phy > RTL8366RB_PHY_NO_MAX)
1633 return -EINVAL;
1634
1635 mutex_lock(&priv->map_lock);
1636
1637 ret = regmap_write(priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG,
1638 RTL8366RB_PHY_CTRL_READ);
1639 if (ret)
1640 goto out;
1641
1642 reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;
1643
1644 ret = regmap_write(priv->map_nolock, reg, 0);
1645 if (ret) {
1646 dev_err(priv->dev,
1647 "failed to write PHY%d reg %04x @ %04x, ret %d\n",
1648 phy, regnum, reg, ret);
1649 goto out;
1650 }
1651
1652 ret = regmap_read(priv->map_nolock, RTL8366RB_PHY_ACCESS_DATA_REG,
1653 &val);
1654 if (ret)
1655 goto out;
1656
1657 ret = val;
1658
1659 dev_dbg(priv->dev, "read PHY%d register 0x%04x @ %08x, val <- %04x\n",
1660 phy, regnum, reg, val);
1661
1662 out:
1663 mutex_unlock(&priv->map_lock);
1664
1665 return ret;
1666 }
1667
rtl8366rb_phy_write(struct realtek_priv * priv,int phy,int regnum,u16 val)1668 static int rtl8366rb_phy_write(struct realtek_priv *priv, int phy, int regnum,
1669 u16 val)
1670 {
1671 u32 reg;
1672 int ret;
1673
1674 if (phy > RTL8366RB_PHY_NO_MAX)
1675 return -EINVAL;
1676
1677 mutex_lock(&priv->map_lock);
1678
1679 ret = regmap_write(priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG,
1680 RTL8366RB_PHY_CTRL_WRITE);
1681 if (ret)
1682 goto out;
1683
1684 reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;
1685
1686 dev_dbg(priv->dev, "write PHY%d register 0x%04x @ %04x, val -> %04x\n",
1687 phy, regnum, reg, val);
1688
1689 ret = regmap_write(priv->map_nolock, reg, val);
1690 if (ret)
1691 goto out;
1692
1693 out:
1694 mutex_unlock(&priv->map_lock);
1695
1696 return ret;
1697 }
1698
rtl8366rb_dsa_phy_read(struct dsa_switch * ds,int phy,int regnum)1699 static int rtl8366rb_dsa_phy_read(struct dsa_switch *ds, int phy, int regnum)
1700 {
1701 return rtl8366rb_phy_read(ds->priv, phy, regnum);
1702 }
1703
rtl8366rb_dsa_phy_write(struct dsa_switch * ds,int phy,int regnum,u16 val)1704 static int rtl8366rb_dsa_phy_write(struct dsa_switch *ds, int phy, int regnum,
1705 u16 val)
1706 {
1707 return rtl8366rb_phy_write(ds->priv, phy, regnum, val);
1708 }
1709
rtl8366rb_reset_chip(struct realtek_priv * priv)1710 static int rtl8366rb_reset_chip(struct realtek_priv *priv)
1711 {
1712 int timeout = 10;
1713 u32 val;
1714 int ret;
1715
1716 priv->write_reg_noack(priv, RTL8366RB_RESET_CTRL_REG,
1717 RTL8366RB_CHIP_CTRL_RESET_HW);
1718 do {
1719 usleep_range(20000, 25000);
1720 ret = regmap_read(priv->map, RTL8366RB_RESET_CTRL_REG, &val);
1721 if (ret)
1722 return ret;
1723
1724 if (!(val & RTL8366RB_CHIP_CTRL_RESET_HW))
1725 break;
1726 } while (--timeout);
1727
1728 if (!timeout) {
1729 dev_err(priv->dev, "timeout waiting for the switch to reset\n");
1730 return -EIO;
1731 }
1732
1733 return 0;
1734 }
1735
rtl8366rb_detect(struct realtek_priv * priv)1736 static int rtl8366rb_detect(struct realtek_priv *priv)
1737 {
1738 struct device *dev = priv->dev;
1739 int ret;
1740 u32 val;
1741
1742 /* Detect device */
1743 ret = regmap_read(priv->map, 0x5c, &val);
1744 if (ret) {
1745 dev_err(dev, "can't get chip ID (%d)\n", ret);
1746 return ret;
1747 }
1748
1749 switch (val) {
1750 case 0x6027:
1751 dev_info(dev, "found an RTL8366S switch\n");
1752 dev_err(dev, "this switch is not yet supported, submit patches!\n");
1753 return -ENODEV;
1754 case 0x5937:
1755 dev_info(dev, "found an RTL8366RB switch\n");
1756 priv->cpu_port = RTL8366RB_PORT_NUM_CPU;
1757 priv->num_ports = RTL8366RB_NUM_PORTS;
1758 priv->num_vlan_mc = RTL8366RB_NUM_VLANS;
1759 priv->mib_counters = rtl8366rb_mib_counters;
1760 priv->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1761 break;
1762 default:
1763 dev_info(dev, "found an Unknown Realtek switch (id=0x%04x)\n",
1764 val);
1765 break;
1766 }
1767
1768 ret = rtl8366rb_reset_chip(priv);
1769 if (ret)
1770 return ret;
1771
1772 return 0;
1773 }
1774
1775 static const struct dsa_switch_ops rtl8366rb_switch_ops_smi = {
1776 .get_tag_protocol = rtl8366_get_tag_protocol,
1777 .setup = rtl8366rb_setup,
1778 .phylink_get_caps = rtl8366rb_phylink_get_caps,
1779 .phylink_mac_link_up = rtl8366rb_mac_link_up,
1780 .phylink_mac_link_down = rtl8366rb_mac_link_down,
1781 .get_strings = rtl8366_get_strings,
1782 .get_ethtool_stats = rtl8366_get_ethtool_stats,
1783 .get_sset_count = rtl8366_get_sset_count,
1784 .port_bridge_join = rtl8366rb_port_bridge_join,
1785 .port_bridge_leave = rtl8366rb_port_bridge_leave,
1786 .port_vlan_filtering = rtl8366rb_vlan_filtering,
1787 .port_vlan_add = rtl8366_vlan_add,
1788 .port_vlan_del = rtl8366_vlan_del,
1789 .port_enable = rtl8366rb_port_enable,
1790 .port_disable = rtl8366rb_port_disable,
1791 .port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags,
1792 .port_bridge_flags = rtl8366rb_port_bridge_flags,
1793 .port_stp_state_set = rtl8366rb_port_stp_state_set,
1794 .port_fast_age = rtl8366rb_port_fast_age,
1795 .port_change_mtu = rtl8366rb_change_mtu,
1796 .port_max_mtu = rtl8366rb_max_mtu,
1797 };
1798
1799 static const struct dsa_switch_ops rtl8366rb_switch_ops_mdio = {
1800 .get_tag_protocol = rtl8366_get_tag_protocol,
1801 .setup = rtl8366rb_setup,
1802 .phy_read = rtl8366rb_dsa_phy_read,
1803 .phy_write = rtl8366rb_dsa_phy_write,
1804 .phylink_get_caps = rtl8366rb_phylink_get_caps,
1805 .phylink_mac_link_up = rtl8366rb_mac_link_up,
1806 .phylink_mac_link_down = rtl8366rb_mac_link_down,
1807 .get_strings = rtl8366_get_strings,
1808 .get_ethtool_stats = rtl8366_get_ethtool_stats,
1809 .get_sset_count = rtl8366_get_sset_count,
1810 .port_bridge_join = rtl8366rb_port_bridge_join,
1811 .port_bridge_leave = rtl8366rb_port_bridge_leave,
1812 .port_vlan_filtering = rtl8366rb_vlan_filtering,
1813 .port_vlan_add = rtl8366_vlan_add,
1814 .port_vlan_del = rtl8366_vlan_del,
1815 .port_enable = rtl8366rb_port_enable,
1816 .port_disable = rtl8366rb_port_disable,
1817 .port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags,
1818 .port_bridge_flags = rtl8366rb_port_bridge_flags,
1819 .port_stp_state_set = rtl8366rb_port_stp_state_set,
1820 .port_fast_age = rtl8366rb_port_fast_age,
1821 .port_change_mtu = rtl8366rb_change_mtu,
1822 .port_max_mtu = rtl8366rb_max_mtu,
1823 };
1824
1825 static const struct realtek_ops rtl8366rb_ops = {
1826 .detect = rtl8366rb_detect,
1827 .get_vlan_mc = rtl8366rb_get_vlan_mc,
1828 .set_vlan_mc = rtl8366rb_set_vlan_mc,
1829 .get_vlan_4k = rtl8366rb_get_vlan_4k,
1830 .set_vlan_4k = rtl8366rb_set_vlan_4k,
1831 .get_mc_index = rtl8366rb_get_mc_index,
1832 .set_mc_index = rtl8366rb_set_mc_index,
1833 .get_mib_counter = rtl8366rb_get_mib_counter,
1834 .is_vlan_valid = rtl8366rb_is_vlan_valid,
1835 .enable_vlan = rtl8366rb_enable_vlan,
1836 .enable_vlan4k = rtl8366rb_enable_vlan4k,
1837 .phy_read = rtl8366rb_phy_read,
1838 .phy_write = rtl8366rb_phy_write,
1839 };
1840
1841 const struct realtek_variant rtl8366rb_variant = {
1842 .ds_ops_smi = &rtl8366rb_switch_ops_smi,
1843 .ds_ops_mdio = &rtl8366rb_switch_ops_mdio,
1844 .ops = &rtl8366rb_ops,
1845 .clk_delay = 10,
1846 .cmd_read = 0xa9,
1847 .cmd_write = 0xa8,
1848 .chip_data_sz = sizeof(struct rtl8366rb),
1849 };
1850 EXPORT_SYMBOL_GPL(rtl8366rb_variant);
1851
1852 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
1853 MODULE_DESCRIPTION("Driver for RTL8366RB ethernet switch");
1854 MODULE_LICENSE("GPL");
1855