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Searched refs:RST_BUS_EHCI0 (Results 1 – 25 of 37) sorted by relevance

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/openbmc/u-boot/include/dt-bindings/reset/
H A Dsun8i-v3s-ccu.h63 #define RST_BUS_EHCI0 18 macro
H A Dsun8i-a83t-ccu.h66 #define RST_BUS_EHCI0 18 macro
H A Dsun50i-a64-ccu.h65 #define RST_BUS_EHCI0 19 macro
H A Dsun8i-h3-ccu.h66 #define RST_BUS_EHCI0 18 macro
H A Dsun50i-h6-ccu.h59 #define RST_BUS_EHCI0 50 macro
H A Dsun8i-r40-ccu.h71 #define RST_BUS_EHCI0 23 macro
/openbmc/linux/include/dt-bindings/reset/
H A Dsun8i-v3s-ccu.h63 #define RST_BUS_EHCI0 18 macro
H A Dsun8i-a83t-ccu.h66 #define RST_BUS_EHCI0 18 macro
H A Dsun50i-a64-ccu.h65 #define RST_BUS_EHCI0 19 macro
H A Dsun8i-h3-ccu.h66 #define RST_BUS_EHCI0 18 macro
H A Dsun50i-h616-ccu.h55 #define RST_BUS_EHCI0 46 macro
H A Dsun50i-a100-ccu.h55 #define RST_BUS_EHCI0 46 macro
H A Dsun50i-h6-ccu.h59 #define RST_BUS_EHCI0 50 macro
H A Dsun20i-d1-ccu.h54 #define RST_BUS_EHCI0 44 macro
H A Dsun8i-r40-ccu.h71 #define RST_BUS_EHCI0 23 macro
/openbmc/u-boot/drivers/clk/sunxi/
H A Dclk_a83t.c55 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)),
H A Dclk_a64.c57 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)),
H A Dclk_h3.c65 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)),
H A Dclk_r40.c71 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)),
/openbmc/linux/drivers/clk/sunxi-ng/
H A Dccu-sun8i-v3s.c662 [RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
697 [RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
H A Dccu-sun8i-h3.c900 [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
963 [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
H A Dccu-sun8i-a83t.c819 [RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
H A Dccu-sun50i-a64.c881 [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
/openbmc/u-boot/arch/arm/dts/
H A Dsunxi-h3-h5.dtsi292 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
302 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsunxi-h3-h5.dtsi304 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
316 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;

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