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Searched refs:RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h6339 #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK … macro
H A Dgc_9_1_sh_mask.h6100 #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK … macro
H A Dgc_9_2_1_sh_mask.h5977 #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK … macro
H A Dgc_9_4_3_sh_mask.h8472 #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK … macro
H A Dgc_9_4_2_sh_mask.h23163 #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK … macro
H A Dgc_11_0_0_sh_mask.h10368 #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK … macro
H A Dgc_10_1_0_sh_mask.h11379 #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK … macro
H A Dgc_11_0_3_sh_mask.h12184 #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK … macro
H A Dgc_10_3_0_sh_mask.h10935 #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK … macro