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Searched refs:RLC_GPM_PERF_COUNT_1__ENABLE_MASK (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h8131 #define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x100000 macro
H A Dgfx_8_0_sh_mask.h9043 #define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x100000 macro
H A Dgfx_8_1_sh_mask.h9583 #define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x100000 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h19835 #define RLC_GPM_PERF_COUNT_1__ENABLE_MASK … macro
H A Dgc_9_2_1_sh_mask.h21073 #define RLC_GPM_PERF_COUNT_1__ENABLE_MASK … macro
H A Dgc_9_1_sh_mask.h21146 #define RLC_GPM_PERF_COUNT_1__ENABLE_MASK … macro
H A Dgc_9_4_3_sh_mask.h23201 #define RLC_GPM_PERF_COUNT_1__ENABLE_MASK … macro
H A Dgc_9_4_2_sh_mask.h13279 #define RLC_GPM_PERF_COUNT_1__ENABLE_MASK … macro
H A Dgc_11_0_0_sh_mask.h27192 #define RLC_GPM_PERF_COUNT_1__ENABLE_MASK … macro
H A Dgc_11_0_3_sh_mask.h29713 #define RLC_GPM_PERF_COUNT_1__ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h27811 #define RLC_GPM_PERF_COUNT_1__ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h26090 #define RLC_GPM_PERF_COUNT_1__ENABLE_MASK … macro