Home
last modified time | relevance | path

Searched refs:RLC_CNTL__RLC_ENABLE_F32_MASK (Results 1 – 19 of 19) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c2431 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { in gfx_v6_0_halt_rlc()
2432 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; in gfx_v6_0_halt_rlc()
2451 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); in gfx_v6_0_rlc_start()
H A Dgfx_v7_0.c3339 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { in gfx_v7_0_halt_rlc()
3342 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; in gfx_v7_0_halt_rlc()
3417 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); in gfx_v7_0_rlc_start()
H A Dgfx_v9_4_3.c1057 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) in gfx_v9_4_3_is_rlc_enabled()
H A Dgfx_v8_0.c5532 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) in gfx_v8_0_is_rlc_enabled()
H A Dgfx_v9_0.c4611 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) in gfx_v9_0_is_rlc_enabled()
H A Dgfx_v10_0.c5456 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { in gfx_v10_0_rlc_backdoor_autoload_enable()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h7094 #define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L macro
H A Dgfx_7_2_sh_mask.h7667 #define RLC_CNTL__RLC_ENABLE_F32_MASK 0x1 macro
H A Dgfx_8_0_sh_mask.h8477 #define RLC_CNTL__RLC_ENABLE_F32_MASK 0x1 macro
H A Dgfx_8_1_sh_mask.h9031 #define RLC_CNTL__RLC_ENABLE_F32_MASK 0x1 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h22729 #define RLC_CNTL__RLC_ENABLE_F32_MASK macro
H A Dgc_9_2_1_sh_mask.h24023 #define RLC_CNTL__RLC_ENABLE_F32_MASK macro
H A Dgc_9_1_sh_mask.h24020 #define RLC_CNTL__RLC_ENABLE_F32_MASK macro
H A Dgc_9_4_3_sh_mask.h26277 #define RLC_CNTL__RLC_ENABLE_F32_MASK macro
H A Dgc_9_4_2_sh_mask.h21497 #define RLC_CNTL__RLC_ENABLE_F32_MASK macro
H A Dgc_11_0_0_sh_mask.h34026 #define RLC_CNTL__RLC_ENABLE_F32_MASK macro
H A Dgc_11_0_3_sh_mask.h37265 #define RLC_CNTL__RLC_ENABLE_F32_MASK macro
H A Dgc_10_1_0_sh_mask.h33196 #define RLC_CNTL__RLC_ENABLE_F32_MASK macro
H A Dgc_10_3_0_sh_mask.h32128 #define RLC_CNTL__RLC_ENABLE_F32_MASK macro