Searched refs:RK3328_PRE_PLL_PCLK_DIV_C (Results 1 – 1 of 1) sorted by relevance
164 #define RK3328_PRE_PLL_PCLK_DIV_C(x) UPDATE(x, 6, 5) macro962 inno_write(inno, 0xa6, RK3328_PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) | in inno_hdmi_phy_rk3328_clk_set_rate()