Searched refs:RK3328_PRE_PLL_PCLK_DIV_A (Results 1 – 1 of 1) sorted by relevance
160 #define RK3328_PRE_PLL_PCLK_DIV_A(x) UPDATE(x, 4, 0) macro960 inno_write(inno, 0xa5, RK3328_PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a) | in inno_hdmi_phy_rk3328_clk_set_rate()