Home
last modified time | relevance | path

Searched refs:RISCV_PMU_EVENT_HW_CPU_CYCLES (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dpmu.c253 event_idx = RISCV_PMU_EVENT_HW_CPU_CYCLES; in riscv_pmu_ctr_monitor_cycles()
312 case RISCV_PMU_EVENT_HW_CPU_CYCLES: in riscv_pmu_update_event_map()
338 if (evt_idx != RISCV_PMU_EVENT_HW_CPU_CYCLES && in pmu_timer_trigger_irq()
381 pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_CPU_CYCLES); in riscv_pmu_timer_cb()
H A Dcpu.h749 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, enumerator