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Searched refs:RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dpmu.c315 case RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS: in riscv_pmu_update_event_map()
H A Dcpu.h752 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, enumerator
H A Dcpu_helper.c1281 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; in pmu_tlb_fill_incr_ctr()