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Searched refs:RISCV_IOMMU_TR_REQ_CTL_NW (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/riscv/
H A Driscv-iommu-bits.h194 #define RISCV_IOMMU_TR_REQ_CTL_NW BIT_ULL(3) macro
H A Driscv-iommu.c1805 .perm = ctrl & RISCV_IOMMU_TR_REQ_CTL_NW ? IOMMU_RO : IOMMU_RW, in riscv_iommu_process_dbg()