Home
last modified time | relevance | path

Searched refs:RISCV_IOMMU_REG_PQCSR (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/tests/qtest/
H A Driscv-iommu-test.c76 reg = riscv_iommu_read_reg32(r_iommu, RISCV_IOMMU_REG_PQCSR); in test_reg_reset()
195 reg = riscv_iommu_read_reg32(r_iommu, RISCV_IOMMU_REG_PQCSR); in test_iommu_init_queues()
197 riscv_iommu_write_reg32(r_iommu, RISCV_IOMMU_REG_PQCSR, reg); in test_iommu_init_queues()
199 qtest_wait_for_queue_active(r_iommu, RISCV_IOMMU_REG_PQCSR); in test_iommu_init_queues()
/openbmc/qemu/tests/qtest/libqos/
H A Driscv-iommu.h57 #define RISCV_IOMMU_REG_PQCSR 0x0050 macro
/openbmc/qemu/hw/riscv/
H A Driscv-iommu.c153 uint32_t ctrl = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_PQCSR); in riscv_iommu_pri()
168 riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_PQCSR, in riscv_iommu_pri()
174 riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_PQCSR, in riscv_iommu_pri()
1757 uint32_t ctrl_set = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_PQCSR); in riscv_iommu_process_pq_control()
1781 riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_PQCSR, ctrl_set, ctrl_clr); in riscv_iommu_process_pq_control()
1888 pqcsr = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_PQCSR); in riscv_iommu_update_ipsr()
1965 case RISCV_IOMMU_REG_PQCSR: in riscv_iommu_mmio_write()
2187 stl_le_p(&s->regs_wc[RISCV_IOMMU_REG_PQCSR], RISCV_IOMMU_PQCSR_PQMF | in riscv_iommu_realize()
2189 stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_PQCSR], RISCV_IOMMU_PQCSR_PQON | in riscv_iommu_realize()
H A Driscv-iommu-bits.h166 #define RISCV_IOMMU_REG_PQCSR 0x0050 macro