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Searched refs:RISCV_IOMMU_REG_IPSR (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/tests/qtest/libqos/
H A Driscv-iommu.h63 #define RISCV_IOMMU_REG_IPSR 0x0054 macro
/openbmc/qemu/tests/qtest/
H A Driscv-iommu-test.c87 reg = riscv_iommu_read_reg32(r_iommu, RISCV_IOMMU_REG_IPSR); in test_reg_reset()
/openbmc/qemu/hw/riscv/
H A Driscv-iommu-bits.h175 #define RISCV_IOMMU_REG_IPSR 0x0054 macro
H A Driscv-iommu.c105 ipsr = riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_IPSR, (1 << vec_type), 0); in riscv_iommu_notify()
1901 riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_IPSR, ipsr_set, ipsr_clr); in riscv_iommu_update_ipsr()
1971 case RISCV_IOMMU_REG_IPSR: in riscv_iommu_mmio_write()
2191 stl_le_p(&s->regs_wc[RISCV_IOMMU_REG_IPSR], ~0); in riscv_iommu_realize()