Home
last modified time | relevance | path

Searched refs:RISCV_IOMMU_REG_DDTP (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/tests/qtest/libqos/
H A Driscv-iommu.h40 #define RISCV_IOMMU_REG_DDTP 0x0010 macro
/openbmc/qemu/tests/qtest/
H A Driscv-iommu-test.c82 reg = riscv_iommu_read_reg32(r_iommu, RISCV_IOMMU_REG_DDTP); in test_reg_reset()
/openbmc/qemu/hw/riscv/
H A Driscv-iommu.c1502 uint64_t new_ddtp = riscv_iommu_reg_get64(s, RISCV_IOMMU_REG_DDTP); in riscv_iommu_process_ddtp()
1532 riscv_iommu_reg_set64(s, RISCV_IOMMU_REG_DDTP, new_ddtp); in riscv_iommu_process_ddtp()
1944 case RISCV_IOMMU_REG_DDTP: in riscv_iommu_mmio_write()
1945 case RISCV_IOMMU_REG_DDTP + 4: in riscv_iommu_mmio_write()
1947 regb = RISCV_IOMMU_REG_DDTP; in riscv_iommu_mmio_write()
2171 stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_DDTP], in riscv_iommu_realize()
2193 stq_le_p(&s->regs_rw[RISCV_IOMMU_REG_DDTP], s->ddtp); in riscv_iommu_realize()
H A Driscv-iommu-bits.h98 #define RISCV_IOMMU_REG_DDTP 0x0010 macro