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Searched refs:RISCV_IOMMU_QUEUE_INTR_ENABLE (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/tests/qtest/libqos/
H A Driscv-iommu.h32 #define RISCV_IOMMU_QUEUE_INTR_ENABLE BIT(1) macro
47 #define RISCV_IOMMU_CQCSR_CIE RISCV_IOMMU_QUEUE_INTR_ENABLE
53 #define RISCV_IOMMU_FQCSR_FIE RISCV_IOMMU_QUEUE_INTR_ENABLE
59 #define RISCV_IOMMU_PQCSR_PIE RISCV_IOMMU_QUEUE_INTR_ENABLE
/openbmc/qemu/hw/riscv/
H A Driscv-iommu-bits.h61 #define RISCV_IOMMU_QUEUE_INTR_ENABLE BIT(1) macro
148 #define RISCV_IOMMU_CQCSR_CIE RISCV_IOMMU_QUEUE_INTR_ENABLE
159 #define RISCV_IOMMU_FQCSR_FIE RISCV_IOMMU_QUEUE_INTR_ENABLE
168 #define RISCV_IOMMU_PQCSR_PIE RISCV_IOMMU_QUEUE_INTR_ENABLE